KR900008918A - 배선기판과 그 제조방법, 박막 캐리어, 반도체 장치 및 그 장착구조와 반도체 장치장착 방법 - Google Patents

배선기판과 그 제조방법, 박막 캐리어, 반도체 장치 및 그 장착구조와 반도체 장치장착 방법

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Publication number
KR900008918A
KR900008918A KR1019890016132A KR890016132A KR900008918A KR 900008918 A KR900008918 A KR 900008918A KR 1019890016132 A KR1019890016132 A KR 1019890016132A KR 890016132 A KR890016132 A KR 890016132A KR 900008918 A KR900008918 A KR 900008918A
Authority
KR
South Korea
Prior art keywords
semiconductor device
manufacturing
thin film
wiring substrate
film carrier
Prior art date
Application number
KR1019890016132A
Other languages
English (en)
Other versions
KR960006763B1 (ko
Inventor
마사까즈 스기모또
가즈오 오우찌
미끼오 아이자와
아쯔시 히노
가즈또 시노자끼
데쯔야 데라다
다까노리 미요시
무네까즈 다나까
쇼지 모리따
아마네 모찌즈끼
요시나리 다까야마
Original Assignee
닛또 덴꼬 가부시끼가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP28320788A external-priority patent/JPH0760840B2/ja
Priority claimed from JP1050792A external-priority patent/JP2815113B2/ja
Priority claimed from JP1050793A external-priority patent/JP2785832B2/ja
Priority claimed from JP1181272A external-priority patent/JP2634672B2/ja
Priority claimed from JP19768289A external-priority patent/JP2654191B2/ja
Priority claimed from JP19768089A external-priority patent/JP2654189B2/ja
Priority claimed from JP19768189A external-priority patent/JP2654190B2/ja
Priority claimed from JP1200847A external-priority patent/JP2808703B2/ja
Application filed by 닛또 덴꼬 가부시끼가이샤 filed Critical 닛또 덴꼬 가부시끼가이샤
Publication of KR900008918A publication Critical patent/KR900008918A/ko
Application granted granted Critical
Publication of KR960006763B1 publication Critical patent/KR960006763B1/ko

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/16Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/11Printed elements for providing electric connections to or between printed circuits
    • H05K1/111Pads for surface mounting, e.g. lay-out
    • H05K1/112Pads for surface mounting, e.g. lay-out directly combined with via connections
    • H05K1/113Via provided in pad; Pad over filled via
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4846Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486Via connections through the substrate with or without pins
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01014Silicon [Si]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01046Palladium [Pd]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3025Electromagnetic shielding
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/03Use of materials for the substrate
    • H05K1/0393Flexible materials
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01Dielectrics
    • H05K2201/0137Materials
    • H05K2201/0154Polyimide
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03Conductive materials
    • H05K2201/0332Structure of the conductor
    • H05K2201/0388Other aspects of conductors
    • H05K2201/0394Conductor crossing over a hole in the substrate or a gap between two separate substrate parts
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09209Shape and layout details of conductors
    • H05K2201/095Conductive through-holes or vias
    • H05K2201/09563Metal filled via
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09209Shape and layout details of conductors
    • H05K2201/09654Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/0979Redundant conductors or connections, i.e. more than one current path between two points
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/36Assembling printed circuits with other printed circuits
    • H05K3/361Assembling flexible printed circuits with other printed circuits
    • H05K3/363Assembling flexible printed circuits with other printed circuits by soldering
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42Plated through-holes or plated via connections
    • H05K3/423Plated through-holes or plated via connections characterised by electroplating method

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
KR1019890016132A 1988-11-09 1989-11-08 배선기판과 그 제조방법, 박막 캐리어, 반도체 장치 및 그 장착구조와 반도체 장치장착 방법 KR960006763B1 (ko)

Applications Claiming Priority (16)

Application Number Priority Date Filing Date Title
JP63-283207 1988-11-09
JP28320788A JPH0760840B2 (ja) 1988-11-09 1988-11-09 配線基板およびその製法
JP50,792 1989-03-01
JP1050792A JP2815113B2 (ja) 1989-03-01 1989-03-01 フィルムキャリアおよび半導体装置の製造方法
JP50,793 1989-03-01
JP1050793A JP2785832B2 (ja) 1989-03-01 1989-03-01 半導体装置の実装構造
JP1181272A JP2634672B2 (ja) 1989-07-13 1989-07-13 半導体装置
JP181,272 1989-07-14
JP19768289A JP2654191B2 (ja) 1989-07-28 1989-07-28 半導体装置の実装方法
JP197,582 1989-07-28
JP197,681 1989-07-28
JP19768089A JP2654189B2 (ja) 1989-07-28 1989-07-28 半導体装置の実装方法
JP197,680 1989-07-28
JP19768189A JP2654190B2 (ja) 1989-07-28 1989-07-28 半導体装置の実装方法
JP1200847A JP2808703B2 (ja) 1989-08-02 1989-08-02 フィルムキャリアおよび半導体装置
JP200,847 1989-08-02

Publications (2)

Publication Number Publication Date
KR900008918A true KR900008918A (ko) 1990-06-03
KR960006763B1 KR960006763B1 (ko) 1996-05-23

Family

ID=27572395

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019890016132A KR960006763B1 (ko) 1988-11-09 1989-11-08 배선기판과 그 제조방법, 박막 캐리어, 반도체 장치 및 그 장착구조와 반도체 장치장착 방법

Country Status (5)

Country Link
US (1) US5072289A (ko)
EP (1) EP0368262B1 (ko)
KR (1) KR960006763B1 (ko)
DE (1) DE68929282T2 (ko)
SG (1) SG49842A1 (ko)

Families Citing this family (75)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5640762A (en) 1988-09-30 1997-06-24 Micron Technology, Inc. Method and apparatus for manufacturing known good semiconductor die
US5634267A (en) * 1991-06-04 1997-06-03 Micron Technology, Inc. Method and apparatus for manufacturing known good semiconductor die
US4954878A (en) * 1989-06-29 1990-09-04 Digital Equipment Corp. Method of packaging and powering integrated circuit chips and the chip assembly formed thereby
JP3154713B2 (ja) * 1990-03-16 2001-04-09 株式会社リコー 異方性導電膜およびその製造方法
DE69233088T2 (de) * 1991-02-25 2003-12-24 Canon K.K., Tokio/Tokyo Elektrisches Verbindungsteil und sein Herstellungsverfahren
DE69216658T2 (de) * 1991-02-25 1997-08-07 Canon Kk Vorrichtung und Verfahren zur Verbindung elektrischer Bauelemente
JPH04301817A (ja) * 1991-03-29 1992-10-26 Rohm Co Ltd 液晶表示装置とその製造方法
US6998860B1 (en) 1991-06-04 2006-02-14 Micron Technology, Inc. Method for burn-in testing semiconductor dice
US5716218A (en) 1991-06-04 1998-02-10 Micron Technology, Inc. Process for manufacturing an interconnect for testing a semiconductor die
US5487999A (en) * 1991-06-04 1996-01-30 Micron Technology, Inc. Method for fabricating a penetration limited contact having a rough textured surface
US5302891A (en) * 1991-06-04 1994-04-12 Micron Technology, Inc. Discrete die burn-in for non-packaged die
US6219908B1 (en) 1991-06-04 2001-04-24 Micron Technology, Inc. Method and apparatus for manufacturing known good semiconductor die
US6340894B1 (en) 1991-06-04 2002-01-22 Micron Technology, Inc. Semiconductor testing apparatus including substrate with contact members and conductive polymer interconnect
US5559444A (en) * 1991-06-04 1996-09-24 Micron Technology, Inc. Method and apparatus for testing unpackaged semiconductor dice
US5578934A (en) * 1991-06-04 1996-11-26 Micron Technology, Inc. Method and apparatus for testing unpackaged semiconductor dice
US5678301A (en) * 1991-06-04 1997-10-21 Micron Technology, Inc. Method for forming an interconnect for testing unpackaged semiconductor dice
US5252850A (en) * 1992-01-27 1993-10-12 Photometrics Ltd. Apparatus for contouring a semiconductor, light responsive array with a prescribed physical profile
US5355019A (en) * 1992-03-04 1994-10-11 At&T Bell Laboratories Devices with tape automated bonding
US5751059A (en) * 1992-06-19 1998-05-12 Thomson-Csf Semiconducteurs Specifiques Pyroelectric sensor
US5596172A (en) * 1993-05-07 1997-01-21 Motorola, Inc. Planar encapsulation process
GB9318573D0 (en) * 1993-09-08 1993-10-27 Deas Alexander R Bonding process for producing multiple simultaneous connections between silicon di and a substrate
US5548091A (en) * 1993-10-26 1996-08-20 Tessera, Inc. Semiconductor chip connection components with adhesives and methods for bonding to the chip
US5434452A (en) * 1993-11-01 1995-07-18 Motorola, Inc. Z-axis compliant mechanical IC wiring substrate and method for making the same
US5734201A (en) * 1993-11-09 1998-03-31 Motorola, Inc. Low profile semiconductor device with like-sized chip and mounting substrate
US5454160A (en) * 1993-12-03 1995-10-03 Ncr Corporation Apparatus and method for stacking integrated circuit devices
US5455390A (en) * 1994-02-01 1995-10-03 Tessera, Inc. Microelectronics unit mounting with multiple lead bonding
US5917229A (en) * 1994-02-08 1999-06-29 Prolinx Labs Corporation Programmable/reprogrammable printed circuit board using fuse and/or antifuse as interconnect
US5513430A (en) * 1994-08-19 1996-05-07 Motorola, Inc. Method for manufacturing a probe
US5476818A (en) * 1994-08-19 1995-12-19 Motorola, Inc. Semiconductor structure and method of manufacture
US5962815A (en) 1995-01-18 1999-10-05 Prolinx Labs Corporation Antifuse interconnect between two conducting layers of a printed circuit board
KR100218996B1 (ko) * 1995-03-24 1999-09-01 모기 쥰이찌 반도체장치
JP3015712B2 (ja) * 1995-06-30 2000-03-06 日東電工株式会社 フィルムキャリアおよびそれを用いてなる半導体装置
WO1997011591A1 (en) * 1995-09-22 1997-03-27 Minnesota Mining And Manufacturing Company Flexible circuits with bumped interconnection capability
US5886877A (en) * 1995-10-13 1999-03-23 Meiko Electronics Co., Ltd. Circuit board, manufacturing method therefor, and bump-type contact head and semiconductor component packaging module using the circuit board
KR100201383B1 (ko) * 1995-10-19 1999-06-15 구본준 인터페이스 조립체를 구비한 유에프비지에이 패키지
JP2736042B2 (ja) * 1995-12-12 1998-04-02 山一電機株式会社 回路基板
WO1997027490A1 (en) * 1996-01-25 1997-07-31 General Dynamics Information Systems, Inc. Performing an operation on an integrated circuit
US5756370A (en) * 1996-02-08 1998-05-26 Micron Technology, Inc. Compliant contact system with alignment structure for testing unpackaged semiconductor dice
US6460245B1 (en) * 1996-03-07 2002-10-08 Tessera, Inc. Method of fabricating semiconductor chip assemblies
US5789271A (en) * 1996-03-18 1998-08-04 Micron Technology, Inc. Method for fabricating microbump interconnect for bare semiconductor dice
US5726075A (en) * 1996-03-29 1998-03-10 Micron Technology, Inc. Method for fabricating microbump interconnect for bare semiconductor dice
US5808360A (en) * 1996-05-15 1998-09-15 Micron Technology, Inc. Microbump interconnect for bore semiconductor dice
US5789278A (en) * 1996-07-30 1998-08-04 Micron Technology, Inc. Method for fabricating chip modules
JP3284262B2 (ja) * 1996-09-05 2002-05-20 セイコーエプソン株式会社 液晶表示装置及びそれを用いた電子機器
US6121689A (en) * 1997-07-21 2000-09-19 Miguel Albert Capote Semiconductor flip-chip package and method for the fabrication thereof
US5989935A (en) * 1996-11-19 1999-11-23 Texas Instruments Incorporated Column grid array for semiconductor packaging and method
US6133072A (en) 1996-12-13 2000-10-17 Tessera, Inc. Microelectronic connector with planar elastomer sockets
US5910354A (en) * 1997-03-04 1999-06-08 W.L. Gore & Associates, Inc. Metallurgical interconnect composite
US6025731A (en) 1997-03-21 2000-02-15 Micron Technology, Inc. Hybrid interconnect and system for testing semiconductor dice
US6016060A (en) * 1997-03-25 2000-01-18 Micron Technology, Inc. Method, apparatus and system for testing bumped semiconductor components
US5962921A (en) * 1997-03-31 1999-10-05 Micron Technology, Inc. Interconnect having recessed contact members with penetrating blades for testing semiconductor dice and packages with contact bumps
US5931685A (en) * 1997-06-02 1999-08-03 Micron Technology, Inc. Interconnect for making temporary electrical connections with bumped semiconductor components
WO1999021224A1 (fr) 1997-10-17 1999-04-29 Ibiden Co., Ltd. Substrat d'un boitier
JP2000106482A (ja) * 1998-07-29 2000-04-11 Sony Chem Corp フレキシブル基板製造方法
DE19912240A1 (de) * 1999-03-18 2000-09-28 Siemens Ag Bauelement und Verfahren zur Herstellung des Bauelementes
US6263566B1 (en) * 1999-05-03 2001-07-24 Micron Technology, Inc. Flexible semiconductor interconnect fabricated by backslide thinning
JP3973340B2 (ja) * 1999-10-05 2007-09-12 Necエレクトロニクス株式会社 半導体装置、配線基板、及び、それらの製造方法
AU2003233029A1 (en) * 2002-06-07 2003-12-22 Koninklijke Philips Electronics N.V. Method of manufacturing an electronic device
JP3935091B2 (ja) 2003-02-27 2007-06-20 浜松ホトニクス株式会社 半導体装置、及びそれを用いた放射線検出器
US7658994B2 (en) * 2003-12-30 2010-02-09 3M Innovative Properties Company Substrates and compounds bonded thereto
TWI255466B (en) * 2004-10-08 2006-05-21 Ind Tech Res Inst Polymer-matrix conductive film and method for fabricating the same
US20070103412A1 (en) * 2005-11-09 2007-05-10 Pao-Yun Tang Liquid crystal display having a voltage divider with a thermistor
JP5425404B2 (ja) * 2008-01-18 2014-02-26 東京エレクトロン株式会社 アモルファスカーボン膜の処理方法およびそれを用いた半導体装置の製造方法
EP2352168A1 (en) * 2008-11-25 2011-08-03 Sumitomo Bakelite Co., Ltd. Electronic component package and electronic component package manufacturing method
US8198131B2 (en) * 2009-11-18 2012-06-12 Advanced Semiconductor Engineering, Inc. Stackable semiconductor device packages
TWI408785B (zh) 2009-12-31 2013-09-11 Advanced Semiconductor Eng 半導體封裝結構
US8569894B2 (en) 2010-01-13 2013-10-29 Advanced Semiconductor Engineering, Inc. Semiconductor package with single sided substrate design and manufacturing methods thereof
TWI419283B (zh) 2010-02-10 2013-12-11 Advanced Semiconductor Eng 封裝結構
TWI411075B (zh) 2010-03-22 2013-10-01 Advanced Semiconductor Eng 半導體封裝件及其製造方法
US8624374B2 (en) 2010-04-02 2014-01-07 Advanced Semiconductor Engineering, Inc. Semiconductor device packages with fan-out and with connecting elements for stacking and manufacturing methods thereof
US8278746B2 (en) 2010-04-02 2012-10-02 Advanced Semiconductor Engineering, Inc. Semiconductor device packages including connecting elements
CN102986314B (zh) * 2010-07-06 2016-10-12 株式会社藤仓 层叠配线基板及其制造方法
TWI451546B (zh) 2010-10-29 2014-09-01 Advanced Semiconductor Eng 堆疊式封裝結構、其封裝結構及封裝結構之製造方法
US9171792B2 (en) 2011-02-28 2015-10-27 Advanced Semiconductor Engineering, Inc. Semiconductor device packages having a side-by-side device arrangement and stacking functionality
CN103402309B (zh) * 2013-07-31 2016-05-04 无锡市伟丰印刷机械厂 一种具有垂直支撑结构的印刷电路板弹性焊盘

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3868724A (en) * 1973-11-21 1975-02-25 Fairchild Camera Instr Co Multi-layer connecting structures for packaging semiconductor devices mounted on a flexible carrier
JPS6148952A (ja) * 1984-08-16 1986-03-10 Toshiba Corp 半導体装置
JPS61111561A (ja) * 1984-10-05 1986-05-29 Fujitsu Ltd 半導体装置
FR2584235B1 (fr) * 1985-06-26 1988-04-22 Bull Sa Procede de montage d'un circuit integre sur un support, dispositif en resultant et son application a une carte a microcircuits electroniques
US4926241A (en) * 1988-02-19 1990-05-15 Microelectronics And Computer Technology Corporation Flip substrate for chip mount

Also Published As

Publication number Publication date
DE68929282D1 (de) 2001-03-22
SG49842A1 (en) 1998-06-15
DE68929282T2 (de) 2001-06-07
KR960006763B1 (ko) 1996-05-23
EP0368262A3 (en) 1990-11-28
EP0368262B1 (en) 2001-02-14
US5072289A (en) 1991-12-10
EP0368262A2 (en) 1990-05-16

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