WO1997011591A1 - Flexible circuits with bumped interconnection capability - Google Patents

Flexible circuits with bumped interconnection capability

Info

Publication number
WO1997011591A1
WO1997011591A1 PCT/US1996/013122 US9613122W WO9711591A1 WO 1997011591 A1 WO1997011591 A1 WO 1997011591A1 US 9613122 W US9613122 W US 9613122W WO 9711591 A1 WO9711591 A1 WO 9711591A1
Authority
WO
WIPO (PCT)
Prior art keywords
bump
ofthe
conductive
copper
flexible circuit
Prior art date
Application number
PCT/US1996/013122
Other languages
French (fr)
Inventor
Gayle R. T. Schueller
Original Assignee
Minnesota Mining And Manufacturing Company
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Minnesota Mining And Manufacturing Company filed Critical Minnesota Mining And Manufacturing Company
Publication of WO1997011591A1 publication Critical patent/WO1997011591A1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4007—Surface contacts, e.g. bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0335—Layered conductors or foils
    • H05K2201/0347—Overplating, e.g. for reinforcing conductors or bumps; Plating over filled vias
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0335—Layered conductors or foils
    • H05K2201/0355—Metal foils
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0364—Conductor shape
    • H05K2201/0367—Metallic bump or raised conductor not used as solder bump
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0388—Other aspects of conductors
    • H05K2201/0394—Conductor crossing over a hole in the substrate or a gap between two separate substrate parts
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09372—Pads and lands
    • H05K2201/09481—Via in pad; Pad over filled via
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09563—Metal filled via
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/24—Reinforcing the conductive pattern
    • H05K3/241—Reinforcing the conductive pattern characterised by the electroplating method; means therefor, e.g. baths or apparatus
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/423—Plated through-holes or plated via connections characterised by electroplating method

Definitions

  • the invention provides flexible circuits capable of z-axis electrical interconnections at specific locations while retaining an insulating barrier over the remainder ofthe contacting surface, and a process for making such flexible circuits.
  • each circuit layer carries electrical connections or traces which are used to connect the various components ofthe board.
  • Multiple layer circuit boards must interconnect the various components, e.g., vias, bumps and the like.
  • Interconnection bumps are formed of a conductive material and protrude above the surface ofthe electrical insulating material. In forming such bumps, the height, shape and uniformity ofthe shape is critical to avoid crosstalk and other unwanted electrical phenomena.
  • bumped interconnection between flexible circuits have been disclosed.
  • the standard process has been an additive processes where the bump is formed by depositing successive layers of metal on a suitable substrate by electrodeposition, sputtering and the like.
  • Bumps made by this method are generally no more than 2.5 pm-3.5 pm in,height and rely on adhesion between the layers to remain anchored onto the circuit. At increased heights, delamination can be a problem.
  • U.S. Patent 5, 283,948 discloses bumps and a semi-additive method of manufacturing bumps using a support or base to provide mechanical interlock with the elevated connection means to prevent displacement ofthe connection. It is disclosed that such bumps may be made to have increased height without delaminating.
  • the circuitry is made on e.g., a steel mandrel having a Teflon pattem which allows plating ofa circuit on the mandrel surface.
  • a dielectric transfer laminate is 6.
  • blind via refers to a via which is not visible from the film side.
  • the present invention relates to the formation of flexible circuits having at least one interconnect bump.
  • the interconnect bump(s) have a rounded surface and a substantially uniform profile.
  • the flexible circuit may have one bump or a multiplicity of such bumps, which are positioned according to a predetermined pattern formed by photolithographic processes.
  • the interconnect bump(s) formed on these flexible circuits are rounded shaped with substantially uniform profiles.
  • the surface ofthe bump has a regular smooth shape without excessive variation in either direction.
  • the uniformity of the bumps results in improved surface planarity and improved electrical connections between multiple layers of circuits.
  • the uniformity also minimizes shorts in electrical circuit traces and other connective features.
  • the interconnect bumps are formed by plating with a conductive metal such as copper, tin, lead, nickel, gold, or alloys thereof, or alloys of such metals with other metals.
  • the interconnect bumps are rounded, and may be formed to a height up to 150 ⁇ m, and typically have a diameter of from 50 ⁇ m to 500 ⁇ m.
  • the interconnect bumps are formed by means of electroplating.
  • the electrolytic plating solution comprises at least one gelatinous brightening agent, preferably a sulfonium salt.
  • Such salts may be selected from sulfonium alkane sulfonates or sulfonium alkane carboxylates, including but not limited to N-cyclohexyl- 2-benzothiazole-sulfonium-l-propanesulfonate, bis (dimethylthiocarbamyl) sulfonium-1- propanesulfonate, and bis(dimethylthiocarbamyl) propane carboxylate.
  • Such salts may be added directly or in combination with other plating bath ingredients present in said bath.
  • the salts comprise from 0.0001 to 1.5 g/l, preferably from 0J g/l to 1.0 g/l.
  • the bath otherwise contains conventional materials for plating, that is, the metal salts, and the electrolytic solution therefore, e.g., copper sulfate, sulfuric acid, hydrochloric acid, and the like.
  • the bath may be operated at ambient or high temperatures. Additional
  • -4- a) providing a dielectric substrate having first and second opposing surfaces having at least one via extending through said first surface to said second surface, said vias defining a predetermined pattem, b) forming a dielectric composite by depositing a conductive metal to said first surface, and forming a conductive circuit pattem thereon, c) contacting a current-carrying electrode against said conductive circuit pattem, d) forming a conductive column in said via by electrolytic deposition of metal from an electrolytic plating solution, said electrolytic plating solution comprising from 5 ml/1 to 20 ml 1 ofa gelatinous brightening agent, e) continuing electrolytic deposition until at least one rounded interconnect bump is formed on said second surface, said bump having a substantially uniform profile.
  • a preferred method for making flexible circuits ofthe invention comprises steps for forming a conductive column in the via and for further forming the interconnect bumps wherein the electrolytic plating solution comprises from 5 ml/1 to 20 ml 1 ofa brightening agent selected from sulfonium salts.
  • resist and “photoresist” are synonymous and interchangeable.
  • pattern and “image” are used interchangeably to mean the configuration which is formed-by the exposure and development ofa photoresist.
  • the following terms have these meanings as used herein: 1.
  • the term “substantially uniform” means that a surface so described is smooth, and without variation greater than about 20%.
  • the term “profile” means an outline shape ofthe object.
  • substrate refers to the polymeric film layer ofthe flexible circuit.
  • dielectric composite means the polymeric film layer and the thin conductive metal layer deposited thereon. 5.
  • via means a channel which extends through the polymeric film layer ofthe dielectric composite. name Apical® D.
  • Other commercially available polyimide precursors include those available from DuPont under the trade name Pyralin®.
  • the substrate has deposited thereon a conductive metal layer to form the dielectric composite, which is then processed as described, infra, to form a flexible circuit.
  • the layer may be deposited through a variety of means including but not limited to electroless deposition, chemical vapor deposition, sputtering, lamination and other known methods.
  • Various conductive metals are useful as the thin conductive metal layer, e.g.,, copper, tin, lead, silver, gold, nickel, alloys thereof, or alloys of such metals with other metals. Copper, tin or nickel metallurgies are widely used for this layer. Trace metal circuitry may also be formed from any of these conductive metals.
  • Negative photoresists useful in processes ofthe invention include negative aqueous processible polymerizable photohardenable compositions such as those disclosed in U.S. Patent Nos. 3,469,982, 3,448,098, 3,867,153, and 3,526,504. Such photoresists include at least one polymer, additional crosslinkable monomeric units and a photoinitiator. Examples of polymers used in photoresists include copolymers of methyl methacrylate, ethyl acrylate and acrylic acid, copolymers of styrene and maleic anhydride isobutyl ester and the like. The crosslinkable monomeric units may be multiacrylates such as trimethylol propane triacrylate. Examples of some aqueous processible negative photoresists employed according to the present invention are from polymethyl-methacrylates such as those commercially available from DuPont under the trade name Riston®, e.g., Riston® 4720.
  • Aquamer® e.g., the "SF” and “CF” series resists, such as SF120, SF125, SF206, and Aquamer® CF 2.0; those available from Lea-Ronal, Inc. as “AP850”, and those available from Hitachi as Photec® HU350.
  • the invention also involves a method for making the flexible circuits described herein. Certain steps ofthe process may vary, depending ofthe type of printed circuit desired; however, for formation of rounded interconnect bumps having substantially uniform profiles, it is critical that the plating bath contain a gelatinous brightening agents. For maximum uniformity, the electrical interconnection ofthe cathode to the flexible composite material during the plating should be minimized to a narrow window
  • -6- additives such as polyethylene glycols, methoxy polyethylene glycols, dyes, aminothiazoles, aminothiazolines, and the like may also be present in conventional amounts.
  • the bath should be highly agitated with minimal gas bubble formation.
  • Typical strengths for such a bath are from 15 g/l to 150 g/l copper sulfate, preferably from 20 g/l to 50 g/l and from 125 g/l to 180 g/l sulfuric acid.
  • CX Additive Materials containing the brightening agents blended with other conventional additives are available commercially, e.g., from Lea-Ronal, Inc. as "CLX Additive". When such combination additives are used in the plating bath solutions, they are present at a concentration of from 5 ml/1 to 20 ml/1, preferably from 8 ml/1 to 15 ml/1.
  • the plating bath When operative, the plating bath is provided with a DC electrical source. Applied current varies from about 2 amps to more than 100 amps, depending on the speed desired for the plating line.
  • the flexible circuits ofthe invention are formed using a dielectric composite comprising a substrate and a conductive metal layer which is subjected to a series of photolithographic and subsequent steps.
  • the substrate is formed of a polymeric film such as polyesters, e.g., polyethylene terephthalate), polycarbonates, and polyimides.
  • Preferred polymeric films are polyimides, including unmodified polyimides and modified polyimides such as polyester imides, polyimide-imide-esters, polyamide-imides, polysiloxane-imides, and other mixed imides.
  • n ranges from 150 to 650, available from E. I. DuPont de Nemours and Company, (DuPont) , under the tradename Kapton®, e.g., Kapton® V, Kapton® E and Kapton® H, and also available from Kaneka Chemical Industries under the trade e.g., potassium permanganate in 3-5% KOH, and subsequently, the original thin conductive metal layer is etched where exposed with an etchant which does not harm the polymeric film, e.g., Perma-etch®, available from Electrochemicals Inc., a mixture of sulfuric acid and hydrogen peroxide, cupric chloride (CuCl 2 ) and the like.
  • Kapton® e.g., Kapton® V, Kapton® E and Kapton® H
  • Kaneka Chemical Industries under the trade e.g., potassium permanganate in 3-5% KOH
  • the conductive metal interconnect bumps are electroplated from the bottom ofthe vias to the desired thickness employing the electrolysis solution containing the gelatinous brightening agent, while current is applied from a narrow region exposed in the photoresist.
  • the flash metal layer and sputtered chrome layer ofthe conductive side are then etched away to form the final circuitry.
  • Immersion tin, gold, palladium, lead or the like is finally used to finish plate the part for protection ofthe copper, and to allow low temperature metallurgical bonding with other interconnection levels.
  • the aqueous processible photoresists are laminated onto both sides ofa substrate having a polymeric film side and a copper side, using standard laminating techniques.
  • the substrate consists of a polymeric film layer about 12 micrometers to 125 micrometers thick with the conductive metal layer being from about 12 to 40 micrometers thick.
  • the photoresist is then exposed on both sides to ultraviolet light or the like, through a suitable mask, crosslinking the exposed portions ofthe resist.
  • the image is then developed with a dilute aqueous solution until desired patterns are obtained on both sides ofthe laminate.
  • the conductive metal side ofthe laminate is then further etched to form the circuitry and portions ofthe polymeric layer thus exposed.
  • the etching is deposited through conventional means, preferably chemical or electrochemical etching on the exposed portions ofthe ofthe conductive metal layer.
  • Areas ofthe polymeric film (on the film side) not covered by the crosslinked resist are then etched with the concentrated base at a temperature of from about 70°C to about 120°C, and the photoresists are then stripped from both sides with a dilute basic solution.
  • An additional layer of mask, such as aqueous photoresist is then laminated over the first resist on the conductive metal side and crosslinked by flood exposure to a radiation source in order to protect exposed polymeric film surface (on the copper
  • the aqueous processible photoresists are laminated onto both sides ofa substrate, having a polymeric film side and a conductive metal side, using standard laminating techniques.
  • the substrate consists of a polymeric film layer of from 25 micrometers to 125 micrometers, with the conductive metal layer being from 1 to 5 micrometers thick.
  • the substrate may be made by various methods such as adhesively bonding a polyimide layer onto conductive metal such as copper foil, coating liquid polyimide on conductive metal or the like.
  • the thickness ofthe photoresist is from 35 to 50 micrometers.
  • the photoresist is then exposed on both sides to ultraviolet light or the like, through masks having predetermined patterns for the circuitry and the vias, respectively, thus crosslinking the exposed portions ofthe resist.
  • the resist is then developed with a dilute aqueous solution, e.g., a 0.5-1.5% sodium carbonate solution, until desired patterns are obtained on both sides ofthe laminate.
  • the conductive metal side ofthe laminate is then further plated to form the circuitry.
  • the plating is deposited through conventional means, preferably electrodeposition on the exposed portions ofthe ofthe conductive metal layer.
  • the laminate is then etched by means ofa spray etch or placement into a bath.
  • the etchant is typically a concentrated base, e.g., potassium hydroxide at a temperature of from 50°C to 120°C which etches the portions ofthe polymeric film not covered by the crosslinked resist. This exposes certain areas ofthe original thin conductive metal layer.
  • a hot water rinse removes residual etchant.
  • the resist is then stripped off both sides ofthe laminate in a 2-5% solution of an alkaline metal hydroxide at from about 20°C to about 80°C, preferably from about 20°C to about 60°C.
  • a layer of masking such as solder mask, covercoat, negative photoresist, or the like, is laminated over the metal circuitry side.
  • the mask may be exposed with UV light, if desired, to protect the circuit layer during bump plating.
  • the seed chrome layer at the bottom ofthe vias, now exposed, is then removed with an etchant solution, Examples Example 1 Two layers of 16.5 micrometer thick aqueous resists, available from Hercules under the tradename Aquamer® SF 2506, were laminated with heated rubber rolls to a flexible substrate consisting of 25 micrometers of Kapton® E polyimide with seed layers of chrome and copper on one side.
  • the laminate was then exposed with ultraviolet (UV) light through a phototool on each side and developed with 0.75% aqueous solution of sodium carbonate on both sides to obtain desired image of circuitry ofthe seed copper side and via pattem on the film side. Copper was then selectively plated on the seed copper side ofthe laminate to about 12 micrometers in thickness.
  • the polyimide side was then spray etched in a conveyorized machine having a KOH module with 4 spray bars with flat jet nozzles using 45% KOH at 93°C for about 1.5 to about 3 minutes, followed by a hot water rinse to remove hydrolyzed polyimide and residual potassium hydroxide.
  • the resists on both sides were then stripped with 3-4% KOH for 1-2 minutes at 60°C.
  • the resists swelled and delaminated from both surfaces cleanly.
  • the seed chrome layer exposed at the bottom ofthe vias was then removed with a solution of 18-22 gms/1 potassium permanganate in 35% KOH, and the exposed copper was etched with sulfuric acid/hydrogen peroxide solution.
  • Copper bumps were then electroplated from the copper layer in the plating solution described above, after complete rinsing with high impingement spray nozzles and cathodic current applied from a narrow region exposed in the photoresist onto the circuit side to minimize current robbing effects on the bump height distribution.
  • the flash copper layer and sputtered chrome layer on the conductive side were then etched away to form the final circuitry.
  • Immersion tin was finally used to finish plate the part for corrosion protection ofthe copper and to allow low temperature metallurgical bonding with other inter connection levels.
  • the resulting circuit had a single conductive routing layer, with bumped interconnect through the dielectric to provide z-axis interconnection.
  • steps may also be included, such as soaking the film in hot water before or after an etching step, post-etching neutralization acid bath steps, pattem steps, metal transformation and/or passivation steps, and the like.
  • interconnect bonding tape for "TAB” tape automated bonding
  • microflex circuits microflex circuits, and the like
  • further layers may be added and processed, the copper plating may be plated with gold, tin, or nickel for subsequent soldering procedures and the like according to conventional means, such as that described in U.S. Patent 5,401,913, adhesive and/or environmental protection layers may be added.
  • the pattem of the various arrays may be varied according to the bonding locations ofthe electronic device to which it is to be attached.
  • Chloride Ion (CY as Hcl) 55.0 ppm 40.0 to 80.0 ppm
  • the plating bath ofthe invention may be run at ambient or elevated temperatures.
  • the plating bath was at 24°C, with a variation of 5°C possible during use.
  • Plating compositions useful in making flexible circuits ofthe invention must be checked about every 2 to 4 hours to detennine the level ofthe brightening agent, and provide replenishment if necessary to provide a bath within the limits specified. Loss of such agents occurs whether current is being applied to the bath or not, that is, whether the bath is in use or not. Analysis is done by means of cyclic voltammetry. electroplated over the bump surface to provide corrosion protection and a low resistance, oxide-free interconnection surface.
  • Example 6 All processing steps as described in Examples 1, 2, 3, 4 and 5, except that the initial copper circuitry was formed by subtractive processing using a reverse imaged artwork.
  • Example 7 All processing steps as described in Examples 1, 2, 3, 5 and 6, except that the initial copper circuitry was formed by subtractive processing using the gold plating described in Example 4 as an etch mask.
  • Example 8 All processing steps as described in Examples 1, 2, 3, 5 and 6, except the first photoresist used wasavailable from Hercules under the tradename of Aquamer® SF220, SF215. MP215.
  • Example 10 All processing steps as described in Examples 1-9 except the polymer film used was available from DuPont under the trade name of KaptonTM H with thicknesses of 25 and 50 microns.
  • Example 1 1 All processing steps as described in Examples 1-9 except the polymer film used was available from DuPont under the trade name of KaptonTM E with a thickness of 50 microns.
  • Example 2 All processing steps as described in Example 1, except that the phototool was designed such that while all vias are filled during the bump electroplating process, some ofthe bumps were unsupported by circuitry and therefore fell out during the seed metal etching process. Without adding any additional processing steps, this allowed both bumped via interconnections and clear vias to be produced in the same circuit.
  • the plating solution used was that described above.
  • the masked regions may include areas requiring spanning or cantilevered leads.
  • Example 4 All processing steps as described in Examples 1, 2 and 3, except that Hercules
  • MP215 photoresist was employed for the first photoresist lamination, exposure, and developing prior to copper circuit plating. After copper circuitization, the laminate was baked to enhance photoresist adhesion to the copper substrate, and used to selectively electroplate gold cover metallurgy to 2.5 ⁇ m in thickness over the copper circuitry. This gold cover metallurgy remains present after seed metal removal. A final treatment with immersion gold plating was then employed to provide complete coverage ofthe copper trace sidewalls (an optional step).
  • Example 5 All processing steps as described in Examples 1 , 2, 3 and 4, except that immediately after copper bump electroplating, a 1 ⁇ m gold cover metallurgy was Another problem which can be caused by increased brightening agent content is accelerated bath contamination.
  • Comparative Example C18 All processing steps as described in Example 1 except that the metal surface contacted on the same side as the bumps to be plated (electrode reversal). The final product exhibited heavy plating on the exposed contacting surface and greatly reduced plating in the vias with the greatest effects near the exposed contacting surfaces.
  • Circuitry was produced using the methods described above, except that the material was placed on a web, unrolled, processed and re-rolled after processing.
  • Example 13 All processing steps as described in Examples 1-12, except after copper circuitization, the laminate was used to selectively electroplate nickel, gold, palladium, tin, lead, indium or other cover metal or alloy thereof to provide desirable contact metallurgical properties on circuit traces.
  • Example 14 All processing steps as described in Examples 1-12, except that after copper bump electroplating the laminate was used to selectively electroplate nickel, gold, palladium, tin, lead, indium or other cover metal or alloy thereof to provide desirable contact metallurgical properties on the bump surfaces.
  • Comparative Example C 15 All processing steps as described in Example 1, except that no brightening agent was used in the plating bath.
  • the final product had rought irregular grain structure and a highly variable bump shape and morphology. The bumps were jagged rather that smooth and rounded.
  • Example C16 All processing steps as described in Example 1 except that only 2.5 ml/1 brightening agent, i.e., CLX additive, available form Lea-Ronal, Inc., was used in the plating bath. Again, the bumps had rough irregular grain structure and a highly variable bump shape and morphology, being jagged rather than smooth and rounded.
  • CLX additive available form Lea-Ronal, Inc.
  • sulfonium salt is selected from the goup consisting of N-cyclohexyl-2-benzotiazole-sulfonium-l- propanesulfonate, bis(dimethylthiocarbamyl)sulfonium- 1 -propanesulfonate, and bis(dimethylthiocarbamyl)sulfonium carboxylate.
  • said electrolytic plating solution further comprises that salt of a conductive metal selected from the group consisting of gold, silver, copper, nickel, tin, lead, palladium, and alloys thereof.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Abstract

The present invention provides flexible circuits having at least one rounded interconnect bump, said bump having a substantially uniform profile, such circuits being formed by a process which includes electrolytic deposition, wherein the electrolytic plating system contains a gelatinous brightening agent.

Description

FLEXIBLE CIRCUITS WITH BUMPED INTERCONNECTION CAPABILITY
Background ofthe Invention Field ofthe Invention The invention provides flexible circuits capable of z-axis electrical interconnections at specific locations while retaining an insulating barrier over the remainder ofthe contacting surface, and a process for making such flexible circuits.
Description ofthe Related Art Flexible circuits and methods for making flexible circuits are well known in the electronics art. Typically each circuit layer carries electrical connections or traces which are used to connect the various components ofthe board. Multiple layer circuit boards must interconnect the various components, e.g., vias, bumps and the like.
Interconnection bumps are formed ofa conductive material and protrude above the surface ofthe electrical insulating material. In forming such bumps, the height, shape and uniformity ofthe shape is critical to avoid crosstalk and other unwanted electrical phenomena.
Several different approaches for forming bumped interconnection between flexible circuits have been disclosed. The standard process has been an additive processes where the bump is formed by depositing successive layers of metal on a suitable substrate by electrodeposition, sputtering and the like. Bumps made by this method are generally no more than 2.5 pm-3.5 pm in,height and rely on adhesion between the layers to remain anchored onto the circuit. At increased heights, delamination can be a problem.
U.S. Patent 5, 283,948 discloses bumps and a semi-additive method of manufacturing bumps using a support or base to provide mechanical interlock with the elevated connection means to prevent displacement ofthe connection. It is disclosed that such bumps may be made to have increased height without delaminating.
U.S. Patents 4,452,975, 4,783,719, and 5,197,184, among others, disclose a method of forming bumps atop circuit leads using microreplication ofa prepatterned mandrel. The circuitry is made on e.g., a steel mandrel having a Teflon pattem which allows plating ofa circuit on the mandrel surface. A dielectric transfer laminate is 6. The term "blind via" refers to a via which is not visible from the film side.
All percents, parts and ratios herein are by weight unless specifically otherwise stated.
Detailed Description ofthe Invention
The present invention relates to the formation of flexible circuits having at least one interconnect bump. The interconnect bump(s) have a rounded surface and a substantially uniform profile. The flexible circuit may have one bump or a multiplicity of such bumps, which are positioned according to a predetermined pattern formed by photolithographic processes.
The interconnect bump(s) formed on these flexible circuits are rounded shaped with substantially uniform profiles. In other words, the surface ofthe bump has a regular smooth shape without excessive variation in either direction. The uniformity of the bumps results in improved surface planarity and improved electrical connections between multiple layers of circuits. The uniformity also minimizes shorts in electrical circuit traces and other connective features. The interconnect bumps are formed by plating with a conductive metal such as copper, tin, lead, nickel, gold, or alloys thereof, or alloys of such metals with other metals. The interconnect bumps are rounded, and may be formed to a height up to 150 μm, and typically have a diameter of from 50 μm to 500 μm.
The interconnect bumps are formed by means of electroplating. The electrolytic plating solution comprises at least one gelatinous brightening agent, preferably a sulfonium salt. Such salts may be selected from sulfonium alkane sulfonates or sulfonium alkane carboxylates, including but not limited to N-cyclohexyl- 2-benzothiazole-sulfonium-l-propanesulfonate, bis (dimethylthiocarbamyl) sulfonium-1- propanesulfonate, and bis(dimethylthiocarbamyl) propane carboxylate. Such salts may be added directly or in combination with other plating bath ingredients present in said bath. The salts comprise from 0.0001 to 1.5 g/l, preferably from 0J g/l to 1.0 g/l. The bath otherwise contains conventional materials for plating, that is, the metal salts, and the electrolytic solution therefore, e.g., copper sulfate, sulfuric acid, hydrochloric acid, and the like. The bath may be operated at ambient or high temperatures. Additional
-4- a) providing a dielectric substrate having first and second opposing surfaces having at least one via extending through said first surface to said second surface, said vias defining a predetermined pattem, b) forming a dielectric composite by depositing a conductive metal to said first surface, and forming a conductive circuit pattem thereon, c) contacting a current-carrying electrode against said conductive circuit pattem, d) forming a conductive column in said via by electrolytic deposition of metal from an electrolytic plating solution, said electrolytic plating solution comprising from 5 ml/1 to 20 ml 1 ofa gelatinous brightening agent, e) continuing electrolytic deposition until at least one rounded interconnect bump is formed on said second surface, said bump having a substantially uniform profile.
A preferred method for making flexible circuits ofthe invention comprises steps for forming a conductive column in the via and for further forming the interconnect bumps wherein the electrolytic plating solution comprises from 5 ml/1 to 20 ml 1 ofa brightening agent selected from sulfonium salts.
As used herein the terms "resist" and "photoresist" are synonymous and interchangeable. Also, the terms "pattem" and "image" are used interchangeably to mean the configuration which is formed-by the exposure and development ofa photoresist.
The following terms have these meanings as used herein: 1. The term "substantially uniform" means that a surface so described is smooth, and without variation greater than about 20%. 2. The term "profile" means an outline shape ofthe object.
3. The term "substrate" refers to the polymeric film layer ofthe flexible circuit.
4. The term "dielectric composite" means the polymeric film layer and the thin conductive metal layer deposited thereon. 5. The term "via" means a channel which extends through the polymeric film layer ofthe dielectric composite. name Apical® D. Other commercially available polyimide precursors include those available from DuPont under the trade name Pyralin®. The substrate has deposited thereon a conductive metal layer to form the dielectric composite, which is then processed as described, infra, to form a flexible circuit. The layer may be deposited through a variety of means including but not limited to electroless deposition, chemical vapor deposition, sputtering, lamination and other known methods.
Various conductive metals are useful as the thin conductive metal layer, e.g.,, copper, tin, lead, silver, gold, nickel, alloys thereof, or alloys of such metals with other metals. Copper, tin or nickel metallurgies are widely used for this layer. Trace metal circuitry may also be formed from any of these conductive metals.
Negative photoresists useful in processes ofthe invention include negative aqueous processible polymerizable photohardenable compositions such as those disclosed in U.S. Patent Nos. 3,469,982, 3,448,098, 3,867,153, and 3,526,504. Such photoresists include at least one polymer, additional crosslinkable monomeric units and a photoinitiator. Examples of polymers used in photoresists include copolymers of methyl methacrylate, ethyl acrylate and acrylic acid, copolymers of styrene and maleic anhydride isobutyl ester and the like. The crosslinkable monomeric units may be multiacrylates such as trimethylol propane triacrylate. Examples of some aqueous processible negative photoresists employed according to the present invention are from polymethyl-methacrylates such as those commercially available from DuPont under the trade name Riston®, e.g., Riston® 4720.
Also useful are those available from Hercules under the tradename Aquamer®, e.g., the "SF" and "CF" series resists, such as SF120, SF125, SF206, and Aquamer® CF 2.0; those available from Lea-Ronal, Inc. as "AP850", and those available from Hitachi as Photec® HU350.
The invention also involves a method for making the flexible circuits described herein. Certain steps ofthe process may vary, depending ofthe type of printed circuit desired; however, for formation of rounded interconnect bumps having substantially uniform profiles, it is critical that the plating bath contain a gelatinous brightening agents. For maximum uniformity, the electrical interconnection ofthe cathode to the flexible composite material during the plating should be minimized to a narrow window
-6- additives such as polyethylene glycols, methoxy polyethylene glycols, dyes, aminothiazoles, aminothiazolines, and the like may also be present in conventional amounts.
The bath should be highly agitated with minimal gas bubble formation. Typical strengths for such a bath are from 15 g/l to 150 g/l copper sulfate, preferably from 20 g/l to 50 g/l and from 125 g/l to 180 g/l sulfuric acid.
Materials containing the brightening agents blended with other conventional additives are available commercially, e.g., from Lea-Ronal, Inc. as "CLX Additive". When such combination additives are used in the plating bath solutions, they are present at a concentration of from 5 ml/1 to 20 ml/1, preferably from 8 ml/1 to 15 ml/1.
When operative, the plating bath is provided with a DC electrical source. Applied current varies from about 2 amps to more than 100 amps, depending on the speed desired for the plating line.
The flexible circuits ofthe invention are formed using a dielectric composite comprising a substrate and a conductive metal layer which is subjected to a series of photolithographic and subsequent steps.
The substrate is formed ofa polymeric film such as polyesters, e.g., polyethylene terephthalate), polycarbonates, and polyimides. Preferred polymeric films are polyimides, including unmodified polyimides and modified polyimides such as polyester imides, polyimide-imide-esters, polyamide-imides, polysiloxane-imides, and other mixed imides. Especially preferred is a polyimide polymer made from the anhydride of pyromelittic acid and 4,4 diamino-diphenyl ether represented by the general formula:
Figure imgf000007_0001
wherein n ranges from 150 to 650, available from E. I. DuPont de Nemours and Company, (DuPont) , under the tradename Kapton®, e.g., Kapton® V, Kapton® E and Kapton® H, and also available from Kaneka Chemical Industries under the trade e.g., potassium permanganate in 3-5% KOH, and subsequently, the original thin conductive metal layer is etched where exposed with an etchant which does not harm the polymeric film, e.g., Perma-etch®, available from Electrochemicals Inc., a mixture of sulfuric acid and hydrogen peroxide, cupric chloride (CuCl2) and the like. After complete rinsing with high impingement, the conductive metal interconnect bumps are electroplated from the bottom ofthe vias to the desired thickness employing the electrolysis solution containing the gelatinous brightening agent, while current is applied from a narrow region exposed in the photoresist. The flash metal layer and sputtered chrome layer ofthe conductive side are then etched away to form the final circuitry.
Immersion tin, gold, palladium, lead or the like is finally used to finish plate the part for protection ofthe copper, and to allow low temperature metallurgical bonding with other interconnection levels.
In an alternate process, the aqueous processible photoresists are laminated onto both sides ofa substrate having a polymeric film side and a copper side, using standard laminating techniques. The substrate consists ofa polymeric film layer about 12 micrometers to 125 micrometers thick with the conductive metal layer being from about 12 to 40 micrometers thick. The photoresist is then exposed on both sides to ultraviolet light or the like, through a suitable mask, crosslinking the exposed portions ofthe resist. The image is then developed with a dilute aqueous solution until desired patterns are obtained on both sides ofthe laminate.
The conductive metal side ofthe laminate is then further etched to form the circuitry and portions ofthe polymeric layer thus exposed. The etching is deposited through conventional means, preferably chemical or electrochemical etching on the exposed portions ofthe ofthe conductive metal layer.
Areas ofthe polymeric film (on the film side) not covered by the crosslinked resist are then etched with the concentrated base at a temperature of from about 70°C to about 120°C, and the photoresists are then stripped from both sides with a dilute basic solution. An additional layer of mask, such as aqueous photoresist is then laminated over the first resist on the conductive metal side and crosslinked by flood exposure to a radiation source in order to protect exposed polymeric film surface (on the copper
-8- or windows, arranged at the edge ofthe web and located on the opposite side from which the plating will occur, i.e., as far as possible from the bumps to be plated. A typical sequence of steps may be described as follows: The aqueous processible photoresists are laminated onto both sides ofa substrate, having a polymeric film side and a conductive metal side, using standard laminating techniques. Typically, the substrate consists ofa polymeric film layer of from 25 micrometers to 125 micrometers, with the conductive metal layer being from 1 to 5 micrometers thick. The substrate may be made by various methods such as adhesively bonding a polyimide layer onto conductive metal such as copper foil, coating liquid polyimide on conductive metal or the like.
The thickness ofthe photoresist is from 35 to 50 micrometers. The photoresist is then exposed on both sides to ultraviolet light or the like, through masks having predetermined patterns for the circuitry and the vias, respectively, thus crosslinking the exposed portions ofthe resist. The resist is then developed with a dilute aqueous solution, e.g., a 0.5-1.5% sodium carbonate solution, until desired patterns are obtained on both sides ofthe laminate.
After the photoresists has been patterned, the conductive metal side ofthe laminate is then further plated to form the circuitry. The plating is deposited through conventional means, preferably electrodeposition on the exposed portions ofthe ofthe conductive metal layer.
The laminate is then etched by means ofa spray etch or placement into a bath. The etchant is typically a concentrated base, e.g., potassium hydroxide at a temperature of from 50°C to 120°C which etches the portions ofthe polymeric film not covered by the crosslinked resist. This exposes certain areas ofthe original thin conductive metal layer. After etching, a hot water rinse removes residual etchant. The resist is then stripped off both sides ofthe laminate in a 2-5% solution of an alkaline metal hydroxide at from about 20°C to about 80°C, preferably from about 20°C to about 60°C.
Next a layer of masking, such as solder mask, covercoat, negative photoresist, or the like, is laminated over the metal circuitry side. The mask may be exposed with UV light, if desired, to protect the circuit layer during bump plating. The seed chrome layer at the bottom ofthe vias, now exposed, is then removed with an etchant solution, Examples Example 1 Two layers of 16.5 micrometer thick aqueous resists, available from Hercules under the tradename Aquamer® SF 2506, were laminated with heated rubber rolls to a flexible substrate consisting of 25 micrometers of Kapton® E polyimide with seed layers of chrome and copper on one side. The laminate was then exposed with ultraviolet (UV) light through a phototool on each side and developed with 0.75% aqueous solution of sodium carbonate on both sides to obtain desired image of circuitry ofthe seed copper side and via pattem on the film side. Copper was then selectively plated on the seed copper side ofthe laminate to about 12 micrometers in thickness. The polyimide side was then spray etched in a conveyorized machine having a KOH module with 4 spray bars with flat jet nozzles using 45% KOH at 93°C for about 1.5 to about 3 minutes, followed by a hot water rinse to remove hydrolyzed polyimide and residual potassium hydroxide. The resists on both sides were then stripped with 3-4% KOH for 1-2 minutes at 60°C. The resists swelled and delaminated from both surfaces cleanly. A layer of 50 micrometer thick, negative, aqueous, processible, photoresist, available from Hercules under the trade name Aquamer® SF220, was laminated over the copper circuitry side and exposed with UV light to protect the circuit layer during bump plating. The seed chrome layer exposed at the bottom ofthe vias was then removed with a solution of 18-22 gms/1 potassium permanganate in 35% KOH, and the exposed copper was etched with sulfuric acid/hydrogen peroxide solution. Copper bumps were then electroplated from the copper layer in the plating solution described above, after complete rinsing with high impingement spray nozzles and cathodic current applied from a narrow region exposed in the photoresist onto the circuit side to minimize current robbing effects on the bump height distribution. The flash copper layer and sputtered chrome layer on the conductive side were then etched away to form the final circuitry. Immersion tin was finally used to finish plate the part for corrosion protection ofthe copper and to allow low temperature metallurgical bonding with other inter connection levels. The resulting circuit had a single conductive routing layer, with bumped interconnect through the dielectric to provide z-axis interconnection.
JO- side) from further etching. The subsequent preparation and electroplating ofthe bumps is similar to that described above.
Other steps may also be included, such as soaking the film in hot water before or after an etching step, post-etching neutralization acid bath steps, pattem steps, metal transformation and/or passivation steps, and the like.
To create finished products such as flexible circuits, interconnect bonding tape for "TAB" (tape automated bonding) processes, microflex circuits, and the like, further layers may be added and processed, the copper plating may be plated with gold, tin, or nickel for subsequent soldering procedures and the like according to conventional means, such as that described in U.S. Patent 5,401,913, adhesive and/or environmental protection layers may be added.
As with any flexible circuit, the pattem ofthe various arrays may be varied according to the bonding locations ofthe electronic device to which it is to be attached.
The following examples are meant to be illustrative and are not intended to limit the scope ofthe invention which is expressed solely by the claims.
Plating Solution Composition
Ingredients Initial Charge Range = Control Limits
Copper Sulfate (CUS04) 31.25g liter 18.75 to 44 gllitcr.
1 Sulfuric Acid (H2SO4) 156J5g/liter 137 to 175 g/liter
Chloride Ion (CY as Hcl) 55.0 ppm 40.0 to 80.0 ppm
CLX Additive 9.0 ml/liter 8.0 to 10 ml/liter
CLX Carrier 13.5 ml/liter 12.0 to 15.0 ml liter
The plating bath ofthe invention may be run at ambient or elevated temperatures. When used in the examples below, the plating bath was at 24°C, with a variation of 5°C possible during use.
Plating compositions useful in making flexible circuits ofthe invention must be checked about every 2 to 4 hours to detennine the level ofthe brightening agent, and provide replenishment if necessary to provide a bath within the limits specified. Loss of such agents occurs whether current is being applied to the bath or not, that is, whether the bath is in use or not. Analysis is done by means of cyclic voltammetry. electroplated over the bump surface to provide corrosion protection and a low resistance, oxide-free interconnection surface.
Example 6 All processing steps as described in Examples 1, 2, 3, 4 and 5, except that the initial copper circuitry was formed by subtractive processing using a reverse imaged artwork.
Example 7 All processing steps as described in Examples 1, 2, 3, 5 and 6, except that the initial copper circuitry was formed by subtractive processing using the gold plating described in Example 4 as an etch mask.
Example 8 All processing steps as described in Examples 1, 2, 3, 5 and 6, except the first photoresist used wasavailable from Hercules under the tradename of Aquamer® SF220, SF215. MP215.
Example 9
All processing steps as described in Examples 1, 2, 3, 4, 5 and 6, except the first photoresist used was available from Hercules as model numbe MP210 or was available from DuPont as model number 9020 or 9008.
Example 10 All processing steps as described in Examples 1-9 except the polymer film used was available from DuPont under the trade name of Kapton™ H with thicknesses of 25 and 50 microns.
Example 1 1 All processing steps as described in Examples 1-9 except the polymer film used was available from DuPont under the trade name of Kapton™ E with a thickness of 50 microns.
■12- Example 2 All processing steps as described in Example 1, except that the phototool was designed such that while all vias are filled during the bump electroplating process, some ofthe bumps were unsupported by circuitry and therefore fell out during the seed metal etching process. Without adding any additional processing steps, this allowed both bumped via interconnections and clear vias to be produced in the same circuit. The plating solution used was that described above.
The unfilled vias described in this example could be useful for machine/part alignment features, etc.
Example 3
All processing steps as described in Examples 1 and 2, except that the second photolithography steps included photoresist lamination on the polymer side as well as the circuit side, and a loose reregistration exposure to flood expose the circuit side and selectively mask windows and other polymer features on the polymer side (where it is undesirable to electroplate bump features). The regions which require bump electroplating were then exposed by developing the photoresist with said developing solution.
The masked regions may include areas requiring spanning or cantilevered leads.
Example 4 All processing steps as described in Examples 1, 2 and 3, except that Hercules
MP215 photoresist was employed for the first photoresist lamination, exposure, and developing prior to copper circuit plating. After copper circuitization, the laminate was baked to enhance photoresist adhesion to the copper substrate, and used to selectively electroplate gold cover metallurgy to 2.5 μm in thickness over the copper circuitry. This gold cover metallurgy remains present after seed metal removal. A final treatment with immersion gold plating was then employed to provide complete coverage ofthe copper trace sidewalls (an optional step).
Example 5 All processing steps as described in Examples 1 , 2, 3 and 4, except that immediately after copper bump electroplating, a 1 μm gold cover metallurgy was Another problem which can be caused by increased brightening agent content is accelerated bath contamination.
Comparative Example C18 All processing steps as described in Example 1 except that the metal surface contacted on the same side as the bumps to be plated (electrode reversal). The final product exhibited heavy plating on the exposed contacting surface and greatly reduced plating in the vias with the greatest effects near the exposed contacting surfaces.
-14- Example 12 Circuitry was produced using the methods described above, except that the material was placed on a web, unrolled, processed and re-rolled after processing.
Example 13 All processing steps as described in Examples 1-12, except after copper circuitization, the laminate was used to selectively electroplate nickel, gold, palladium, tin, lead, indium or other cover metal or alloy thereof to provide desirable contact metallurgical properties on circuit traces.
Example 14 All processing steps as described in Examples 1-12, except that after copper bump electroplating the laminate was used to selectively electroplate nickel, gold, palladium, tin, lead, indium or other cover metal or alloy thereof to provide desirable contact metallurgical properties on the bump surfaces.
Comparative Example C 15 All processing steps as described in Example 1, except that no brightening agent was used in the plating bath. The final product had rought irregular grain structure and a highly variable bump shape and morphology. The bumps were jagged rather that smooth and rounded.
Comparative Example C16 All processing steps as described in Example 1 except that only 2.5 ml/1 brightening agent, i.e., CLX additive, available form Lea-Ronal, Inc., was used in the plating bath. Again, the bumps had rough irregular grain structure and a highly variable bump shape and morphology, being jagged rather than smooth and rounded.
Comparative Example C17 All processing steps as described in Example 1, except that a very high level of
"CLX Additive" brightening agent was used, i.e. 27 ml/1. The final product exhibited bumps having a "lumpy" shape, that is, multiple, smooth rounded surfaces instead ofa single smooth rounded bump, and the peak bump height was not always centered. 6. A method according to claim 5 wherein said sulfonium salt is selected from the goup consisting of N-cyclohexyl-2-benzotiazole-sulfonium-l- propanesulfonate, bis(dimethylthiocarbamyl)sulfonium- 1 -propanesulfonate, and bis(dimethylthiocarbamyl)sulfonium carboxylate.
7. A method according to claim 4 wherein said sulfonium salt is added directly to said electrolytic plating bath.
8. A method according to claim 4 wherein said sulfonium salt is added as a blend with other additives.
9. A method according to claim 4 wherein said electrolytic plating solution further comprises that salt ofa conductive metal selected from the group consisting of gold, silver, copper, nickel, tin, lead, palladium, and alloys thereof.
-16-
SUBSTrrUTE SHEET (RULE 26)

Claims

What is claimed is:
1. A flexible circuit having at least one rounded interconnect bump, said bump having a substantially uniform profile, said bump has a height of up to 150 μm, and a diameter of from 50 μm to 500 μm..
2. A flexible circuit according the claim 1 wherein said bump has a profile surface variation of less than 20%, wherein said bump is formed from a conductive metal selected from the group consisting of gold, silver, copper, nickel, tin, lead, palladium, alloys thereof, and alloys thereof with other metals.
3. A flexible circuit according to claim 1 comprising a multiplicity of said interconnect bumps .
4. A method for making a flexible circuit according to claim 1 comprising the steps of: a) providing a dielectric substrate having first and second opposing surfaces having at least one via extending through said first surface to said second surface, said vias defining a predetermined pattern, b) forming a dielectric composite by depositing a conductive metal to said first surface, and forming a conductive circuit pattem thereon, c) contacting a current-carrying electrode against said conductive circuit pattern, d) forming a conductive column in said via by electrolytic deposition of metal from an electrolytic plating solution, said electrolytic plating solution comprising from 0.0001 g/l to 1.5 g/l of a gelatinous brightening agent, e) continuing electrolytic deposition until at least one rounded interconnect bump is formed on said second surface, said bump having a substantially uniform profile.
5. A method according to claim 4 wherein said electrolytic plating solution comprises a sulfonium salt selected from the group consisting of sulfonium alkane sulfonates and solfonium alkane carboxylates in an amount of 0.01 g/l to 1.0 g/l..
-15- SUBST1TUTE SHEET (RULE 26) C(Conπnuanon) DOCUMENTS CONSIDERED TO BE RELEVANT
Category ' Citation of document, with indication, where appropnate, of the relevant passages Relevant to claim No.
INTERNATIONAL JOURNAL OF MICROCIRCUITS AND 1-3
ELECTRONIC PACKAGING, vol . 17, no. 3, A US, pages 259-270, XP0O0497391
Y. YAMAMOTO ET AL.: "Evaluation of new micro-connection system using microbumps"
3th quarter of 1994 see page 260 - page 261
EP,A,0 368262 (NITTO DENKO CORP.) 16 May 1-3
1990 see column 8, line 36 - column 10, line
44; figures
4
US,A,3 832 769 (OLYPHANT, JR. ET AL.) 3 1-4
September 1974 cited in the application see the whole document
US,A,3 725220 (KESSLER ET AL.) 3 April 4,6,7,10
1973 cited in the application see abstract
Form PCT ISA -10 (continuation of second sheet) (July 1992) page 2 of 2
PCT/US1996/013122 1995-09-22 1996-08-14 Flexible circuits with bumped interconnection capability WO1997011591A1 (en)

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