DE68928087D1 - Substratsstruktur für zusammengesetztes Halbleiterbauelement - Google Patents

Substratsstruktur für zusammengesetztes Halbleiterbauelement

Info

Publication number
DE68928087D1
DE68928087D1 DE68928087T DE68928087T DE68928087D1 DE 68928087 D1 DE68928087 D1 DE 68928087D1 DE 68928087 T DE68928087 T DE 68928087T DE 68928087 T DE68928087 T DE 68928087T DE 68928087 D1 DE68928087 D1 DE 68928087D1
Authority
DE
Germany
Prior art keywords
semiconductor device
substrate structure
composite semiconductor
composite
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE68928087T
Other languages
English (en)
Other versions
DE68928087T2 (de
Inventor
Koichi C O Patent Div Kitahara
Yoshinori C O Patent D Natsume
Yoshinori C O Patent Di Hosoki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Application granted granted Critical
Publication of DE68928087D1 publication Critical patent/DE68928087D1/de
Publication of DE68928087T2 publication Critical patent/DE68928087T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76275—Vertical isolation by bonding techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76286—Lateral isolation by refilling of trenches with polycristalline material

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Recrystallisation Techniques (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Bipolar Transistors (AREA)
DE68928087T 1988-01-05 1989-01-05 Substratsstruktur für zusammengesetztes Halbleiterbauelement Expired - Fee Related DE68928087T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63000465A JPH01179342A (ja) 1988-01-05 1988-01-05 複合半導体結晶体

Publications (2)

Publication Number Publication Date
DE68928087D1 true DE68928087D1 (de) 1997-07-10
DE68928087T2 DE68928087T2 (de) 1997-10-16

Family

ID=11474545

Family Applications (1)

Application Number Title Priority Date Filing Date
DE68928087T Expired - Fee Related DE68928087T2 (de) 1988-01-05 1989-01-05 Substratsstruktur für zusammengesetztes Halbleiterbauelement

Country Status (5)

Country Link
US (1) US4985745A (de)
EP (1) EP0323856B1 (de)
JP (1) JPH01179342A (de)
KR (1) KR910010220B1 (de)
DE (1) DE68928087T2 (de)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2788269B2 (ja) * 1988-02-08 1998-08-20 株式会社東芝 半導体装置およびその製造方法
US5049968A (en) * 1988-02-08 1991-09-17 Kabushiki Kaisha Toshiba Dielectrically isolated substrate and semiconductor device using the same
US5332920A (en) * 1988-02-08 1994-07-26 Kabushiki Kaisha Toshiba Dielectrically isolated high and low voltage substrate regions
US5089863A (en) * 1988-09-08 1992-02-18 Mitsubishi Denki Kabushiki Kaisha Field effect transistor with T-shaped gate electrode
US5543646A (en) * 1988-09-08 1996-08-06 Mitsubishi Denki Kabushiki Kaisha Field effect transistor with a shaped gate electrode
US5272100A (en) * 1988-09-08 1993-12-21 Mitsubishi Denki Kabushiki Kaisha Field effect transistor with T-shaped gate electrode and manufacturing method therefor
US5416354A (en) * 1989-01-06 1995-05-16 Unitrode Corporation Inverted epitaxial process semiconductor devices
EP0398468A3 (de) * 1989-05-16 1991-03-13 Kabushiki Kaisha Toshiba Dielektrisch isoliertes Substrat und Halbleiteranordnung mit diesem Substrat
JPH03129854A (ja) * 1989-10-16 1991-06-03 Toshiba Corp 半導体装置の製造方法
FR2656738B1 (fr) * 1989-12-29 1995-03-17 Telemecanique Procede pour fabriquer un dispositif semiconducteur, dispositif et composant semiconducteur obtenus par le procede.
US5102809A (en) * 1990-10-11 1992-04-07 Texas Instruments Incorporated SOI BICMOS process
JP2609753B2 (ja) * 1990-10-17 1997-05-14 株式会社東芝 半導体装置
WO1993026041A1 (en) * 1992-06-17 1993-12-23 Harris Corporation Bonded wafer processing
US5260233A (en) * 1992-11-06 1993-11-09 International Business Machines Corporation Semiconductor device and wafer structure having a planar buried interconnect by wafer bonding
JP3116609B2 (ja) * 1992-11-25 2000-12-11 日本電気株式会社 半導体装置の製造方法
JP2773611B2 (ja) * 1993-11-17 1998-07-09 株式会社デンソー 絶縁物分離半導体装置
EP0661735B1 (de) * 1993-12-29 2001-03-07 Consorzio per la Ricerca sulla Microelettronica nel Mezzogiorno Verfahren zur Herstellung integrierter Schaltungen, insbesondere intelligenter Leistungsanordnungen
JP3396553B2 (ja) * 1994-02-04 2003-04-14 三菱電機株式会社 半導体装置の製造方法及び半導体装置
JPH09331072A (ja) * 1996-06-12 1997-12-22 Toshiba Corp 半導体装置及びその製造方法
JP3595182B2 (ja) * 1999-02-10 2004-12-02 沖電気工業株式会社 半導体装置の製造方法
US6555891B1 (en) 2000-10-17 2003-04-29 International Business Machines Corporation SOI hybrid structure with selective epitaxial growth of silicon
JP2002217282A (ja) * 2001-01-19 2002-08-02 Mitsubishi Electric Corp 半導体装置及びその製造方法
JP2005244020A (ja) * 2004-02-27 2005-09-08 Toshiba Corp 半導体装置及びその製造方法

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5334483A (en) * 1977-09-09 1978-03-31 Hitachi Ltd Substrate for semiconductor integrating circuit
US4261003A (en) * 1979-03-09 1981-04-07 International Business Machines Corporation Integrated circuit structures with full dielectric isolation and a novel method for fabrication thereof
US4283235A (en) * 1979-07-27 1981-08-11 Massachusetts Institute Of Technology Dielectric isolation using shallow oxide and polycrystalline silicon utilizing selective oxidation
FR2472268A1 (fr) * 1979-12-21 1981-06-26 Thomson Csf Procede de formation de caisson dans des circuits integres
US4408386A (en) * 1980-12-12 1983-10-11 Oki Electric Industry Co., Ltd. Method of manufacturing semiconductor integrated circuit devices
JPS57133637A (en) * 1981-02-13 1982-08-18 Hitachi Ltd Semiconductor integrated circuit device
US4661832A (en) * 1982-06-30 1987-04-28 International Business Machines Corporation Total dielectric isolation for integrated circuits
US4501060A (en) * 1983-01-24 1985-02-26 At&T Bell Laboratories Dielectrically isolated semiconductor devices
US4494303A (en) * 1983-03-31 1985-01-22 At&T Bell Laboratories Method of making dielectrically isolated silicon devices
JPS6081839A (ja) * 1983-10-12 1985-05-09 Fujitsu Ltd 半導体装置の製造方法
EP0156964A1 (de) * 1983-11-18 1985-10-09 Motorola, Inc. Anordnung und Verfahren zur Isolierung durch PN-Übergang
JPS60113455A (ja) * 1983-11-24 1985-06-19 Hitachi Ltd 半導体集積回路装置
US4523370A (en) * 1983-12-05 1985-06-18 Ncr Corporation Process for fabricating a bipolar transistor with a thin base and an abrupt base-collector junction
DE3583183D1 (de) * 1984-05-09 1991-07-18 Toshiba Kawasaki Kk Verfahren zur herstellung eines halbleitersubstrates.
JPS61184843A (ja) * 1985-02-13 1986-08-18 Toshiba Corp 複合半導体装置とその製造方法
US4601779A (en) * 1985-06-24 1986-07-22 International Business Machines Corporation Method of producing a thin silicon-on-insulator layer
JPS6276645A (ja) * 1985-09-30 1987-04-08 Toshiba Corp 複合半導体結晶体構造
JPH077798B2 (ja) * 1986-01-31 1995-01-30 日本電信電話株式会社 同一平面上に互いに分離しかつ複数の材料からなる島領域を有する複合基板の作製方法
US4784970A (en) * 1987-11-18 1988-11-15 Grumman Aerospace Corporation Process for making a double wafer moated signal processor

Also Published As

Publication number Publication date
KR890012364A (ko) 1989-08-26
EP0323856A3 (de) 1991-02-20
KR910010220B1 (ko) 1991-12-21
DE68928087T2 (de) 1997-10-16
JPH01179342A (ja) 1989-07-17
EP0323856A2 (de) 1989-07-12
EP0323856B1 (de) 1997-06-04
US4985745A (en) 1991-01-15

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8320 Willingness to grant licences declared (paragraph 23)
8339 Ceased/non-payment of the annual fee