KR890008952A - 반도체 기판의 표면처리방법 - Google Patents

반도체 기판의 표면처리방법 Download PDF

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Publication number
KR890008952A
KR890008952A KR1019880015699A KR880015699A KR890008952A KR 890008952 A KR890008952 A KR 890008952A KR 1019880015699 A KR1019880015699 A KR 1019880015699A KR 880015699 A KR880015699 A KR 880015699A KR 890008952 A KR890008952 A KR 890008952A
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South Korea
Prior art keywords
semiconductor substrate
surface treatment
treatment method
pure water
semiconductor
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KR1019880015699A
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KR920003878B1 (ko
Inventor
모리야 미야시타
신타로 요시이
게이코 사쿠마
Original Assignee
아오이 죠이치
가부시키가이샤 도시바
다케다이 마사다카
도시바마이콤엔지니어링 가부시키가이샤
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Publication of KR890008952A publication Critical patent/KR890008952A/ko
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Publication of KR920003878B1 publication Critical patent/KR920003878B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67017—Apparatus for fluid treatment
    • H01L21/67023—Apparatus for fluid treatment for general liquid treatment, e.g. etching followed by cleaning
    • H01L21/203—
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/974—Substrate surface preparation

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Cleaning Or Drying Semiconductors (AREA)

Abstract

내용 없음

Description

반도체 기판의 표면처리방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제 1 도는 본 발명에 따른 반도체 기판의 표면처리방법을 실시할때에 사용되는 표면처리장치의 구성예를 설명하기 위한 정면도,
제 2 도는 제1도에 도시한 표면처리장치의 측면도,
제 3 도는 본 발명에 따른 반도체 기판의 표면처리방법을 실시할 때에 사용되는 표면처리방치의 다른 구성예를 도시한 정면도.

Claims (11)

  1. 초음파를 발생시키는 공정과, 상기 초음파를 처리액(11)을 통해서 반도체 기판(13,21)의 한쪽면으로 전파시킴으로써 그 반도체 기판(13,21)의 한쪽면에 기계적인 디스토션(distortion)을 주는 공정으로 이루어진 반도체 기판의 표면처리방법.
  2. 제1항에 있어서, 초음파의 출력은 50W∼500W의 범위내에서 선택하고, 초음파의 주파수는 10㎑∼100㎑의 범위내에서 선택하도록 한 것을 특징으로 하는 반도체 기판의 표면처리방법.
  3. 제1항에 있어서, 처리액은 순수한 물 및 초순수한 물(11)을 함유한 그룹에서 선택하도록 한 것을 특정으로 하는 반도체 기판의 표면처리방법.
  4. 제1항에 있어서, 반도체 기판(13,21)의 한쪽면은 표면처리 다음의 공정에서 반도체소자가 형성되는 면의 이면인 것을 특징으로 하는 반도체 기판의 표면처리방법.
  5. 제1항에 있어서, 순수한 물로 가득채원진 용기(10)내에 상기 반도체 기판(13)을 수직으로 세워두고, 상기 용기(10)의 밑부분에 초음파발생부(12)를 설치해서 상기 순수한 물중으로 초음파를 전파시킴으로써 상기 반도체 기판(13)의 한쪽면에 기계적인 디스토션을 주며, 다른쪽면에는 밑부분으로 부터 가스를 분출시켜서 순수한 물중에 기포를 발생시킴으로써 기계적인 디스토션이 주어지는 것을 저지시키는 것을 특징으로 하는 방도체기판의 표면처리방법.
  6. 제5항에 있어서, 가스는 가스필터(18)를 통해서 미세한 입자를 제거시킨후에 공급하도록 한 것을 특징으로 하는 반도체 기판의 표면처리방법.
  7. 제6항에 있어서, 가스는 공기 및 질소를 함유한 그룹에서 선택하도록 한 것을 특징으로 하는 반도체 기판의 표면처리방법.
  8. 제5항에 있어서, 반도체 기판(13) 사이에는 간막이판(15)을 설치한 것을 특징으로 하는 반도체 기판의 표변처리방법.
  9. 제5항에 있어서, 기계적인 디스토션을 줄때에 상기 반도체 기판(13)을 회전시키도록 한 것을 특징으로 하는 반도체 기판의 표면처리방법.
  10. 제1항에 있어서, 반도체 기판(21)을 회전대(20)위에 수평으로 올려놓고, 내부에 초음파발생부(24)가 설치된 노즐(23)로 부터 상기 반도체 기판(21)의 표면으로 순수한 물을 분사시킴으로써 상기 반도체 기판(21)의 한쪽면에 기계적인 디스토션을 주도록 한 것을 특징으로 하는 반도체 기판의 표면처리방법.
  11. 제10항에 있어서, 노즐(23)을 상기 반도체 기판(21)의 중심과 바깥둘레를 연결하는 선을 따라서 방향(103A,103B)으로 이동시키도록 한 것을 특징으로 하는 반도체 기판의 표면처리방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019880015699A 1987-11-28 1988-11-28 반도체기판의 표면처리방법 KR920003878B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP62-300356 1987-11-28
JP62300356A JPH01143223A (ja) 1987-11-28 1987-11-28 半導体基板の表面処理方法

Publications (2)

Publication Number Publication Date
KR890008952A true KR890008952A (ko) 1989-07-13
KR920003878B1 KR920003878B1 (ko) 1992-05-16

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US (1) US4980300A (ko)
EP (2) EP0534497B1 (ko)
JP (1) JPH01143223A (ko)
KR (1) KR920003878B1 (ko)
DE (2) DE3856135T2 (ko)

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Also Published As

Publication number Publication date
DE3856135D1 (de) 1998-03-26
DE3856135T2 (de) 1998-07-02
EP0534497B1 (en) 1998-02-18
JPH0524661B2 (ko) 1993-04-08
DE3887477D1 (de) 1994-03-10
DE3887477T2 (de) 1994-05-11
US4980300A (en) 1990-12-25
EP0534497A1 (en) 1993-03-31
KR920003878B1 (ko) 1992-05-16
EP0319806B1 (en) 1994-01-26
EP0319806A1 (en) 1989-06-14
JPH01143223A (ja) 1989-06-05

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