KR860003671A - 상보형 반도체 장치 - Google Patents

상보형 반도체 장치 Download PDF

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KR860003671A
KR860003671A KR1019850007623A KR850007623A KR860003671A KR 860003671 A KR860003671 A KR 860003671A KR 1019850007623 A KR1019850007623 A KR 1019850007623A KR 850007623 A KR850007623 A KR 850007623A KR 860003671 A KR860003671 A KR 860003671A
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well
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아쯔오 와다나베
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미다 가쓰시게
가부시기가이샤 히다찌 세이사꾸쇼
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Priority claimed from JP59249339A external-priority patent/JPS61127147A/ja
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    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823892—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
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Abstract

내용 없음

Description

상보형 반도체 장치
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도~제3도는 본 발명의 기본실시예를 개략적으로 보인 반도체칩의 부분단면도.
도면의 주요부분에 대한 부호의 설명
1 : 기판, 2,3 : 매립영역, 4 : 에피택샬층, 5,21 : 아이쏘레이션영역, 13 : 질화막, 14,16,35 : 산화막, 15 : 홈부, 18 : 부동막, 20 : n형영역, 22,24 : n형웰, 23 : p형웰, 25 : p형매립영역, 27 : p형 +영역, 30 : p형영역, 33 : 폴리실리콘막, 36 : 막. 37 : HLD막, 38 : 포오토레지스트, 39 : 폴리실리콘패턴, 41 : 에미터영역, 42 : n형폴리크리스탈린실리콘, 43 : p형베이스영역, 44 : 클렉터접촉영역, 61 : n채널 MOS FET.

Claims (14)

  1. 모노리딕 상보형 반도체 장치에 있어서, 제1도전형의 반도체 기판과, 기판상에 배열되고, 적어도 하나 이상의 제1도전형의 제1매립 영역과 제1 매립 영역에 인접하여 배치된 제2매립 영역으로 구성되며, 제1도전형에 반대되는 제2도전형으로 이루어진 높은 불순물 농도의 반도체 매립영역과, 매립영역에 배치되고 주표면을 형성하며, 적어도 하나이상의 제1매립영역에 배치된 제1도전형의 제1웰 영역과 제2매립영역상에 배치된 제2도전형의 제2웰영역으로 구성시킨 낮은 불순물 농도의 반도체웰영역과, 주표면으로부터 기판영역내로 연장하고 제1웰과 매립영역을 제2웰과 매립영역으로부터 분리되게 하는 절연부재들로 구성시킨 것을 특징으로 하는 모노리딕 상보형 반도체 장치.
  2. 제1항에 있어서, 주표면에 인접한 제1웰에 도우프된 제2도전형의 제1도우프영역과, 주표면에 인접하여 제2웰영역에 도우프된 제1도전형의 제2도우프 영역으로 이루어지게 한 것을 특징으로 하는 모노리딕 상보형 반도체 장치.
  3. 제2항에 있어서, 주표면에 인접하여 제1웰영역에 도우프되고, 제1도우프 영역으로부터 소정거리만큼 분리된 제3도우프영역과, 전계를 형성하고, 제1 및 제3도우프영역과 사이에서 전류경로를 조정하는 제1게이트와, 주표면에 인접하여 제2웰영역에 도우프되고, 제2도우프영역으로부터 소정거리만큼 분리된 제1도전형의 제4도우프영역과, 전계를 형성하고, 제2 및 제4도우프영역 사이에서 전류경로를 조정하는 제2게이트들로 구성시킨 것을 특징으로 하는 모노리딕 상보형 반도체 장치.
  4. 제1항에 있어서, 반도체가 실리콘이며, 절연부재가 폴리-크리스탈린 실리콘의 동체와 폴리크리스탈린 실리콘의 동체를 둘러싸고 있는 절연물질층으로 이루어지게 한 것을 특징으로 하는 모노리딕 상보형 반도체 장치.
  5. 제4항에 있어서, 절연물질을 산화실리콘으로 이루어지게한 것을 특징으로 하는 모노리딕 상보형 반도체 장치.
  6. 제1항에 있어서, 기판에서 절연부재 아래에 배치된 기판의 농도보다 높은 불순물 농도를 가지며, 제2매립영역을 둘러싸고 있는 제1도전형의 반도체 아이쏘레이션 영역으로 구성시킨 것을 특징으로 하는 모노리딕 상보형 반도체 장치.
  7. 제1항에 있어서, 매립영역이 제2도전형의 제3매립영역을 가지며, 웰영역이 제2도전형의 제3웰영역으로 이루어지게 한 반도체 장치가 주표면에 인접한 제3웰영역에 형성한 제1도전형의 베이스영역과, 주표면에 인접한 제3웰영역에 형성한 제2도전형의 에미터영역과, 주표면에 인접한 제3웰영역에 형성한 제2도전형의 콜렉터접촉영역들로 구성되게 한 것을 특징으로 하는 모노리딕 상보형 반도체 장치.
  8. 제7항에 있어서, 기판에서 절연부재 아래에 배치된 기판의 농도보다 높은 불순물 농도를 가지며, 제3매립영역을 둘러싸고 있는 제1도전형의 반도체 아이쏘레이션으로 구성시킨 것을 특징으로 하는 모노리딕 상보형 반도체 장치.
  9. 제8항에 있어서, 주표면에 인접한 제1웰영역에서 그들사이에 소정거리를 두고 배치된 제2도전형의 제1 및 제3도우프영역과, 전계를 형성하고, 제1 및 제3도우프 영역사이 사이에 전류경로를 조정하는 제1게이트와, 주표면에 인접한 제2웰영역에서 그들 사이에 소정거리를 두고 배치된 제1도전형의 제2 및 제4도우프영역과, 전계를 형성하고, 제2 및 제4도우프 영역사이에 전류경로를 조정하는 제2게이트들로 구성시킨 것을 특징으로 하는 모노리딕 상보형 반도체 장치.
  10. 제9항에 있어서, 제1 및 제3도우프영역을 둘러싸고 절연부재에 인접하여 배치된 제1웰영역에 형성한 제1도전형의 채널스토퍼 영역들로 구성시킨 것을 특징으로 하는 모노리딕 상보형 반도체 장치.
  11. 제8항에 있어서, 반도체아이쏘레이션 영역이 매립영역으로부터 분리되게 한 것을 특징으로 하는 모노리딕 상보형 반도체 장치.
  12. 모노리딕상보형 장치에 있어서, 제1도전형의 반도체기판과, 기판에 배치되고, 적어도 하나이상의 제1도전형의 제1매립영역 및 제1매립영역에 인접하여 배치한 제2매립영역으로 구성시키며, 제1도전형에 반대되는 제2도전형으로 이루어진 높은 불순물 농도의 반도체매립영역과, 매립영역에 배치되고, 주표면을 형성하며, 적어도 하나이상의 제1매립영역에 배치된 제1도전형의 제1웰영역과 제2매립영역상에 배치된 제2웰영역으로 이루어진 반도체매립영역에 비교되는 낮은 불순물 농도의 반도체 웰영역과, 주표면으로부터 기판내로 연장하고, 제1웰과 매립영역을 제2웰과 매립영역으로부터 분리되게 한 절연부재들로 구성시킨 것을 특징으로 하는 모노리딕 상보형 반도체 장치.
  13. 제12항에 있어서, 기판에서 절연부재 아래에 배치된 기판의 농도보다 높은 불순물 농도를 가지고 제2매립영역을 둘러싸고 그로부터 분리되게 한 제1도전형의 반도체 버퍼영역으로 구성시킨 것을 특징으로 하는 모노리딕 상보형 반도체 장치.
  14. 바이폴라와 상보형 MOS 집적회로 장치에 있어서, 높은 저항을 가진 제1도전형의 반도체칩과, 반도체칩에 형성되고, BTJ 웰의 저부에 매립된 제2도전형의 도우프량이 많은 서브-콜렉터영역을 가진 수직 BJT로 구성시킨 BJT와, 반도체칩상에 형성되고, 제2도전형의 트랜지스터로 이루어진 제1도전형의 제1웰을 포함하며, 제1웰의 저부에 매립된 제1도전형의 도우량이 많은 매립영역과 제1도전형의 MOS 트랜지스터로 이루어진 제2도전형의 제2웰을 포함하고, 제2웰의 저부에 매립된 제2도전형의 상당량이 도우프된 제2의 매립영역을 가진 상보형 MOSFE와, 제1 및 제1의 도우프량이 많은 매립영역보다 더 깊은 깊이를 가지고 BJT와 CMOSFET를 서로 분리되게 하는 반도체칩에 배치된 절연아이쏘레이션 부재와, 반도체 칩에서 절연아이쏘레이션 부재아래에 배치된 반도체칩의 농도보다 높은 불순물 농도를 가지며 사브-콜렉터영역을 둘러싸면서 그로부터 분리된 반도체아이쏘레이션 영역들로 구성시킨 것을 특징으로 하는 모노리딕 상보형 반도체 장치.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019850007623A 1984-10-17 1985-10-16 상보형 반도체장치 KR900005124B1 (ko)

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US4862240A (en) 1989-08-29
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