KR850008759A - 저항 제조 방법 및 그에 의한 반도체 소자 - Google Patents
저항 제조 방법 및 그에 의한 반도체 소자 Download PDFInfo
- Publication number
- KR850008759A KR850008759A KR1019850003707A KR850003707A KR850008759A KR 850008759 A KR850008759 A KR 850008759A KR 1019850003707 A KR1019850003707 A KR 1019850003707A KR 850003707 A KR850003707 A KR 850003707A KR 850008759 A KR850008759 A KR 850008759A
- Authority
- KR
- South Korea
- Prior art keywords
- polysilicon
- doping
- region
- cooling
- ambient temperature
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/268—Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
- H01L21/2686—Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation using incoherent radiation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3215—Doping the layers
- H01L21/32155—Doping polycristalline - or amorphous silicon layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/20—Resistors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
- H10B10/15—Static random access memory [SRAM] devices comprising a resistor load element
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
- Y10S257/903—FET configuration adapted for use as static memory cell
- Y10S257/904—FET configuration adapted for use as static memory cell with passive components,, e.g. polysilicon resistors
Abstract
내용 없음
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 다결정 실리콘 저항의 제조에 이용된 반도체 소자에 대한 횡단면도.
제4도는 폴리실리콘 라인상의 포토레지스트의 방향을 도시한 편면도.
제7도는 본 발명에서부터 종래 기술에 이르기 까지의 저항을 비교한 그래프.
*도면의 주요 부분에 대한 부호설명
10:기판, 12:필드 산화물층, 14:폴리실리콘층, 16:폴리실리콘라인, 18:열산화물층, 20:포토레지스트.
Claims (11)
- 서로 다른 형태의 불순물로 폴리실리콘 구조체의 영역을 도핑하는 단계를 포함하는, 폴리실리콘에서의 저항제조 방법으로서, 도핑후 구조체가 가열냉각 되는 것을 특징으로 하는 저항 제조방법.
- 반도체 집적 회로용 폴리실리콘에서의 저항 제조방법으로서, 한가지 형태의 도핑 분순물을 구비한 제1영역과 상기 제1영역과 인접해있고 상기 제1영역에서의 도핑분술문과 전기적으로 반대인 도핑 분순물을 구비한 제2영역을 갖춘 폴리실리콘 구조체를 형성하고, 상기 폴리실리콘 구조체를 열처리하는 단계를 포함하는 것을 특징으로 하는 저항 제조 방법.
- 제1항이나 제2항에 있어서, 상기 가열냉각이나 열처리 단계에서는 상기 구조체를 제어된 온도로 급속가열하는 단계를 포함하는 것을 특징으로 하는 저항 제조방법.
- 선항 중 어느 항에 있어서, 가열냉각이나 열처리 단계는 구조체에서의 온도를 제어된 시간동안 고온에서 유지하고, 구조체를 제어된 방식으로 냉각하는 단계를 포함하는 것을 특징으로 하는 저항제조 방법.
- 선항중 어느항에 있어서, 상기 구조체를 급속 가열하고, 높은 주변 온도를 제어된 기간동안 유지하며, 상기 구조체를 제어된 비율로 냉각시키는 단계를 포함하는 것을 특징으로 하는 저항 제조방법.
- 제4항이나 제5항에 있어서, 상기 냉각 단계는 가열 전력을 가능한한 급속히 저감시키는 단계를 포함하는 것을 특징으로 하는 저항 제조방법.
- 선항중 어느 항에 있어서, 구조체의 주변 온도를 900℃이상 1200℃이하로 급속히 변경시키고, 주변온도를 약 5초간 유지하며, 주변온도를 제어된 비율로 저감시키는 단계를 포함하는 것을 특징으로 하는 저항 제조방법.
- 실리콘 기판상에 산화물층이나 폴리실리콘층을 첨가하고, 한가지 전도형의 제1도판트로 폴리실리콘을 도핑하며, 다른 전도형의 제2도판트로 폴리실리콘 부분을 도핑하며, 반도체 소자를 가열 냉각하는 단계를 포함하는 것을 특징으로 하는 반도체 소자 제조방법.
- 선항에서 청구된 바와 같은 방법으로 제조된 것을 특징으로 하는 반도체 소자.
- 실리콘 기판상에 산화물층과,한가지 전도형의 불순물로 도핑된 제1영역, 다른 전도형의 불순물로 도핑된 제2영역을, 갖춘 폴리실리콘층을 첨가한, 실리콘 기판을 포함한 반도체 소자로서, 상기 제1 및 제2 영역의 도핑후 가열 냉각된 것을 특징으로 하는 반도체 소자.
- ※참고사항:최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US615,166 | 1984-05-30 | ||
US615166 | 1984-05-30 | ||
US06/615,166 US4560419A (en) | 1984-05-30 | 1984-05-30 | Method of making polysilicon resistors with a low thermal activation energy |
Publications (2)
Publication Number | Publication Date |
---|---|
KR850008759A true KR850008759A (ko) | 1985-12-21 |
KR940001890B1 KR940001890B1 (ko) | 1994-03-10 |
Family
ID=24464276
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019850003707A KR940001890B1 (ko) | 1984-05-30 | 1985-05-29 | 폴리실리콘 저항 제조방법 및 그에 의한 반도체 소자 |
Country Status (7)
Country | Link |
---|---|
US (1) | US4560419A (ko) |
EP (1) | EP0167249B1 (ko) |
JP (1) | JPS60262453A (ko) |
KR (1) | KR940001890B1 (ko) |
AT (1) | ATE51319T1 (ko) |
CA (1) | CA1213680A (ko) |
DE (1) | DE3576762D1 (ko) |
Families Citing this family (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4616404A (en) * | 1984-11-30 | 1986-10-14 | Advanced Micro Devices, Inc. | Method of making improved lateral polysilicon diode by treating plasma etched sidewalls to remove defects |
US4637836A (en) * | 1985-09-23 | 1987-01-20 | Rca Corporation | Profile control of boron implant |
JPH07101677B2 (ja) * | 1985-12-02 | 1995-11-01 | 株式会社東芝 | 半導体装置の製造方法 |
US4745079A (en) * | 1987-03-30 | 1988-05-17 | Motorola, Inc. | Method for fabricating MOS transistors having gates with different work functions |
GB8710359D0 (en) * | 1987-05-01 | 1987-06-03 | Inmos Ltd | Semiconductor element |
US5248623A (en) * | 1988-02-19 | 1993-09-28 | Nippondenso Co., Ltd. | Method for making a polycrystalline diode having high breakdown |
JPH02185069A (ja) * | 1988-12-02 | 1990-07-19 | Motorola Inc | 高エネルギー阻止能力及び温度補償された阻止電圧を具備する半導体デバイス |
US5126279A (en) * | 1988-12-19 | 1992-06-30 | Micron Technology, Inc. | Single polysilicon cross-coupled resistor, six-transistor SRAM cell design technique |
US5196233A (en) * | 1989-01-18 | 1993-03-23 | Sgs-Thomson Microelectronics, Inc. | Method for fabricating semiconductor circuits |
US5065362A (en) * | 1989-06-02 | 1991-11-12 | Simtek Corporation | Non-volatile ram with integrated compact static ram load configuration |
US5151387A (en) | 1990-04-30 | 1992-09-29 | Sgs-Thomson Microelectronics, Inc. | Polycrystalline silicon contact structure |
US5141597A (en) * | 1990-11-14 | 1992-08-25 | United Technologies Corporation | Thin polysilicon resistors |
US5581159A (en) * | 1992-04-07 | 1996-12-03 | Micron Technology, Inc. | Back-to-back diode current regulator for field emission display |
JP2934738B2 (ja) | 1994-03-18 | 1999-08-16 | セイコーインスツルメンツ株式会社 | 半導体装置およびその製造方法 |
US5847515A (en) * | 1996-11-01 | 1998-12-08 | Micron Technology, Inc. | Field emission display having multiple brightness display modes |
US6140684A (en) * | 1997-06-24 | 2000-10-31 | Stmicroelectronic, Inc. | SRAM cell structure with dielectric sidewall spacers and drain and channel regions defined along sidewall spacers |
US6455392B2 (en) | 2000-01-21 | 2002-09-24 | Bae Systems Information And Electrical Systems Integration, Inc. | Integrated resistor having aligned body and contact and method for forming the same |
US8072834B2 (en) * | 2005-08-25 | 2011-12-06 | Cypress Semiconductor Corporation | Line driver circuit and method with standby mode of operation |
US7881118B2 (en) * | 2007-05-25 | 2011-02-01 | Cypress Semiconductor Corporation | Sense transistor protection for memory programming |
US8059458B2 (en) * | 2007-12-31 | 2011-11-15 | Cypress Semiconductor Corporation | 3T high density nvDRAM cell |
US8064255B2 (en) * | 2007-12-31 | 2011-11-22 | Cypress Semiconductor Corporation | Architecture of a nvDRAM array and its sense regime |
Family Cites Families (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CH581904A5 (ko) * | 1974-08-29 | 1976-11-15 | Centre Electron Horloger | |
US3943545A (en) * | 1975-05-22 | 1976-03-09 | Fairchild Camera And Instrument Corporation | Low interelectrode leakage structure for charge-coupled devices |
JPS5810863B2 (ja) * | 1978-04-24 | 1983-02-28 | 株式会社日立製作所 | 半導体装置 |
US4309224A (en) * | 1978-10-06 | 1982-01-05 | Tokyo Shibaura Denki Kabushiki Kaisha | Method for manufacturing a semiconductor device |
US4214918A (en) * | 1978-10-12 | 1980-07-29 | Stanford University | Method of forming polycrystalline semiconductor interconnections, resistors and contacts by applying radiation beam |
US4290185A (en) * | 1978-11-03 | 1981-09-22 | Mostek Corporation | Method of making an extremely low current load device for integrated circuit |
JPS5688818A (en) * | 1979-12-17 | 1981-07-18 | Hitachi Ltd | Polycrystalline silicon membrane and its production |
JPS5687354A (en) * | 1979-12-17 | 1981-07-15 | Matsushita Electric Ind Co Ltd | Formation of resistor body |
US4331485A (en) * | 1980-03-03 | 1982-05-25 | Arnon Gat | Method for heat treating semiconductor material using high intensity CW lamps |
US4381201A (en) * | 1980-03-11 | 1983-04-26 | Fujitsu Limited | Method for production of semiconductor devices |
US4409724A (en) * | 1980-11-03 | 1983-10-18 | Texas Instruments Incorporated | Method of fabricating display with semiconductor circuits on monolithic structure and flat panel display produced thereby |
JPS57133660A (en) * | 1981-02-10 | 1982-08-18 | Matsushita Electric Ind Co Ltd | Controlling method for resistance value of polycrystalline semiconductor |
JPS57133661A (en) * | 1981-02-10 | 1982-08-18 | Matsushita Electric Ind Co Ltd | Heat treatment for polycrystalline semiconductor |
US4467518A (en) * | 1981-05-19 | 1984-08-28 | Ibm Corporation | Process for fabrication of stacked, complementary MOS field effect transistor circuits |
JPS5880852A (ja) * | 1981-11-10 | 1983-05-16 | Toshiba Corp | 半導体装置の製造方法 |
US4467519A (en) * | 1982-04-01 | 1984-08-28 | International Business Machines Corporation | Process for fabricating polycrystalline silicon film resistors |
JPS5946057A (ja) * | 1982-09-08 | 1984-03-15 | Nec Corp | 半導体装置の製造方法 |
US4658378A (en) * | 1982-12-15 | 1987-04-14 | Inmos Corporation | Polysilicon resistor with low thermal activation energy |
US4489104A (en) * | 1983-06-03 | 1984-12-18 | Industrial Technology Research Institute | Polycrystalline silicon resistor having limited lateral diffusion |
-
1984
- 1984-05-30 US US06/615,166 patent/US4560419A/en not_active Expired - Lifetime
- 1984-09-18 CA CA000463510A patent/CA1213680A/en not_active Expired
-
1985
- 1985-05-14 DE DE8585303396T patent/DE3576762D1/de not_active Expired - Lifetime
- 1985-05-14 EP EP85303396A patent/EP0167249B1/en not_active Expired - Lifetime
- 1985-05-14 AT AT85303396T patent/ATE51319T1/de not_active IP Right Cessation
- 1985-05-29 JP JP60116298A patent/JPS60262453A/ja active Pending
- 1985-05-29 KR KR1019850003707A patent/KR940001890B1/ko active IP Right Grant
Also Published As
Publication number | Publication date |
---|---|
ATE51319T1 (de) | 1990-04-15 |
CA1213680A (en) | 1986-11-04 |
EP0167249B1 (en) | 1990-03-21 |
JPS60262453A (ja) | 1985-12-25 |
EP0167249A3 (en) | 1986-03-12 |
EP0167249A2 (en) | 1986-01-08 |
KR940001890B1 (ko) | 1994-03-10 |
US4560419A (en) | 1985-12-24 |
DE3576762D1 (de) | 1990-04-26 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR850008759A (ko) | 저항 제조 방법 및 그에 의한 반도체 소자 | |
US4679170A (en) | Resistor with low thermal activation energy | |
US7436044B2 (en) | Electrical fuses comprising thin film transistors (TFTS), and methods for programming same | |
KR910019174A (ko) | 시간종속 유전체 결함을 감소시킨 반도체 장치및 그 제조방법 | |
US4394191A (en) | Stacked polycrystalline silicon film of high and low conductivity layers | |
US3333326A (en) | Method of modifying electrical characteristic of semiconductor member | |
US3434021A (en) | Insulated gate field effect transistor | |
US4080618A (en) | Insulated-gate field-effect transistor | |
US3497773A (en) | Passive circuit elements | |
JPH0818011A (ja) | 半導体装置及びその製造方法 | |
KR930022557A (ko) | 반도체 집적 회로 장치 및 그 제조방법 | |
US6974751B2 (en) | Semiconductor device and method for producing the same | |
JPH07297394A (ja) | 半導体装置およびその製造方法 | |
JPS6238865B2 (ko) | ||
JPH03166757A (ja) | 半導体装置 | |
JP2534608B2 (ja) | 半導体装置の製造方法 | |
KR970030791A (ko) | 반도체 소자의 저항 제조방법 | |
JPH0778831A (ja) | 熱処理方法 | |
KR970008588A (ko) | 반도체 기억소자 및 그 제조방법 | |
JPH021178A (ja) | 多結晶ダイオードおよびその製造方法 | |
KR960026929A (ko) | 트랜지스터 제조방법 | |
JPS63308367A (ja) | 半導体集積回路 | |
JPS62149172A (ja) | 不純物導入方法 | |
JPS61236150A (ja) | 半導体装置 | |
JPS6294924A (ja) | 半導体装置の製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
E902 | Notification of reason for refusal | ||
E902 | Notification of reason for refusal | ||
G160 | Decision to publish patent application | ||
E701 | Decision to grant or registration of patent right | ||
NORF | Unpaid initial registration fee |