JPS57133661A - Heat treatment for polycrystalline semiconductor - Google Patents

Heat treatment for polycrystalline semiconductor

Info

Publication number
JPS57133661A
JPS57133661A JP1878781A JP1878781A JPS57133661A JP S57133661 A JPS57133661 A JP S57133661A JP 1878781 A JP1878781 A JP 1878781A JP 1878781 A JP1878781 A JP 1878781A JP S57133661 A JPS57133661 A JP S57133661A
Authority
JP
Japan
Prior art keywords
layer
poly
film
resistance
ions
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1878781A
Other languages
Japanese (ja)
Inventor
Haruhide Fuse
Koichi Kugimiya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP1878781A priority Critical patent/JPS57133661A/en
Publication of JPS57133661A publication Critical patent/JPS57133661A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering

Abstract

PURPOSE:To improve the quality of a film, and to ameliorate the controllability and stability of resistance value by introducing the P type or N type impurity of predetermined concentration or lower to the polycrystalline semiconductor made of poly Si, etc., melting the surface through high energy density beam irradiation and thermally treating the surface. CONSTITUTION:A film such as an SiO2 film 2 is formed onto an Si substrate 1, a poly Si layer 3 is deposited through a decompression CVD method, and patterned, ions such as B ions 4 are implanted under a condition set so that mean concentration reaches 10<19>cm<-3> or lower, and an implantation layer 3' is shaped. Laser beams such as Ar laser beams are irradiated under a condition that the surface is heated at 320 deg.C, the layer 3' is melted, and a poly Si layer 6 in which grains grow is formed. The surface is thermally treated for approximately 30min in N2 at 500-1,000 deg.C, and a poly Si resistance layer 7 having predetermined sheet resistance is shaped. Accordingly, since a trap existing in the crystalline grain boundary of poly Si and a defect generated due to thermal strain can be reduced, the quality of the film can be improved, and the resistance layer, the resistance value thereof can be controlled by the quantity of doping and a secular change thereof is small, can be manufactured.
JP1878781A 1981-02-10 1981-02-10 Heat treatment for polycrystalline semiconductor Pending JPS57133661A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1878781A JPS57133661A (en) 1981-02-10 1981-02-10 Heat treatment for polycrystalline semiconductor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1878781A JPS57133661A (en) 1981-02-10 1981-02-10 Heat treatment for polycrystalline semiconductor

Publications (1)

Publication Number Publication Date
JPS57133661A true JPS57133661A (en) 1982-08-18

Family

ID=11981317

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1878781A Pending JPS57133661A (en) 1981-02-10 1981-02-10 Heat treatment for polycrystalline semiconductor

Country Status (1)

Country Link
JP (1) JPS57133661A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6074466A (en) * 1983-06-17 1985-04-26 テキサス　インスツルメンツ　インコ−ポレイテツド Method of producing polysilicon resistance element
JPS60262453A (en) * 1984-05-30 1985-12-25 ソーン、イーエムアイ、ノース、アメリカ、インコーポレーテッド Method of forming resistor in polysilicon and semiconductor element
US5126277A (en) * 1988-06-07 1992-06-30 Oki Electric Industry Co., Ltd. Method of manufacturing a semiconductor device having a resistor

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6074466A (en) * 1983-06-17 1985-04-26 テキサス　インスツルメンツ　インコ−ポレイテツド Method of producing polysilicon resistance element
JPH0587986B2 (en) * 1983-06-17 1993-12-20 Texas Instruments Inc
JPS60262453A (en) * 1984-05-30 1985-12-25 ソーン、イーエムアイ、ノース、アメリカ、インコーポレーテッド Method of forming resistor in polysilicon and semiconductor element
US5126277A (en) * 1988-06-07 1992-06-30 Oki Electric Industry Co., Ltd. Method of manufacturing a semiconductor device having a resistor

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