KR850008017A - Cmos 입출력회로 - Google Patents
Cmos 입출력회로 Download PDFInfo
- Publication number
- KR850008017A KR850008017A KR1019850003675A KR850003675A KR850008017A KR 850008017 A KR850008017 A KR 850008017A KR 1019850003675 A KR1019850003675 A KR 1019850003675A KR 850003675 A KR850003675 A KR 850003675A KR 850008017 A KR850008017 A KR 850008017A
- Authority
- KR
- South Korea
- Prior art keywords
- electrical
- input
- output
- signal
- circuit
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
- G06F13/4072—Drivers or receivers
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/01—Shaping pulses
- H03K5/02—Shaping pulses by amplifying
- H03K5/026—Shaping pulses by amplifying with a bidirectional operation
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Computer Hardware Design (AREA)
- Logic Circuits (AREA)
- Microcomputers (AREA)
Abstract
내용 없음
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명에 의한 CMOS 입 출력회로의 일 실시예.
제2도는 본 발명에 의한 복수의 CMOS입 출력회로의 블럭도.
제3도는 본 발명에 의한 CMOS 입 출력회로의 데이터 출력모우드를 표시한 타이밍도.
*도면의 주요 부분에 대한 부호의 설명
102,104,106,108 : CMOS 입출력회로, 200 : 일시기억회로, 206 : 입력버퍼, 208 : 입력 제어회로.
Claims (3)
- 데이터 버스의 정보를 일시 기억하는 회로와, 신호입력부와, I/O 포오트에 접속된 신호 출력부를 보유하고, 전기 데이터 버스의 정보를 전기 I/O 포오트에 출력하는 CMOS 출력버퍼와, 전기 기억회로의 출력부와 전기 CMOS 출력버퍼의 출력부간에 접속되고 제어신호가 입력되면 전기 CMOS 출력버퍼를 프로오팅 상태로 하는 출력제어 회로와, 신호 입력부와, 전기 데이터 버스에 접속된 신호출력부를 보유하고, 선택적으로 전기 I/O 포오트의 정보를 전기 데이터 버스에 전달하는 입력 버퍼회로와, 전기 I/O 포오트와 전기신호 전송회로의 신호입력부간에 접속되고, 전기 제어신호가 입력되면 전기 I/O 포오트의 정보에 관계없이 "L" 또는 "H" 레벨에 고정된 신호를 출력하는 입력 제어회로를 보유함을 특징으로 하는 CMOS 입출력회로.
- 제1항에 있어서, 전기입력제어회로가 CMOS 구성으로 되는 것을 특징으로 하는 CMOS 입출력회로.
- 제2항에 있어서, 전기입력제어회로가 NOR 논리회로인 것을 특징으로 하는 CMOS 입출력회로.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59-108475 | 1984-05-28 | ||
JP59108475A JPS60252979A (ja) | 1984-05-30 | 1984-05-30 | Cmos入出力回路 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR850008017A true KR850008017A (ko) | 1985-12-11 |
KR910001327B1 KR910001327B1 (ko) | 1991-03-04 |
Family
ID=14485697
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019850003675A KR910001327B1 (ko) | 1984-05-30 | 1985-05-28 | Cmos 입 출력회로 |
Country Status (5)
Country | Link |
---|---|
US (1) | US4680491A (ko) |
EP (1) | EP0163305B1 (ko) |
JP (1) | JPS60252979A (ko) |
KR (1) | KR910001327B1 (ko) |
DE (1) | DE3583537D1 (ko) |
Families Citing this family (36)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61208251A (ja) * | 1985-03-12 | 1986-09-16 | Matsushita Electronics Corp | 集積回路装置 |
JPS62197856A (ja) * | 1986-02-25 | 1987-09-01 | Matsushita Electric Ind Co Ltd | マイクロコンピユ−タ |
FR2609831B1 (fr) * | 1987-01-16 | 1989-03-31 | Thomson Semiconducteurs | Circuit de lecture pour memoire |
US4804864A (en) * | 1987-03-09 | 1989-02-14 | Rockwell International Corporation | Multiphase CMOS toggle flip-flop |
US4774422A (en) * | 1987-05-01 | 1988-09-27 | Digital Equipment Corporation | High speed low pin count bus interface |
US4829515A (en) * | 1987-05-01 | 1989-05-09 | Digital Equipment Corporation | High performance low pin count bus interface |
JPH01100656A (ja) * | 1987-10-13 | 1989-04-18 | Nec Corp | マイクロコンピュータの出力回路 |
US4835418A (en) * | 1987-11-17 | 1989-05-30 | Xilinx, Inc. | Three-state bidirectional buffer |
US4908796A (en) * | 1988-05-24 | 1990-03-13 | Dallas Semiconductor Corporation | Registered outputs for a memory device |
US4987319A (en) * | 1988-09-08 | 1991-01-22 | Kawasaki Steel Corporation | Programmable input/output circuit and programmable logic device |
US4982115A (en) * | 1989-02-02 | 1991-01-01 | Rockwell International Corporation | Digital signal direction detection circuit |
JPH0821846B2 (ja) * | 1989-02-03 | 1996-03-04 | 日本電気株式会社 | ワイアード信号ドライブ回路 |
EP0420203A3 (en) * | 1989-09-29 | 1991-06-19 | Siemens Aktiengesellschaft | Circuit for controlling a bidirectional bus drive |
US5030853A (en) * | 1990-03-21 | 1991-07-09 | Thunderbird Technologies, Inc. | High speed logic and memory family using ring segment buffer |
US5105105A (en) * | 1990-03-21 | 1992-04-14 | Thunderbird Technologies, Inc. | High speed logic and memory family using ring segment buffer |
US5043606A (en) * | 1990-03-30 | 1991-08-27 | Seagate Technology, Inc. | Apparatus and method for programmably controlling the polarity of an I/O signal of a magnetic disk drive |
JP2604276B2 (ja) * | 1990-11-20 | 1997-04-30 | 三菱電機株式会社 | 半導体記憶装置 |
JPH05233840A (ja) * | 1991-08-23 | 1993-09-10 | Oki Electric Ind Co Ltd | 半導体装置 |
EP0574177B2 (en) * | 1992-06-12 | 2003-08-20 | Texas Instruments Incorporated | Method and apparatus for changing processor clock rate |
US5602496A (en) * | 1992-06-17 | 1997-02-11 | Advanced Micro Devices, Inc. | Input buffer circuit including an input level translator with sleep function |
US5424589A (en) * | 1993-02-12 | 1995-06-13 | The Board Of Trustees Of The Leland Stanford Junior University | Electrically programmable inter-chip interconnect architecture |
US5324996A (en) * | 1993-02-16 | 1994-06-28 | Ast Research, Inc. | Floating fault tolerant input buffer circuit |
US5373470A (en) * | 1993-03-26 | 1994-12-13 | United Memories, Inc. | Method and circuit for configuring I/O devices |
JP3406444B2 (ja) * | 1995-01-10 | 2003-05-12 | 富士通株式会社 | データ転送システムのバス制御装置 |
US5517135A (en) * | 1995-07-26 | 1996-05-14 | Xilinx, Inc. | Bidirectional tristate buffer with default input |
CA2192426C (en) * | 1996-01-03 | 2000-08-01 | Richard Ng | Bidirectional voltage translator |
FR2753586B1 (fr) * | 1996-09-18 | 1998-11-20 | Sgs Thomson Microelectronics | Circuit tampon de sortie de signaux logiques |
US6023174A (en) * | 1997-07-11 | 2000-02-08 | Vanguard International Semiconductor Corporation | Adjustable, full CMOS input buffer for TTL, CMOS, or low swing input protocols |
JPH11175502A (ja) * | 1997-12-08 | 1999-07-02 | Mitsubishi Electric Corp | 半導体装置 |
DE19855372A1 (de) * | 1998-12-01 | 2000-06-08 | Bosch Gmbh Robert | Vorrichtung zur bidirektionalen Signalübertragung |
JP2000183719A (ja) * | 1998-12-11 | 2000-06-30 | Nec Corp | 入力回路、出力回路及び入出力回路、並びに該入出力回路を備えた信号伝送システム |
KR100465599B1 (ko) | 2001-12-07 | 2005-01-13 | 주식회사 하이닉스반도체 | 데이타 출력 버퍼 |
US7230450B2 (en) * | 2004-05-18 | 2007-06-12 | Intel Corporation | Programming semiconductor dies for pin map compatibility |
US7577029B2 (en) | 2007-05-04 | 2009-08-18 | Mosaid Technologies Incorporated | Multi-level cell access buffer with dual function |
US7795914B2 (en) * | 2007-11-02 | 2010-09-14 | International Business Machines Corporation | Circuit design methodology to reduce leakage power |
US10322309B2 (en) | 2014-09-19 | 2019-06-18 | Doree Feldman | Weighted garment |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4063225A (en) * | 1976-03-08 | 1977-12-13 | Rca Corporation | Memory cell and array |
JPS6041364B2 (ja) * | 1980-08-29 | 1985-09-17 | 富士通株式会社 | 出力バッファ回路 |
JPH11774A (ja) * | 1997-06-10 | 1999-01-06 | Ishikawajima Harima Heavy Ind Co Ltd | レーザ・ウォータジェット複合切断方法及び装置 |
-
1984
- 1984-05-30 JP JP59108475A patent/JPS60252979A/ja active Granted
-
1985
- 1985-05-28 KR KR1019850003675A patent/KR910001327B1/ko not_active IP Right Cessation
- 1985-05-29 US US06/739,304 patent/US4680491A/en not_active Expired - Lifetime
- 1985-05-30 EP EP85106665A patent/EP0163305B1/en not_active Revoked
- 1985-05-30 DE DE8585106665T patent/DE3583537D1/de not_active Revoked
Also Published As
Publication number | Publication date |
---|---|
EP0163305B1 (en) | 1991-07-24 |
KR910001327B1 (ko) | 1991-03-04 |
JPH0142013B2 (ko) | 1989-09-08 |
JPS60252979A (ja) | 1985-12-13 |
US4680491A (en) | 1987-07-14 |
EP0163305A2 (en) | 1985-12-04 |
EP0163305A3 (en) | 1988-05-18 |
DE3583537D1 (de) | 1991-08-29 |
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