KR890006003A - 데이타 입출력 회로 - Google Patents

데이타 입출력 회로 Download PDF

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Publication number
KR890006003A
KR890006003A KR1019880011904A KR880011904A KR890006003A KR 890006003 A KR890006003 A KR 890006003A KR 1019880011904 A KR1019880011904 A KR 1019880011904A KR 880011904 A KR880011904 A KR 880011904A KR 890006003 A KR890006003 A KR 890006003A
Authority
KR
South Korea
Prior art keywords
shift register
data
output
input
reversible shift
Prior art date
Application number
KR1019880011904A
Other languages
English (en)
Other versions
KR960005751B1 (ko
Inventor
마사히사 시미즈
히데끼 오하시
마사끼 가와구찌
미쯔요시 후꾸다
Original Assignee
이우에 사또시
상요덴기 가부시기가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 이우에 사또시, 상요덴기 가부시기가이샤 filed Critical 이우에 사또시
Publication of KR890006003A publication Critical patent/KR890006003A/ko
Application granted granted Critical
Publication of KR960005751B1 publication Critical patent/KR960005751B1/ko

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/76—Arrangements for rearranging, permuting or selecting data according to predetermined rules, independently of the content of the data
    • G06F7/768—Data position reversal, e.g. bit reversal, byte swapping
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M9/00—Parallel/series conversion or vice versa

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Communication Control (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Shift Register Type Memory (AREA)

Abstract

내용 없음

Description

데이타 입출력 회로
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 실시예를 도시한 블록도.
제2도는 직렬 데이타 전송의 포맷을 도시한 도면.

Claims (1)

  1. 데이타의 프리셋트 가능한 N비트의 가역 시프트레지스터와, 외부에서 직렬로 입력되는 데이타를 상기 가역 시프트레지스터의 임의의 단의 입력에 선택적으로 인가하는 입력 게이트회로와, 상기 가역 시프트레지스터의 임의의 단의 출력을 선택해서 직렬로 출력하는 출력 게이트회로와, 상기 가역 시프트레지스터의 임의의 M비트 출력에 접속되고, 상기 가역 시프트레지스터에 취입된 데이타를 보존하여 데이타 버스에 송출하는 입력 래치 회로와, 상기 가역 시프트레지스터의 임의의 M비트의 프리셋트 단자에 접속되고, 상기 데이타 버스에서 수치한 데이타를 상기 가역 시프트레지스터에 프리셋트하는 출력 래치 회로를 구비하고, 다른 형식의 직렬 데이타 송 수신에 대응가능하게 한 것을 특징으로 하는 데이타 입출력 회로.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019880011904A 1987-09-16 1988-09-15 데이타 입출력 회로 KR960005751B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP62231576A JPH0782423B2 (ja) 1987-09-16 1987-09-16 データ入出力回路
JP87-231576 1987-09-16
JP62-231576 1987-09-16

Publications (2)

Publication Number Publication Date
KR890006003A true KR890006003A (ko) 1989-05-18
KR960005751B1 KR960005751B1 (ko) 1996-05-01

Family

ID=16925683

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019880011904A KR960005751B1 (ko) 1987-09-16 1988-09-15 데이타 입출력 회로

Country Status (5)

Country Link
US (1) US5489901A (ko)
EP (1) EP0311798B1 (ko)
JP (1) JPH0782423B2 (ko)
KR (1) KR960005751B1 (ko)
DE (1) DE3889612T2 (ko)

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US5799211A (en) * 1996-03-22 1998-08-25 General Electric Company Shift register having latch cell operable in serial-in/parallel-out and parallel-in/serial-out modes in response to a sequence of commands for controlling appropriate switches
EP0858178B1 (de) * 1997-02-06 2006-06-21 Studer Professional Audio GmbH Verfahren und Vorrichtung zum Mischen von digitalen Audio-Signalen
US6405092B1 (en) * 1997-09-29 2002-06-11 William Vincent Oxford Method and apparatus for amplifying and attenuating digital audio
US7616200B1 (en) 1998-06-12 2009-11-10 3Dlabs Inc. Ltd. System for reducing aliasing on a display device
WO2000004495A1 (en) 1998-07-17 2000-01-27 Intergraph Corporation System for processing vertices from a graphics request stream
WO2000004482A2 (en) 1998-07-17 2000-01-27 Intergraph Corporation Multi-processor graphics accelerator
US6577316B2 (en) 1998-07-17 2003-06-10 3Dlabs, Inc., Ltd Wide instruction word graphics processor
US6480913B1 (en) * 1998-07-17 2002-11-12 3Dlabs Inc. Led. Data sequencer with MUX select input for converting input data stream and to specific output data stream using two exclusive-or logic gates and counter
WO2000004527A1 (en) * 1998-07-17 2000-01-27 Intergraph Corporation Apparatus and method of directing graphical data to a display device
US7518616B1 (en) 1998-07-17 2009-04-14 3Dlabs, Inc. Ltd. Graphics processor with texture memory allocation system
US6181355B1 (en) 1998-07-17 2001-01-30 3Dlabs Inc. Ltd. Graphics processing with transcendental function generator
WO2000004494A1 (en) 1998-07-17 2000-01-27 Intergraph Corporation Graphics processing system with multiple strip breakers
US6459453B1 (en) 1998-07-17 2002-10-01 3Dlabs Inc. Ltd. System for displaying a television signal on a computer monitor
US6674440B1 (en) 1999-04-05 2004-01-06 3Dlabs, Inc., Inc. Ltd. Graphics processor for stereoscopically displaying a graphical image
US6388589B1 (en) * 2000-07-17 2002-05-14 Trw Inc. Programmable video interface
US6734707B2 (en) * 2002-01-11 2004-05-11 Samsung Electronics Co., Ltd. Data input circuit for reducing loading difference between fetch signal and multiple data in semiconductor device
TWI226601B (en) * 2003-01-17 2005-01-11 Winbond Electronics Corp System and method of synthesizing a plurality of voices
JP5060803B2 (ja) * 2007-03-08 2012-10-31 ラピスセミコンダクタ株式会社 直列インタフェース回路
US9881664B1 (en) * 2017-01-12 2018-01-30 Cadence Design Systems, Inc. Per-group delay line architecture to de-skew input/output timing between a high bandwidth memory (HBM) physical (PHY) interface and the HBM device

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3432243A (en) * 1963-10-10 1969-03-11 George K C Hardesty Ratio spectroradiometer
DE1962362A1 (de) * 1969-12-12 1971-06-16 Olympia Werke Ag Schaltungsanordnung fuer ein Rechenwerk
US3742466A (en) * 1971-11-24 1973-06-26 Honeywell Inf Systems Memory system for receiving and transmitting information over a plurality of communication lines
US3967101A (en) * 1975-03-17 1976-06-29 Honeywell Information Systems, Inc. Data alignment circuit
US3971920A (en) * 1975-05-05 1976-07-27 The Bendix Corporation Digital time-off-event encoding system
US4079372A (en) * 1976-05-03 1978-03-14 The United States Of America As Represented By The Secretary Of The Navy Serial to parallel converter
JPS55141823A (en) * 1979-04-24 1980-11-06 Fujitsu Ltd Data read-out circuit
US4504925A (en) * 1982-01-18 1985-03-12 M/A-Com Linkabit, Inc. Self-shifting LIFO stack
NL8202365A (nl) * 1982-06-11 1984-01-02 Philips Nv Serie-parallel-serie schuifregistergeheugen, hetwelk redundante parallelgeschakelde opslagregisters bevat, en afbeeldtoestel, voorzien van een zodanig georganiseerd beeldgeheugen.
US4594685A (en) * 1983-06-24 1986-06-10 General Signal Corporation Watchdog timer
DE3373730D1 (en) * 1983-12-15 1987-10-22 Ibm Series-parallel/parallel-series device for variable bit length configuration
US4620180A (en) * 1985-10-21 1986-10-28 Northern Telecom Limited Serial-to-parallel converter for high-speed bit streams

Also Published As

Publication number Publication date
EP0311798B1 (en) 1994-05-18
DE3889612T2 (de) 1995-01-12
DE3889612D1 (de) 1994-06-23
US5489901A (en) 1996-02-06
KR960005751B1 (ko) 1996-05-01
JPH0782423B2 (ja) 1995-09-06
EP0311798A2 (en) 1989-04-19
JPS6474615A (en) 1989-03-20
EP0311798A3 (en) 1991-04-24

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