KR920007187A - 반도체 기억장치 - Google Patents
반도체 기억장치 Download PDFInfo
- Publication number
- KR920007187A KR920007187A KR1019910015462A KR910015462A KR920007187A KR 920007187 A KR920007187 A KR 920007187A KR 1019910015462 A KR1019910015462 A KR 1019910015462A KR 910015462 A KR910015462 A KR 910015462A KR 920007187 A KR920007187 A KR 920007187A
- Authority
- KR
- South Korea
- Prior art keywords
- holding
- information
- reading
- transmitting
- holding means
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title 1
- 230000005540 biological transmission Effects 0.000 claims 3
- 238000010586 diagram Methods 0.000 description 3
- 230000009977 dual effect Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
- G11C7/1093—Input synchronization
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
- G11C7/1039—Read-write modes for single port memories, i.e. having either a random port or a serial port using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
- G11C7/106—Data output latches
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1075—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for multiport memories each having random access ports and serial ports, e.g. video RAM
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
- G11C7/1087—Data input latches
Abstract
내용 없음
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 이 발명의 한 실시예에 의한 듀얼포트 메모리에 포함되는 입출력회로의 구성을 표시하는 회로도,
제2도는 동실시예에 사용되는 클럭제네레이터의 구성을 표시하는 도면,
제3도는 제1도의 입출력회로의 동작을 설명하기 위한 파형도.
Claims (1)
- 복수의 정보를 기억하는 기억수단, 상기 기억수단에 기억된 정보를 시리얼로 판독하는 판독수단, 상기 판독수단에 의하여 판독된 정보를 유지하기 위한 제1의 유지수단, 상기 제1의 유지수단으로 부터 주어지는 정보를 유지하기 위한 제2의 유지수단, 상기 판독수단에 의하여 판독된 정보를 상기 제1의 유지수단으로 전송하는 제1의 전송수단, 상기 제1의 유지수단으로 부터 상기 제2의 유지수단으로 정보를 전송하는 제2의 전송수단, 상기 제2의 유지수단에 유지된 정보를 외부로 출력하는 출력수단 및 상기 제2의 전송수단에 의한 전송동작이 행하여진후 상기 출력수단에 의한 출력동작이 행하여지고, 그후 상기 제1의 전송수단에 의한 전송동작이 행하여지도록 제어를 행하는 제어수단을 구비한 반도체 기억장치.※ 참고사항 : 최초출원 내용에 의하여 공개되는 것임.
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2-243007 | 1990-09-12 | ||
JP90-243007 | 1990-09-12 | ||
JP2243007A JPH04121893A (ja) | 1990-09-12 | 1990-09-12 | 半導体記憶装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR920007187A true KR920007187A (ko) | 1992-04-28 |
KR960006878B1 KR960006878B1 (ko) | 1996-05-23 |
Family
ID=17097505
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019910015462A KR960006878B1 (ko) | 1990-09-12 | 1991-09-04 | 반도체 기억장치 |
Country Status (4)
Country | Link |
---|---|
US (1) | US5229965A (ko) |
JP (1) | JPH04121893A (ko) |
KR (1) | KR960006878B1 (ko) |
DE (1) | DE4130205A1 (ko) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR0147398B1 (ko) * | 1992-10-09 | 1998-12-01 | 로오라 케이 니퀴스트 | 랜덤 액세스 메모리 |
JP2985554B2 (ja) * | 1993-02-03 | 1999-12-06 | 日本電気株式会社 | 記憶回路 |
US5457654A (en) * | 1994-07-26 | 1995-10-10 | Micron Technology, Inc. | Memory circuit for pre-loading a serial pipeline |
KR0167687B1 (ko) * | 1995-09-11 | 1999-02-01 | 김광호 | 고속액세스를 위한 데이타 출력패스를 구비하는 반도체 메모리장치 |
US6154056A (en) * | 1997-06-09 | 2000-11-28 | Micron Technology, Inc. | Tri-stating address input circuit |
JP3983969B2 (ja) * | 2000-03-08 | 2007-09-26 | 株式会社東芝 | 不揮発性半導体記憶装置 |
KR20040038081A (ko) * | 2002-10-31 | 2004-05-08 | 주식회사 맥시멈 | 세탁물 건조용 행거 |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58182185A (ja) * | 1982-04-19 | 1983-10-25 | Nec Corp | 半導体記憶装置 |
US4541075A (en) * | 1982-06-30 | 1985-09-10 | International Business Machines Corporation | Random access memory having a second input/output port |
JPS60119698A (ja) * | 1983-12-01 | 1985-06-27 | Fujitsu Ltd | 半導体メモリ |
JPS62226498A (ja) * | 1986-03-28 | 1987-10-05 | Hitachi Ltd | 半導体記憶装置 |
JPH0682520B2 (ja) * | 1987-07-31 | 1994-10-19 | 株式会社東芝 | 半導体メモリ |
-
1990
- 1990-09-12 JP JP2243007A patent/JPH04121893A/ja active Pending
-
1991
- 1991-09-04 US US07/754,897 patent/US5229965A/en not_active Expired - Fee Related
- 1991-09-04 KR KR1019910015462A patent/KR960006878B1/ko not_active IP Right Cessation
- 1991-09-11 DE DE4130205A patent/DE4130205A1/de not_active Ceased
Also Published As
Publication number | Publication date |
---|---|
DE4130205A1 (de) | 1992-03-19 |
US5229965A (en) | 1993-07-20 |
KR960006878B1 (ko) | 1996-05-23 |
JPH04121893A (ja) | 1992-04-22 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
E902 | Notification of reason for refusal | ||
G160 | Decision to publish patent application | ||
E701 | Decision to grant or registration of patent right | ||
GRNT | Written decision to grant | ||
LAPS | Lapse due to unpaid annual fee |