KR20200008655A - 어레이 기판, 칩 온 필름, 표시 장치 및 얼라인먼트 방법 - Google Patents

어레이 기판, 칩 온 필름, 표시 장치 및 얼라인먼트 방법 Download PDF

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Publication number
KR20200008655A
KR20200008655A KR1020207000274A KR20207000274A KR20200008655A KR 20200008655 A KR20200008655 A KR 20200008655A KR 1020207000274 A KR1020207000274 A KR 1020207000274A KR 20207000274 A KR20207000274 A KR 20207000274A KR 20200008655 A KR20200008655 A KR 20200008655A
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South Korea
Prior art keywords
alignment
pin
mark
chip
film
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Ceased
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KR1020207000274A
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English (en)
Korean (ko)
Inventor
런제 류
샹첸 왕
링옌 천
Original Assignee
쿤산 고-비젼녹스 옵토-일렉트로닉스 씨오., 엘티디.
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Application filed by 쿤산 고-비젼녹스 옵토-일렉트로닉스 씨오., 엘티디. filed Critical 쿤산 고-비젼녹스 옵토-일렉트로닉스 씨오., 엘티디.
Publication of KR20200008655A publication Critical patent/KR20200008655A/ko
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/68—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0266—Marks, test patterns or identification means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/5442—Marks applied to semiconductor devices or parts comprising non digital, non alphanumeric information, e.g. symbols
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
    • H01L2223/54486—Located on package parts, e.g. encapsulation, leads, package substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8112—Aligning
    • H01L2224/81121—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors
    • H01L2224/8113—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors using marks formed on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8112—Aligning
    • H01L2224/81121—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors
    • H01L2224/81132—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors using marks formed outside the semiconductor or solid-state body, i.e. "off-chip"
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8512—Aligning
    • H01L2224/85121—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors
    • H01L2224/8513—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors using marks formed on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H05K1/147—Structural association of two or more printed circuits at least one of the printed circuits being bent or folded, e.g. by using a flexible printed circuit
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09918—Optically detected marks used for aligning tool relative to the PCB, e.g. for mounting of components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10007—Types of components
    • H05K2201/10128—Display

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Electroluminescent Light Sources (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
KR1020207000274A 2018-04-02 2018-08-28 어레이 기판, 칩 온 필름, 표시 장치 및 얼라인먼트 방법 Ceased KR20200008655A (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
CN201810283325.3 2018-04-02
CN201810283325.3A CN108493183B (zh) 2018-04-02 2018-04-02 一种阵列基板、覆晶薄膜及其对位方法及显示装置
PCT/CN2018/102687 WO2019192137A1 (zh) 2018-04-02 2018-08-28 阵列基板、覆晶薄膜、显示装置及对位方法

Publications (1)

Publication Number Publication Date
KR20200008655A true KR20200008655A (ko) 2020-01-28

Family

ID=63318062

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020207000274A Ceased KR20200008655A (ko) 2018-04-02 2018-08-28 어레이 기판, 칩 온 필름, 표시 장치 및 얼라인먼트 방법

Country Status (6)

Country Link
EP (1) EP3640980A4 (enExample)
JP (1) JP7058319B2 (enExample)
KR (1) KR20200008655A (enExample)
CN (1) CN108493183B (enExample)
TW (1) TWI659513B (enExample)
WO (1) WO2019192137A1 (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20240057501A (ko) * 2022-10-24 2024-05-03 세메스 주식회사 반도체 기판 장치와, 반도체 처리 방법 및 반도체 처리 장치

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110097823B (zh) * 2019-04-09 2021-02-02 深圳市华星光电半导体显示技术有限公司 显示面板及显示模组
CN110930866B (zh) * 2019-11-26 2021-07-06 Tcl华星光电技术有限公司 覆晶薄膜及显示装置
CN111081151A (zh) * 2020-01-08 2020-04-28 深圳市华星光电半导体显示技术有限公司 显示面板
WO2022236780A1 (zh) * 2021-05-13 2022-11-17 京东方科技集团股份有限公司 电路板、覆晶膜、显示装置和绑定方法

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JPH11274670A (ja) * 1998-03-19 1999-10-08 Kyocera Corp 積層基板
JP4651886B2 (ja) * 2001-09-14 2011-03-16 東北パイオニア株式会社 電子機器及び電子機器の製造方法
JP4214357B2 (ja) * 2002-02-28 2009-01-28 セイコーエプソン株式会社 電子デバイスの製造方法
JP3544970B2 (ja) * 2002-09-30 2004-07-21 沖電気工業株式会社 Ｃｏｆテープキャリア、半導体素子、半導体装置
JP2006119321A (ja) * 2004-10-21 2006-05-11 Kofu Casio Co Ltd 電気回路間の導通接続構造
JP2006245514A (ja) * 2005-03-07 2006-09-14 Hitachi Media Electoronics Co Ltd フレキシブル基板同士の接続方法
CN100461984C (zh) * 2005-09-30 2009-02-11 友达光电股份有限公司 电路组装结构
TWI292936B (en) * 2006-03-24 2008-01-21 Chipmos Technologies Inc Inner lead bonding tape and tape carrier package utilizing the tape
TW200822303A (en) * 2006-11-07 2008-05-16 Chipmos Technologies Inc Substrate for chip on film packages
CN100545890C (zh) * 2007-03-22 2009-09-30 中华映管股份有限公司 显示面板、显示面板的引脚接合及检测方法
TWI343090B (en) * 2007-05-18 2011-06-01 Au Optronics Corp System and method for alignment
CN101060112B (zh) * 2007-06-11 2010-10-06 友达光电股份有限公司 基板对位系统及其对位方法
JP2012013719A (ja) * 2010-06-29 2012-01-19 Funai Electric Co Ltd Ｃｏｆアライメントマーク
US8994898B2 (en) * 2012-10-18 2015-03-31 Shenzhen China Star Optoelectronics Technology Co., Ltd COF base tape and manufacturing method thereof and liquid crystal display module comprising same
CN203365865U (zh) * 2013-07-04 2013-12-25 京东方科技集团股份有限公司 一种阵列基板、覆晶薄膜和显示装置
CN105551378A (zh) * 2016-02-04 2016-05-04 京东方科技集团股份有限公司 一种覆晶薄膜、柔性显示面板及显示装置
CN106783664B (zh) * 2017-01-03 2020-04-21 京东方科技集团股份有限公司 一种显示模组、绑定检测方法及绑定系统

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20240057501A (ko) * 2022-10-24 2024-05-03 세메스 주식회사 반도체 기판 장치와, 반도체 처리 방법 및 반도체 처리 장치

Also Published As

Publication number Publication date
TWI659513B (zh) 2019-05-11
JP7058319B2 (ja) 2022-04-21
CN108493183B (zh) 2020-05-08
CN108493183A (zh) 2018-09-04
TW201943044A (zh) 2019-11-01
JP2020526934A (ja) 2020-08-31
EP3640980A1 (en) 2020-04-22
EP3640980A4 (en) 2020-10-28
WO2019192137A1 (zh) 2019-10-10

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