KR20150130516A - 비아와 커패시터의 플레이트 사이에 유전체를 갖는 커패시터 - Google Patents

비아와 커패시터의 플레이트 사이에 유전체를 갖는 커패시터 Download PDF

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Publication number
KR20150130516A
KR20150130516A KR1020157029145A KR20157029145A KR20150130516A KR 20150130516 A KR20150130516 A KR 20150130516A KR 1020157029145 A KR1020157029145 A KR 1020157029145A KR 20157029145 A KR20157029145 A KR 20157029145A KR 20150130516 A KR20150130516 A KR 20150130516A
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South Korea
Prior art keywords
capacitor
substrate
plate
dielectric
vias
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Abandoned
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KR1020157029145A
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English (en)
Korean (ko)
Inventor
제-흐시웅 란
청지에 주오
창한 윤
데이비드 에프. 버디
데릭 디. 김
로버트 피. 미쿨라
마리오 프란시스코 벨레즈
종해 김
Original Assignee
퀄컴 인코포레이티드
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Publication of KR20150130516A publication Critical patent/KR20150130516A/ko
Abandoned legal-status Critical Current

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    • H01L28/40
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00Resistors, capacitors or inductors
    • H10D1/60Capacitors
    • H10D1/68Capacitors having no potential barriers
    • G06F17/5068
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00Computer-aided design [CAD]
    • G06F30/30Circuit design
    • G06F30/39Circuit design at the physical level
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481Internal lead connections, e.g. via connections, feedthrough structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822Multilayer substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H01L27/016
    • H01L27/12
    • H01L28/10
    • H01L28/60
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00Resistors, capacitors or inductors
    • H10D1/20Inductors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00Resistors, capacitors or inductors
    • H10D1/60Capacitors
    • H10D1/68Capacitors having no potential barriers
    • H10D1/692Electrodes
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/80Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple passive components, e.g. resistors, capacitors or inductors
    • H10D86/85Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple passive components, e.g. resistors, capacitors or inductors characterised by only passive components
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/12Mountings, e.g. non-detachable insulating substrates
    • H01L23/14Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/15Ceramic or glass substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Theoretical Computer Science (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)
  • Ceramic Capacitors (AREA)
  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Semiconductor Memories (AREA)
KR1020157029145A 2013-03-15 2014-03-12 비아와 커패시터의 플레이트 사이에 유전체를 갖는 커패시터 Abandoned KR20150130516A (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/833,632 2013-03-15
US13/833,632 US9935166B2 (en) 2013-03-15 2013-03-15 Capacitor with a dielectric between a via and a plate of the capacitor
PCT/US2014/024118 WO2014150747A1 (en) 2013-03-15 2014-03-12 Capacitor with a dielectric between a via and a plate of the capacitor

Publications (1)

Publication Number Publication Date
KR20150130516A true KR20150130516A (ko) 2015-11-23

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020157029145A Abandoned KR20150130516A (ko) 2013-03-15 2014-03-12 비아와 커패시터의 플레이트 사이에 유전체를 갖는 커패시터

Country Status (6)

Country Link
US (1) US9935166B2 (enExample)
EP (1) EP2973693B1 (enExample)
JP (1) JP2016518702A (enExample)
KR (1) KR20150130516A (enExample)
CN (1) CN105009280B (enExample)
WO (1) WO2014150747A1 (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10943908B2 (en) 2018-09-21 2021-03-09 Samsung Electronics Co., Ltd. Method of forming semiconductor device

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US9954267B2 (en) 2015-12-28 2018-04-24 Qualcomm Incorporated Multiplexer design using a 2D passive on glass filter integrated with a 3D through glass via filter
US10373868B2 (en) * 2016-01-18 2019-08-06 Infineon Technologies Austria Ag Method of processing a porous conductive structure in connection to an electronic component on a substrate
JP6857329B2 (ja) * 2016-10-24 2021-04-14 大日本印刷株式会社 高周波部品及びその製造方法
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WO2019059898A1 (en) * 2017-09-20 2019-03-28 Intel Corporation PERIPHERAL INDUCERS
JP2019102733A (ja) * 2017-12-06 2019-06-24 凸版印刷株式会社 配線基板、半導体装置、及び配線基板の製造方法
TWI669997B (zh) * 2018-01-25 2019-08-21 欣興電子股份有限公司 線路板結構及其製作方法
IT202000017554A1 (it) * 2020-07-20 2022-01-20 Thales Alenia Space Italia Spa Con Unico Socio Feedthrough capacitivo per moduli ermetici ibridi
WO2022222131A1 (zh) * 2021-04-23 2022-10-27 京东方科技集团股份有限公司 集成有无源器件的基板及其制备方法
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10943908B2 (en) 2018-09-21 2021-03-09 Samsung Electronics Co., Ltd. Method of forming semiconductor device

Also Published As

Publication number Publication date
EP2973693B1 (en) 2020-08-26
CN105009280A (zh) 2015-10-28
US9935166B2 (en) 2018-04-03
JP2016518702A (ja) 2016-06-23
CN105009280B (zh) 2017-12-15
WO2014150747A1 (en) 2014-09-25
US20140268616A1 (en) 2014-09-18
EP2973693A1 (en) 2016-01-20

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