WO2009118694A1 - Integrated 3d high density and high quality inductive element - Google Patents

Integrated 3d high density and high quality inductive element Download PDF

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Publication number
WO2009118694A1
WO2009118694A1 PCT/IB2009/051240 IB2009051240W WO2009118694A1 WO 2009118694 A1 WO2009118694 A1 WO 2009118694A1 IB 2009051240 W IB2009051240 W IB 2009051240W WO 2009118694 A1 WO2009118694 A1 WO 2009118694A1
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Prior art keywords
vias
substrate
solenoid
metal layers
silicon
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PCT/IB2009/051240
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French (fr)
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Stephane Bouvier
Emmanuel Savin
Lionel Guiraud
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Nxp B.V.
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Publication of WO2009118694A1 publication Critical patent/WO2009118694A1/en

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    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F17/00—Fixed inductances of the signal type 
    • H01F17/0006—Printed inductances
    • H01F17/0033—Printed inductances with the coil helically wound around a magnetic core
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
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    • H01L2223/6661—High-frequency adaptations for passive devices
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
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    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
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    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
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    • H01L2924/151—Die mounting substrate
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    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/157—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof

Abstract

The present invention describes a high density and quality inductive element, integrated in semiconductor substrate (in particular Si) by realizing a solenoid. A System In Package needs to integrate different passive components and dies to realize it. Inductive components are one type of the passives (see e.g. Fig. 1a,b). Inductive components on silicon substrate are known in the art. They are usually implemented in a planar spiral way so that they use available interconnection metal layers. These types of inductors are usable as long as they do not reach high value inductance (see e.g. Fig. 1c). When higher value and or quality factor is needed, SMD components or specific added process steps above existing substrate are necessary. These solutions increase overall cost, logistic and design complexity of System In Package (see e.g. Fig. 2).

Description

Integrated 3D high density and high quality inductive element
FIELD OF THE INVENTION
The present invention describes a high density and quality inductive element, integrated in semiconductor substrate (in particular Si) by realizing a solenoid.
BACKGROUND OF THE INVENTION
A requirement of a System In Package (SiP) is that it need to integrate various passive components and dies to realize it. Inductive components are one type of passives (see e.g. Fig. la,b).
Inductive components on silicon substrate are known in the art. They are usually implemented in a planar spiral way so that they use available interconnection metal layers. These types of inductors are usable as long as they do not reach high value inductance (see e.g. Fig. Ic).
When a higher value and or quality factor is needed, SMD components or specific added process steps above an existing substrate are necessary. These solutions increase overall cost, logistic and design complexity of System in Package (see e.g. Fig. 2). The need of more integration in SiP 's and cost pressure has induced the development of new silicon substrate with fine pitch through silicon vias.
Various system in packages or integrated inductors have been disclosed.
EP 1 280 203 A2 discloses a semiconductor package which enables various interconnections between pins at a low cost. In an embodiment of the disclosure, the semiconductor package has a base substrate and a group of ICs (spacer ICs, routing ICs, and flip chip ICs) stacked on the base substrate in three dimensions. The routing IC is an interposer for wiring between the pins of the chips located above and below the routing IC and enables the integration of passive elements.
This disclosure does, however, not relate to a SIP comprising a solenoid. US6,858,892 B2 discloses a SiP (System-in-Package) having large- capacity passive elements incorporated therein or mounted thereon. On an interposer made of a silicon substrate, metal substrate or glass substrate having via-holes formed therein, IC chips, or a plurality of chips, which are passive elements formed on a silicon substrate, metal substrate or glass substrate, are mounted in a face-up manner and re-wired en bloc on the chip. Because all of the silicon substrate, metal substrate and glass substrate are durable against high-temperature annealing for crystallizing a high-dielectric-constant material, a large-capacity passive elements can be formed on the substrate which serves as an interposer or on the re-wiring of the chips to be mounted. It is also allowable that large-capacity passive elements formed on the silicon substrate, metal substrate or glass substrate is divided into chips, and that the resultant chips are mounted together with the IC chips.
This disclosure does, however, not relate to a SIP comprising a solenoid, nor to through wafer vias.
US6,927,666 B2 discloses an inductor which is fabricated on a substrate having a top surface and a bottom surface. The inductor includes a plurality of holes extending through the substrate, wherein the plurality of holes interconnect the top surface and the bottom surface of the substrate. The inductor also includes a plurality of conductive posts formed in the plurality of holes and a plurality of conductive segments formed on the top surface and on the bottom surface that interconnect the conductive posts such that a continuous conductive coil is formed. The inductor also includes a magnetic core that occupies substantially the entire volume enclosed by the conductive coil.
US6,976,300 B2 discloses an inductor comprising a plurality of interconnected conductive segments interwoven with a substrate. The inductance of the inductor is increased through the use of coatings and films of ferromagnetic materials such as magnetic metals, alloys, and oxides. The inductor is compatible with integrated circuit manufacturing techniques and eliminates the need in many systems and circuits for large off chip inductors. A sense and measurement coil, which is fabricated on the same substrate as the inductor, provides the capability to measure the magnetic field or flux produced by the inductor. This on chip measurement capability supplies information that permits circuit engineers to design and fabricate on chip inductors to very tight tolerances. A further example of prior art silicon substrate use is given in Fig. 3a-c.
Problems with the system in packages of the state of the art are that these are still not fully integrated, e.g. still many components remain present as separate items, thereby increasing costs, complexity, and involving extra process steps. Further disadvantages of the prior art are that inductance per unit substrate area is relatively low. Further these are difficult to integrate in existing silicon technology, and as a consequence involving typically additional process steps. Also good quality factors can not be realized at low frequencies, due to the specific layout of the inductors. Furthermore, via pitch and metal lines are not lithographically defined, giving bad control over winding dimensions. Also magnetic cores can not be integrated using magnetic material layers.
A next disadvantage of the SiP of the prior art is that relatively large elements, such as solenoids, are typically not integrated in the System in Package, thereby increasing costs, degrading quality of various components in a combined System in package, and leading to sub-optimal configurations.
Thus, there still is a need for improvement relating to e.g. the items mentioned above, in the field of System in Package, integrating high-quality, low- cost, inductor elements in existing silicon technology platforms.
SUMMARY OF THE INVENTION
The invention relates to a solenoid which is realized by using metal layers made available on both sides of the silicon wafer and fine pitch through silicon vias, various uses thereof, and a method of making the same. Further, this configuration allows building a high performance solenoid by optimal use of mutual inductance effects. Furthermore, the nature of this component enables an effective embedding in a System In Package. DETAILED DESCRIPTION OF THE INVENTION
In a first aspect the invention relates to a system in package comprising at least one solenoid, wherein the at least one solenoid comprises a substrate, such as a silicon wafer, metal layers forming electrically conductive tracks on both sides of said substrate, and fine pitch through silicon vias, wherein the tracks are electrically connected to one or more vias.
A solenoid according to the invention is realized by using metal layers made available on both sides of the silicon wafer and fine pitch through silicon vias. Metal layers are of formed of an electrically conducting material, which material need not be the same on both sides. Furthermore, also the vias are typically formed of an electrically conducting material, such as W, Al, Cu, or suitable combinations thereof. Further, this configuration allows building of a high performance solenoid by optimal use of mutual inductance effects. The nature of this component enables an effective embedding in a System In Package.
The solenoid, having windings composed of conductive lines on two opposite sides of the substrate, and conductive holes, having a small diameter and a high aspect ratio, running through the substrate connecting the conductive lines on opposite sides. Part of the windings effectively runs perpendicular to the substrate surfaces comprising the conductive lines.
For example, if the substrate is a silicon semiconductor wafer, the conductive lines are made of metal layers being present on both sides of the silicon wafer, and the holes are vias having small diameter of about 30 μm, and having a high aspect ratio of 20 and larger. Larger vias may also be formed, such as vias having a diameter of up to 100 μm, such as 75 μm.
A new generation with fine pitch vias system in package is given in Fig. 4. Examples of target specifications of a process are: pitch vias = 35 μm, vias diameter = 20μm, metal thickness (copper) = 8μm, substrate thickness = 300 μm. The pitch between vias is defined as the shortest distance between two neighbouring vias. A further example of a present 3D solenoid inductor is given in Fig. 5.
Fig. 6 shows a comparison to a component alone and a SMD type. The possibility to realize a very dense via matrix allows to reach a high density of inductance by square millimeter, as is shown in Fig. 7. The use of a good conducting metal (such as copper) reduces the electrical series resistance (ESR) and as a consequence increases the quality factor. An optimized structure can increase the performance of an inductor by the mutual inductance effect between adjacent vias and tracks. Advantages of the present invention are that the construction of the windings allows the manufacture of a high-performance solenoid, at the same time requiring a small substrate area, i.e. the inductance per unit substrate area is relatively high.
A further advantage is the simple integration in present and near future silicon technology. For example, no additional process steps, compared to prior art technology, are required.
A next advantage is that good quality factors, such as larger than 60, can be realized at low frequencies, e.g. at 650 MHZ.
A yet further advantage is that via pitch and metal lines are lithographically defined, giving precise control over winding dimensions.
Furthermore, multiple solenoids can be configured such as to optimally use mutual inductance of each solenoid. Thus, even substantially circular solenoids can be made.
As indicated above a combination according to the invention of one or more solenoids is formed with a SIP, which combination takes special advantage of the mutual inductance.
A next advantage is that one or more magnetic cores can be easily integrated in a solenoid according to the invention, using magnetic material layers.
Without adding extra metal layers, the present invention provides a benefit of side magnetic coupling factor, by making an extra side inductor.
It is noted that this component comes for free in a process and further is fully compatible with the other passive components, which already may be existing, like trench capacitors and poly-silicon resistors.
Also this component is compatible with nowadays packaging techniques.
In a preferred embodiment the invention relates to a system in package, wherein the vias have a pitch of 20-50 μm, preferably 30-40 μm, most preferably 33- 37 μm, such as 35 μm, and/or wherein the vias have diameter of 10-50 μm, preferably 15-40 μm, most preferably 18-30 μm, such as 20μm, and/or wherein the vias have an aspect ratio of 5 and larger, preferably of 10 and larger, more preferably of 20 and larger, such as larger than 30, and/or wherein metal layers have a thickness of 2-20 μm, preferably 4-15 μm, most preferably 6-10 μm, such as 8 μm, and/or wherein the metal layers are preferably formed of copper, and/or wherein the substrate has a thickness of 150-500 μm, preferably 200-400 μm, most preferably 250-350 μm, such as 300 μm.
A small pitch allows for a high inductance per unit surface area. A too small pitch leads to undesired interactions, whereas a too large pitch is not costs effective in terms of surface area used.
Preferably the metal layers are formed of an electrically conducting element, having a low resistivity, such as copper. The lower the resistivity, the better. The resistivity may further be improved by increasing the metal layer thickness to some extent. The metal used typically needs to be compatible with the technology used to form the solenoid.
In a yet further preferred embodiment the invention relates to a system in package further comprising various other components. Preferably the system in package allows integration of these components to a high degree, i.e. many and various other components are integrated in the same package. Preferably at least one integrated 3D high density and high quality inductive element, and preferably at least one component such as a discrete passive component, such as an inductor, a transformer, and an antenna, is present in the SiP according to the invention. These inductive elements have various uses, such as transforming, antenna to the outside world to pick up signals, an oscillator, and an inductor in a circuit, respectively. Further preferably at least one IC, preferably more than one IC, is present. The number of ICs is somewhat limited, due to limited space available, and due to heat dissipation. In principal as many ICs as possible may be present. Further preferably a leadframe is present. Such as leadframe allows for electrical connections. Preferably a combination of one or more of the above elements is present. Integration of various elements contributes to a reduction in costs, lower power consumption, increased reliability, and improved performance. In a yet further preferred embodiment the invention relates to a system in package further comprising a printed circuit board. As such, a further integration of components is achieved, with the above mentioned advantages.
In a yet further preferred embodiment the invention relates to a system in package, which system is embedded in a housing, preferably formed from epoxy.
The solenoid according to the invention may further comprise a magnetic core. Thereby the magnetic properties of said solenoid may further be tuned to specific requirements.
In a further embodiment the present solenoid profits from an enlargement of the horizontal tracks, in order to minimize the serial electrical resistance. However, by doing this, the solenoid will tend to decrease the intrinsic self-inductance value developed by the tracks. In fact the self-inductance value per unit length value of a metal trace is decreasing when track thickness and track width are increasing. So, as the quality factor in a low frequency domain can be expressed as follows:
L ω
Q =
R
A smaller value of L will lead to a smaller value of Q. But on the other side there is a way to increase the mutual coupling between tracks so to increase the device self-inductance value only by enlarging the tracks. According to the following formula the self- inductance is equal to: n n
L = Σ Σ Mij i=l j=l
So the mutual inductance value will participate to the total self- inductance value and a gain is also expected on the quality factor. Then, of course, a good balance must be found by the gain realized by this operation and the loss induced by the enlargement of the tracks. So, the inductance density in that case is not limited by vias, as is the case in the prior art, but only follows the minimum spacing DRC rule between metal tracks. From a practical point of view, however, we will avoid to use the minimum DRC rules which in that case is in the same order of magnitude for the Self-Resonant Frequency (SRF). Fig. 12 gives an overview on the way the tracks (141 top track; 111 bottom track; 140 via; 110 via) are enlarged. Also indicated are the width and length of the solenoid. In that case, mutual coupling between tracks is maximized in order to at least keep the density integration constant, which methodology applied is described below, and the serial electrical resistance value is decreased leading to higher quality factor at low frequency, such as 1 GHz.
From a physical point of view the self- inductance per unit length value is decreasing with track width and thickness while it is increasing with conductor length. On the other side coupling between tracks is increasing with the inverse of track spacing. The trade-off here consists in finding the right balance between track self-inductance and mutual track coupling.
Fig. 13 shows the evolution of the inductance contribution as a function of the track width (top curves); the evolution of the total self-inductance value as a function of the track width is an enlarged fragment of the top curve (bottom curve). So preferably the track width is smaller than 30 μm, or larger than 65 μm.
Then the electrical serial resistance is calculated and an estimation of the quality factor is carried-out and this confirms the previous choice in the solenoid parameters (i.e. track width).
Fig. 13 b shows the evolution of the inductance contribution as a function of the normalized track width (top curves); the evolution of the total self- inductance value as a function of the normalized track width is an enlarged fragment of the top curve (bottom curve). The normalized track width W/Wi is normalized with respect to a classical width, in this case having a width of 30 μm. The thickness of the tracks is 8 μm. Typically the tracks are formed of copper. The relative thickness of the tracks becomes only important if it becomes approximately as large as the width. It can be seen that if the width is taken to be larger than approximately 2.2 times that of the classical case, the inductance is optimized.
Fig. 14 shows the evolution of electrical serial resistance of the normalized track width (top curves); and evolution of the estimated Q-factor as a function of the normalized track width (bottom curves). The positive effect on relative resistance R/Ro and relative quality factor Q/Qo can be seen from these graphs, wherein Ro and Qo are the resistance and quality factor of the reference or classical solenoid, respectively. EM simulations with the help of a 3D simulator have been carried out in order to quantify the advantages added by this design improvement. Results are presented on the following Figs.:
Fig. 15 Shows simulation results showing the variations against frequency of the self inductance value (top curves) and the quality factor (bottom curves). Clearly the present invention shows an improved self inductance as well as an improved quality factor.
We can clearly see the big impact of the proposed invention on the quality factor. Its value is increased by 60% (see Fig. 15) over a broad frequency range (from 1 * 106- 1 * 109 Hz), whereas at the same time the self inductance is in the same order of magnitude (5% more), but anyhow improved as well.
Advantages of the present embodiment are that by a single method to enlarge the horizontal tracks of a 3D solenoid in an Si IC process leads to a improvement by 50-60% of the quality factor. Further, this improvement does not have any negative impact on other intrinsic electrical parameters of the device itself, such as SRF (Self Resonant Frequency) and Self-Inductance value.
It is noted that the present embodiment does not impact the layout of the floor plan (i.e. the footprint of the improved solenoid is not larger a comparable one with classical tracks).
Even further, the design of the present solenoid is not more limited by design rules related to through wafer interconnects (or vias) that are not so much aggressive.
More over, a twisted 3D architecture is described leading to a decrease of EMC related issues together combined with a higher density integration.
Thus, the present invention teaches a way to achieve a high value of quality factor only by modifying the design of the horizontal tracks (on top and back side top metals of the process). The self inductance-value is not impacted as the mutual coupling between tracks is maximized. It leads to a drastically reduction of electrical serial resistance value. The present solenoid can be easily used within SiP products in order to realize a low cost and embedded matching network. In a second aspect the invention relates to a device comprising a system in package according to the invention, such as a DC/DC converter, a TV front- end filter, an FM radio PLL filter, or a magnetic sensor.
In a third aspect the invention relates to a solenoid comprising a silicon wafer, forming a substrate, metal layers on both sides of said wafer, and fine pitch through silicon vias, wherein the metal layers are electrically connected to one or more vias.
The solenoid according to the invention is described above. Typically the solenoid forms part of a System in Package. In a fourth aspect the invention relates to a method of manufacturing a solenoid, comprising the steps of: providing a substrate, preferably made of silicon, lithographically defining through substrate vias, etching the vias, using a process such as Deep Reactive Ion Etching (DRIE), filling the vias with a conducting material, preferably with copper, using a process such as electroplating, applying metal layers on both sides of the substrate, preferably copper layers, using a process such as electroplating, - lithographically defining metal lines, and etching the metal layers, using a process such as standard dry or wet etching.
The vias are typically etch to a depth almost equal to the thickness of the substrate, such as from 250-450 um, such as 350 um. If a remainder of the substrate remains present, a grinding step may be used to remove the remainder, e.g. grinding to a thickness of e.g. approximately 320 μm.
Optionally the vias and/or substrate may be covered with an oxide and a subsequent nitride layer.
Further, a protective Ti layer may be deposited, on the front side and/or on the back side.
Thereafter a metal layer is deposited, typically a copper layer. Thereto, one of the sides, e.g. the back side, is protected with a foil. Copper is subsequently deposited on the front side, e.g. by electroplating. Subsequently a lithographic step is used to define metal lines. The metal is than etched, towards a seed layer, which seed layer typically is formed by the oxide/nitride layer.
Thereafter a metal layer is deposited on the other side, typically a copper layer. Thereto, one of the sides, e.g. the front side, is protected with a foil. Copper is subsequently deposited on the back side, e.g. by electroplating.
Subsequently a lithographic step is used to define metal lines. The metal is than etched, towards a seed layer, which seed layer typically is formed by the oxide/nitride layer. The application of electrically conductive material in the first trenches and the second trenches does not mean that this is the same material, neither that there is a common step in the application of this conductive material for both first and second trenches. It appears advantageous that the conductive material provided in the first trenches forms a seed layer in the second trenches, that is thereafter thickened in an electroplating process.
Subsequently a protective layer is deposited on the back side, such as a polymer, such as polyimide. The polyimide is then etched, after a lithographic step.
Thereafter the foil is removed. The back side polyimide is than baked.
The back side is then covered with a foil. Subsequently a protective layer is deposited on the front side, such as a polymer, such as polyimide. The polyimide is then etched, after a lithographic step.
Thereafter the foil is removed. The front side polyimide is than baked.
Of course, several of the above steps may be combined, e.g. in stead of using two foils on the front side, one foil may be used, thereafter performing the required steps.
Subsequently a conductor is formed at the outer side of the substrate, being connected to the metal layer. Such a conductor is for instance a Ni/Au conductor. It is deposited at both sides.
Thereafter balls and bumps are formed. The bumps are approximately 200 μm in diameter. The bumps are used to separate the substrate from ICs, that form part of a SiP. The balls are used to electrically connect various components to one and another and the outside world. Typically the balls are formed from a material such as SAC. The through wafer vias are used to connect various components on either side of the substrate. A total SiP may further be provided with one or more protective layers and/or a package.
BRIEF DESCRIPTION OF THE DRAWINGS
Figs. Ia, b and c. Photographs of a silicon based System in Packages comprising different passive components.
Fig. 2. Schematic drawing of a discrete solenoid. Figs. 3a,b. Photograph of a silicon based System in Packages and a schematic drawing thereof, respectively.
Fig. 3c. Schematic drawing of a silicon based System in Packages. Fig. 4. Schematic drawing of a silicon based System in Packages comprising through silicon vias to connect several active dies together (two in the
Fig-)- Fig. 5. Perspective view of a System in Packages comprising a solenoid according to the invention.
Fig. 6. Schematic drawing of a silicon based solenoid compare to a discrete one (SMD).
Fig. 7. Schematic drawing of a silicon based System in Packages comprising a solenoid according to the invention.
Figs. 8a,b,c. Schematic drawing of a silicon based solenoid that takes advantage of the positive side magnetic coupling.
Fig. 9. EM simulation of a System in Packages comprising a solenoid according to the invention. Fig. 10. EM simulation results of a silicon based solenoid . The Quality
Factor reaches 63 at 650 Mhz for a 100 nH inductor (lmm2 area).
Figs. 1 la,b. Schematic drawing of a silicon based solenoid that takes advantage of the positive side magnetic coupling of 3 inductors segment.
Fig. 12 shows an solenoid with relatively wide tracks. Fig. 13 shows the evolution of the inductance contribution as a function of the track width (top curves); the evolution of the total self-inductance value as a function of the track width is an enlarged fragment of the top curve (bottom curve). Fig. 13 b shows the evolution of the inductance contribution as a function of the normalized track width (top curves); the evolution of the total self- inductance value as a function of the normalized track width is an enlarged fragment of the top curve (bottom curve). Fig. 14 shows the evolution of electrical serial resistance of the normalized track width (top curves); and evolution of the estimated Q-factor as a function of the normalized track width (bottom curves).
Fig. 15 Shows simulation results showing the variations against frequency of the self inductance value (top curves) and the quality factor (bottom curves).
DETAILED DESCRIPTION OF THE DRAWINGS
Figs. Ia, b and c show photographs of a silicon based System in Packages comprising different passive components, such as antennas, inductors, a chip, a power supply. These system in packages further comprise one or more solenoids, which solenoids are not integrated with other components, such as other passive components. Clearly these separate components, such as the solenoids, occupy a substantive part of the surface area available. Integration of components is therefore one of the key issues to e.g. reduce costs of system in packages.
Fig. 2. Schematic drawing of a discrete solenoid. Therein wires are shown, wounded around a core. The wires are attached to two outer electrodes, for contact with the outside world. Further, the solenoid may comprise a specific material as a core, such as alumina, Typically the core is non conductive. For further isolation and protection, e.g. against influence from the outside world, the solenoid is covered with a coating, such as a resin, e.g. an epoxy resin.
Figs. 3a,b. Photograph of silicon based System in Packages and a schematic drawing thereof, respectively. The drawing is up-side down with respect to the photograph. Visible are solder bumps on the outside, and an active die or an IC, indicated with an arrow, and a substrate, such as silicon. The active die is attached to the silicon by balls, such as SAC (SnAgCu solder), which are not visible in the photograph, but indicated in the drawing. Further a printed circuit board is shown on the bottom part of Fig. 3b. Fig. 3c. Schematic drawing of a silicon based System in Package. Herein elements of Figs. 3a and b are visible. Furthermore, inductors are shown on the front corner.
Fig. 4. Schematic drawing of a silicon based System in Packages comprising through silicon vias to connect several active dies together (two in the Figure). Furthermore, through vias are indicated at the edges of the substrate. Otherwise, Fig. 4 resembles Fig. 3b.
Fig. 5. Perspective view of a System in Packages comprising a solenoid according to the invention. The solenoid comprises through substrate vias, metal lines on either side of the substrate, which metal lines are in electrical connection to the vias. The solenoid has a circular like spiralized form. As such, the spiral runs through and over the substrate.
Fig. 6. Schematic drawing of a silicon based solenoid compared to a discrete one (SMD). It is clearly visivle that a prior art discrete SMD occupies much more extra space than the integrated solenoid according to the invention. Of the solenoid, only through wafer vias are indicated.
Fig. 7. Schematic drawing of a silicon based System in Packages comprising a solenoid according to the invention. Apart from the solenoid, two ICs are drawn, wherein each IC is further electrically connected by through wafer vias. The same or similar through wafer vias are in this case used for forming the solenoid.
Fig. 8a,b, c. Schematic drawing of a silicon based solenoid that takes advantage of the positive side magnetic coupling. Two solenoids according to the invention are indicated. Preferably the solenoids according to the invention have an electrical current that runs in an opposite direction, thereby generating a magnetic field in an opposite direction. As such, the magnetic fields formed cancel each other to a large extent. The two (or more) solenoids may be mutually electrically connected, depending on specific requirements of the specific System in Package.
Visible in Fig. 8 (and in Figs. 9 and 11 for that matter) is also a simple ground ring, which may necessary for the RF characterization of the component. As such, the ground ring may form part of a solenoid according to the invention.
Fig. 9. EM simulation of a System in Packages comprising a solenoid according to the invention. This System in Package comprises two solenoids, of which the mutual magnetic fields large cancel each other. Outside the direct area of the solenoids virtually no magnetic field is present. Therefore, interactions with other components, such as passives, such as inductors, are largely ruled out. This offers a significant advantage, for instance in terms of number of components which may be packed in one system. Fig. 10. EM simulation results of a silicon based solenoid . The Quality
Factor reaches 63 at 650Mhz for a 10OnH inductor (lmm2 area). Such a Quality Factor is very satisfying, and can not be reached with prior art solenoids. Furthermore, the solenoid according to the invention may easily be tuned, by adjusting the layout thereof, to provide high Quality Factors at other frequencies, as desired. Fig. 1 la,b. Schematic drawing of a silicon based solenoid that takes advantage of the positive side magnetic coupling of 3 inductors segment. It is envisaged that more solenoids according to the invention may be present. Fig. 12 shows an solenoid with relatively wide tracks. Fig. 13 shows the evolution of the inductance contribution as a function of the track width (top curves); the evolution of the total self-inductance value as a function of the track width is an enlarged fragment of the top curve (bottom curve).
Fig. 13 b shows the evolution of the inductance contribution as a function of the normalized track width (top curves); the evolution of the total self- inductance value as a function of the normalized track width is an enlarged fragment of the top curve (bottom curve).
Fig. 14 shows the evolution of electrical serial resistance of the track width (top curves); and evolution of the estimated Q-factor as a function of the track width (bottom curves). Fig. 15 Shows simulation results showing the variations against frequency of the self inductance value (top curves) and the quality factor (bottom curves).

Claims

Integrated 3D high density and high quality inductive element CLAIMS:
1. System in package comprising at least one solenoid, wherein the at least one solenoid comprises a substrate, such as a silicon wafer, metal layers forming electrically conductive tracks on both sides of said substrate, and fine pitch through silicon vias, wherein the tracks are electrically connected to one or more vias.
2. System in package according to claim 1, wherein the vias have a pitch of 20-50 μm, preferably 30-40 μm, most preferably 33-37 μm, such as 35 μm, and/or wherein the vias have diameter of 10-50 μm, preferably 15-40 μm, most preferably 18-30 μm, such as 20μm, and/or wherein the vias have an aspect ratio of 5 and larger, preferably of 10 and larger, more preferably of 20 and larger, such as larger than 30, and/or wherein metal layers have a thickness of 2-20 μm, preferably 4-15 μm, most preferably 6-10 μm, such as 8 μm, and/or wherein the metal layers are preferably formed of copper, and/or wherein the substrate has a thickness of 150-500 μm, preferably 200-400 μm, most preferably 250-350 μm, such as 300 μm.
3. System in package according to claim 1 or 2, further comprising at least one integrated 3D high density and high quality inductive element, preferably at least one component such as a discrete passive component, such as an inductor, a transformer, and an antenna, preferably at least one IC, preferably more than one IC, and preferably a leadframe.
4. System in package according to any of claims 1-3, further comprising a printed circuit board.
5. System in package according to any of claims 1-4, which system is embedded in a housing, preferably formed from epoxy.
6. Device comprising a system in package according to any of claims 1-5, such as a DC/DC converter, a TV front-end filter, an FM radio PLL filter, or a magnetic sensor.
7. Solenoid comprising a silicon wafer forming a substrate, metal layers on both sides of said wafer, and fine pitch through silicon vias, wherein the metal layers are electrically connected to one or more vias.
8. Method of manufacturing a solenoid, comprising the steps of: - providing a substrate, preferably made of silicon, lithographically defining through substrate vias, etching the vias, filling the vias with a conducting material, preferably with copper, applying metal layers on both sides of the substrate, preferably copper layers, lithographically defining metal lines, and etching the metal layers.
PCT/IB2009/051240 2008-03-25 2009-03-25 Integrated 3d high density and high quality inductive element WO2009118694A1 (en)

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