KR20140112347A - 소스/드레인에 하부 ＳｉＧｅ 층을 갖는 FinFET - Google Patents

소스/드레인에 하부 ＳｉＧｅ 층을 갖는 FinFET Download PDF

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KR20140112347A
KR20140112347A KR1020130058486A KR20130058486A KR20140112347A KR 20140112347 A KR20140112347 A KR 20140112347A KR 1020130058486 A KR1020130058486 A KR 1020130058486A KR 20130058486 A KR20130058486 A KR 20130058486A KR 20140112347 A KR20140112347 A KR 20140112347A
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finfet
fin structure
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밍-화 유
페이-렌 젱
체-리앙 리
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타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드
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Abstract

FinFET은 기판, 기판 상의 핀 구조, 핀 구조 내의 소스, 핀 구조 내의 드레인, 소스와 드레인 사이의 핀 구조 내의 채널, 채널 위의 게이트 유전체 층 및 게이트 유전체 층 위의 게이트를 포함한다. 소스와 드레인 중 적어도 하나는 하부 SiGe 층을 포함한다.

Description

소스/드레인에 하부 ＳｉＧｅ 층을 갖는 FinFET{FINFET WITH BOTTOM SIGE LAYER IN SOURCE/DRAIN}
본 개시는 일반적으로 반도체 디바이스에 관한 것으로, 보다 상세하게는 FinFET에 관한 것이다.
일부 FinFET 디바이스에서, 디바이스의 크기가 감소됨에 따라, 약한 구동 전류 및 단채널 효과가 난제가 되고 있다. 개선된 구동 전류 및 감소된 단채널 효과를 갖는 FinFET가 바람직하다.
FinFET은 기판, 기판 상의 핀 구조, 핀 구조 내의 소스, 핀 구조 내의 드레인, 소스와 드레인 사이의 핀 구조 내의 채널, 채널 위의 게이트 유전체 층 및 게이트 유전체 층 위의 게이트를 포함한다. 소스와 드레인 중 적어도 하나는 하부 SiGe 층을 포함한다.
이제 첨부 도면과 함께 취한 다음의 설명을 참조한다.
도 1은 일부 실시예에 따른 예시적인 FinFET의 개략도이다.
도 2는 일부 실시예에 따른 도 1의 예시적인 FinFET에 대해 채널 변형 대 Fin 상부로부터의 거리의 그래프이다.
도 3a는 일부 실시예에 따른 도 1의 예시적인 FinFET의 구동 전류 대 게이트 길이의 그래프이다.
도 3b는 일부 실시예에 따른 도 1의 예시적인 FinFET의 총 저항 대 게이트 길이의 그래프이다.
도 4는 일부 실시예에 따른 다른 예시적인 FinFET의 개략도이다.
도 5는 일부 실시예에 따른 또 다른 예시적인 FinFET의 개략도이다.
도 6a 내지 도 6e는 일부 실시예에 따라 도 4의 예시적인 FinFET를 제조하는 중간 단계들이다.
다양한 실시예를 형성하고 사용하는 것이 아래에 상세하게 설명된다. 그러나, 본 개시는 광범위하게 다양한 구체적 상황에서 구현될 수 있는 많은 적용가능한 발명의 개념을 제공하는 것임을 알아야 한다. 설명되는 구체적 실시예는 단지 본 개시를 형성하고 사용하기 위한 특정 방식을 예시한 것뿐이며 본 개시의 범위를 한정하지 않는다.
또한, 본 개시는 다양한 예에서 참조 번호 및/또는 문자를 반복할 수 있다. 이 반복은 단순하고 명확하게 하기 위한 목적이고, 설명되는 다양한 실시예 및/또는 구성 간의 관계를 그 자체가 지시하는 것은 아니다. 또한, 이어지는 다음의 본 개시에서 다른 특징부 상에, 다른 특징부에 접속 및/또는 연결되는 한 특징부의 형성은, 특징부들이 직접 접촉하여 형성되는 실시예를 포함할 수 있고, 특징부들이 직접 접촉하지 않도록 특징부들 중간에 추가의 특징부가 형성될 수 있는 실시예도 또한 포함할 수 있다. 또한, 공간적으로 상대적인 용어, 예를 들어 "하단", "상단", "수평","수직", "위", "위에", "아래", "아래에", "위로", "아래로", "상부", "하부" 등 뿐만 아니라 이의 변형어(예를 들어, "수평으로", "아래방향으로", "윗방향으로" 등)는 한 특징부의 다른 특징부에 대한 관계에 대해 본 개시를 용이하게 하고자 사용된다. 공간적으로 상대적인 용어는 특징부를 포함한 디바이스의 상이한 배향을 커버하도록 의도된다.
도 1은 일부 실시예에 따른 예시적인 FinFET(100)의 개략도이다. FinFET(100)은 기판(101), 기판 상에 형성된 핀 구조(102), 및 핀 구조(102) 내에 형성된 소스(103) 및 드레인(105), 소스(103)와 드레인(105) 사이의 핀 구조(102) 내의 채널(111)을 포함한다. 채널 위에 게이트 유전체 층(109)이 형성되고, 게이트 유전체 층(109) 위에 게이트(108)가 형성된다. 소스(103) 및 드레인(105) 중 적어도 하나는 하부 SiGe 층(106)을 포함한다. 스페이서(110)가 게이트(108)에 인접하게 형성된다. 일부 실시예에서, FinFET(100)는 인접한 디바이스로부터 쉘로우 트렌치 아이솔레이션(STI; shallow trench isolation) 구조(예를 들어, SiO2, 도시되지 않음)에 의해 격리될 수 있다.
일부 실시예에서, FinFET(100)는 N 타입 FinFET이다. 기판은 Si 또는 임의의 기타 적합한 재료를 포함한다. 소스(103) 및 드레인(105)은 SiP, SiCP, 또는 임의의 기타 적합한 재료를 포함하는 제1 층(104)을 포함한다. 제1 층(104)은 하부 SiGe 층(106) 위에 배치된다. 일부 실시예에서, 하부 SiGe 층(106)은 SiP 또는 SiCP를 포함하는 제1 층(104)의 하부에 형성된 에피텍셜 층이다. 스페이서(110)는 SiN, SiCN, SiCON, 기타 유전체 또는 임의의 기타 적합한 재료를 포함한다.
일부 실시예에서, 제1 층(104)(SiP 또는 SiCP)에 대한 하부 SiGe 층(106) 내의 SiGe의 부피 비는 10 % 내지 40 % 범위이다. 일부 실시예에서, 제1 층(104) 내의 인(P) 농도는 5e20 cm-3 내지 1e22 cm-3 범위이다. 일부 실시예에서, 제1 층(104)은 SiCP를 포함하고, 탄소 도핑 비율은 0.5 % 내지 2 % 범위이다.
일부 실시예에서, 핀 구조(102)의 높이 X, 소스(103) 또는 드레인(105)의 높이 Y, 및 하부 SiGe 층(106)의 높이 Z는 Z ≤ Y - X의 관계식을 갖는다. 일부 예에서, X는 30 nm 내지 40 nm 범위이고, Y는 45 nm 내지 60 nm 범위이고, Z는 5 nm 내지 15 nm 범위이고, 게이트(108) 길이 L은 15 nm 내지 30 nm 범위이다. 일부 실시예에서 소스(103) 및 드레인(105)의 상부는 핀 구조(102)보다 5 nm - 20 nm 더 높을 수 있다. 일부 실시예에서 소스(103) 및 드레인(105)의 하부는 기판(101) 상에 형성된 리세스에서 핀 구조(102) 아래일 수 있다. FinFET(100)의 치수는 디바이스 설계 및 응용에 따라 달라질 수 있다.
도 2는 일부 실시예에 따른 도 1의 예시적인 FinFET(100)에 대해 채널 변형(strain) 대 Fin 상부로부터의 거리의 그래프이다. 채널(111)은 Si를 포함하고, 하부 SiGe 층(106)은 양의 변형 값으로 도 2에 도시된 바와 같이 채널의 인접한 영역(핀 구조(102)의 상부로부터 약 30 nm - 40 nm)에 압축 응력을 가한다. 하부 SiGe 층(106)은 음의 변형 값으로 도 2에 도시된 바와 같이 채널(111)의 상부 영역(핀 구조(102)의 상부로부터 0 nm - 20 nm)에 인장 응력을 유도한다. 유도된 인장 응력의 결과로서 채널(111)의 상부 영역에서는 더 나은 모빌리티 이득이 얻어진다.
도 3a는 일부 실시예에 따른 도 1에서의 예시적인 FinFET(100)의 구동 전류 대 게이트 길이의 그래프이다. FinFET(100)의 곡선(302)은 더 나은 모빌리티 이득의 결과로서 다양한 게이트(108) 길이(L)에 대해 일부 다른 FinFET의 곡선(304)에 비교하여 개선된 구동 전류(Idsat) 성능을 보여준다.
도 3b는 일부 실시예에 따른 도 1에서의 예시적인 FinFET(100)의 총 저항 대 게이트 길이의 그래프이다. 총 저항(Rtot)은 채널 저항과 컨택 저항의 합이다. FinFET(100)의 곡선(306)은 다양한 게이트(108) 길이(L)에 대해 일부 다른 FinFET의 곡선(308)에 비교하여 감소된 총 저항(Rtot)을 보여준다.
따라서, FinFET(100)은 일부 실시예에서 N 타입 디바이스에 대한 인의 높은 도핑 농도를 갖는 동시에 단채널 효과를 극복하는 개선된 성능을 보여준다. 제1 층(104)의 인(P) 농도는 일부 실시예에서 5e20 cm-3 내지 1e22 cm-3 범위이다. 일부 실시예에서, 제1 층(104)의 인(P) 농도는 1e21 cm-3 내지 4e21 cm-3 범위이다.
도 4는 일부 실시예에 따른 다른 예시적인 FinFET(400)의 개략도이다. FinFET(400)은 도 1의 FinFET(100)과 유사하고, 소스(103a)와 드레인(105a) 중 적어도 하나는 SiGe 층(106a)을 포함한다. FinFET(400)의 소스(103a)/드레인(105a)은 SiGe 층(106a)을 형성하도록 하부 SiGe 층에 더하여 측벽 SiGe 층을 포함한다. 일부 실시예에서, 에피텍셜 SiGe 층(106a)은 SiP 또는 SiCP를 포함하는 제1 층(104a)의 하부 및 측벽에 형성된다.
도 5는 일부 실시예에 따른 또 다른 예시적인 FinFET의 개략도이다. FinFET(500)은 도 4의 FinFET(400)와 유사하고, 소스(103b)와 드레인(105b) 중 적어도 하나는 SiGe 층(106a)을 포함한다. FinFET(500)의 소스(103b)/드레인(105b)은 SiGe 층(106a)을 형성하도록 하부 SiGe 층에 더하여 측벽 SiGe 층을 포함한다.
또한, FinFET(500)의 소스(103b)/드레인(105b)은 제1 층(104a) 위에 제2 층(104b)을 더 포함한다. 제2 층(104b)은 제1 층(104a)보다 더 높은 도펀트 농도를 갖는다. 일부 실시예에서, 제1 층(104a) 및 제2 층(104b)은 SiP 또는 SiCP를 포함하고, 제1 층(104a)은 5e20 cm-3 내지 2e21 cm-3 범위의 인 농도를 가지며, 제2 층(104b)은 1e21 cm-3 내지 1e22 cm-3 범위의 인 농도를 갖는다.
일부 예에서, 제1 층(104a)은 7e20 cm-3 내지 1e21 cm-3 범위의 인 농도를 가지며, 제2 층(104b)은 1e21 cm-3 내지 4e21 cm-3 범위의 인 농도를 갖는다. 일부 실시예에서, 제1 층(104a) 및 제2 층(104b)은 SiCP를 포함하고, 탄소 도핑 비율은 0.5 % 내지 2 % 범위이다.
도 6a 내지 도 6e는 일부 실시예에 따른 도 4의 예시적인 FinFET을 제조하는 중간 단계들이다. 도 6a에서, 예를 들어 건식 에칭 및 화학적 기상 증착(CVD)에 의해 핀 구조(102) 및 쉘로우 트렌치 아이솔레이션 구조(602)가 기판(101) 상에 형성된다. (기판(101)은 단순화를 위해 후속 단계에서 도시되지 않음) 일부 실시예에서, 기판(101)은 Si를 포함하고 STI는 SiO2를 포함한다.
도 6b에서, STI는 예를 들어 핀 구조(102)를 형성하도록 염화 수소를 사용한 습식 에칭에 의해 에칭된다.
도 6c에서, 게이트 유전체 층(109) 및 게이트(108)가 형성된다. 예를 들어, SiO2 또는 임의의 기타 적합한 재료와 같은 게이트 유전체 층(109)이 고온 CVD에 의해 형성될 수 있다. 폴리실리콘 또는 금속과 같은 게이트(108)는 CVD 또는 원자층(AL) CVD에 의해 형성될 수 있다.
도 6d에서, 게이트(108)에 인접한 스페이서(110)(예를 들어, SiN)가 ALCVD 또는 고온 CVD를 사용하여 SiN를 증착함으로써 형성되고, 핀 구조(102) 내의(그리고 기판(101) 내의) 리세스(604)가 예를 들어 플라즈마 에칭에 의해 에칭된다.
도 6e에서, 소스(103a) 및 드레인(105a)이 형성된다. 예를 들어, SiGe 층(106a)(하부 SiGe 및 측벽 SiGe를 포함함)이 CVD에 의해 증착된다. 그 다음, 제1 층(104a)(예를 들어, SiP)이 CVD에 의해 증착된다.
도 4의 FinFET(400)이 도 6a 내지 도 6e에서 예시적인 제조 단계에 대해 도시되었지만, 도 1의 FinFET(100) 및 도 5의 FinFET(500)도 마찬가지의 단계에서 제조될 수 있다.
일부 실시예에 따르면, FinFET은 기판, 기판 상의 핀 구조, 핀 구조 내의 소스, 핀 구조 내의 드레인, 소스와 드레인 사이의 핀 구조 내의 채널, 채널 위의 게이트 유전체 층, 및 게이트 유전체 층 위의 게이트를 포함한다. 소스와 드레인 중 적어도 하나는 하부 SiGe 층을 포함한다.
일부 실시예에 따르면, FinFET을 형성하는 방법은 기판 상에 핀 구조를 형성하는 것을 포함한다. 소스 및 드레인이 형성되고, 소스와 드레인 중 적어도 하나는 하부 SiGe 층을 포함한다. 게이트 유전체 층이 소스와 드레인 사이의 채널 위에 형성된다. 게이트가 게이트 유전체 층 위에 형성된다.
당해 기술 분야에서의 숙련자라면 본 개시의 많은 실시예 변형이 있을 수 있다는 것을 알 것이다. 실시예 및 이의 특징이 상세하게 기재되었지만, 실시예의 사상 및 범위에서 벗어나지 않고서 다양한 변경, 치환 및 대안이 여기에 행해질 수 있다는 것을 이해하여야 한다. 또한, 본 출원의 범위는 명세서에 기재된 프로세스, 기계, 제조, 및 물질 조성물, 수단, 방법 및 단계의 특정 실시예에 한정되고자 하는 것이 아니다. 당해 기술 분야에서의 통상의 지식을 가진 자라면, 여기에 기재된 대응하는 실시예와 실질적으로 동일한 기능을 수행하거나 실질적으로 동일한 결과를 달성하는, 현재 존재하거나 나중에 개발될, 프로세스, 기계, 제조, 물질 조성물, 수단, 방법 또는 단계가 본 개시에 따라 이용될 수 있다는 것을 개시된 실시예로부터 용이하게 알 수 있을 것이다.
상기 방법 실시예는 예시적인 단계들을 보여주지만, 이들이 보여준 순서대로 반드시 수행되어야 하는 것은 아니다. 단계들은 본 개시의 실시예의 사상 및 범위에 따라, 적합하게 추가되거나, 교체되거나, 순서가 바뀌거나 그리고/또는 삭제될 수 있다. 상이한 청구항 및/또는 상이한 실시예를 조합한 실시예가 본 개시의 범위 내에 속하고, 본 개시를 검토한 후에 당해 기술 분야에서의 숙련자에게 명백할 것이다.
100: FinFET 101: 기판
102: 핀 구조 103: 소스
105: 드레인 106: 하부 SiGe 층
108: 게이트 109: 게이트 유전체 층
111: 채널

Claims (10)

  1. FinFET에 있어서,
    기판;
    상기 기판 상의 핀 구조;
    상기 핀 구조 내의 소스;
    상기 핀 구조 내의 드레인;
    상기 소스와 상기 드레인 사이의 상기 핀 구조 내의 채널;
    상기 채널 위의 게이트 유전체 층; 및
    상기 게이트 유전체 층 위의 게이트를 포함하고,
    상기 소스와 상기 드레인 중 적어도 하나는 하부 SiGe 층을 포함하는 것인 FinFET.
  2. 청구항 1에 있어서, 상기 소스 또는 상기 드레인 중 적어도 하나에 측벽 SiGe 층을 더 포함하는 FinFET.
  3. 청구항 1에 있어서, 상기 소스 및 상기 드레인은 SiP 또는 SiCP를 포함하는 제1 층을 포함하고, 상기 제1 층은 상기 하부 SiGe 층 위에 배치되는 것인 FinFET.
  4. 청구항 3에 있어서, SiP에 대한 SiGe 또는 SiCP에 대한 SiGe의 부피 비는 10 % 내지 40 % 범위인 것인 FinFET.
  5. 청구항 3에 있어서, 상기 제1 층의 인 농도는 5e20 cm-3 내지 1e22 cm-3 범위인 것인 FinFET.
  6. 청구항 3에 있어서, 상기 소스 및 상기 드레인은 SiP 또는 SiCP를 포함하는 제2 층을 더 포함하고, 상기 제2 층은 상기 제1 층 위에 배치되며, 상기 제2 층은 상기 제1 층보다 더 높은 인 농도를 갖는 것인 FinFET.
  7. 청구항 6에 있어서, 상기 제1 층은 5e20 cm-3 내지 2e21 cm-3 범위의 인 농도를 갖고, 상기 제2 층은 1e21 cm-3 내지 1e22 cm-3 범위의 인 농도를 갖는 것인 FinFET.
  8. 청구항 1에 있어서, 상기 핀 구조의 높이 X, 상기 소스 또는 상기 드레인의 높이 Y, 및 상기 하부 SiGe 층의 높이 Z는 Z ≤ Y - X의 관계식을 갖는 것인 FinFET.
  9. FinFET을 형성하는 방법에 있어서,
    기판 상에 핀 구조를 형성하는 단게;
    소스 및 드레인을 형성하는 단계 - 상기 소스와 상기 드레인 중 적어도 하나는 하부 SiGe 층을 가짐 - ;
    상기 소스와 상기 드레인 사이의 채널 위에 게이트 유전체 층을 형성하는 단계; 및
    상기 게이트 유전체 층 위에 게이트를 형성하는 단계를 포함하는 FinFET의 형성 방법.
  10. FinFET에 있어서,
    기판;
    상기 기판 상의 핀 구조;
    상기 핀 구조 내의 소스;
    상기 핀 구조 내의 드레인;
    상기 소스와 상기 드레인 사이의 상기 핀 구조 내의 채널;
    상기 채널 위의 게이트 유전체 층; 및
    상기 게이트 유전체 층 위의 게이트를 포함하고,
    상기 소스와 상기 드레인 중 적어도 하나는 SiP 또는 SiCP를 포함하는 상부 층, 하부 SiGe 층, 및 측벽 SiGe 층을 포함하는 것인 FinFET.
KR20130058486A 2013-03-13 2013-05-23 소스/드레인에 하부 ＳｉＧｅ 층을 갖는 FinFET KR101492719B1 (ko)

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US20160163836A1 (en) 2016-06-09
DE102013105735B4 (de) 2017-09-21
US20140264590A1 (en) 2014-09-18
CN104051525B (zh) 2016-12-28
US8963258B2 (en) 2015-02-24
US9293581B2 (en) 2016-03-22
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