CN104051525A - 源极/漏极中带有底部SiGe层的FinFET - Google Patents
源极/漏极中带有底部SiGe层的FinFET Download PDFInfo
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- 229910000577 Silicon-germanium Inorganic materials 0.000 title claims abstract description 44
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- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 22
- 229910052698 phosphorus Inorganic materials 0.000 claims description 22
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- 238000000034 method Methods 0.000 claims description 9
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 4
- 229910052799 carbon Inorganic materials 0.000 claims description 4
- 229910020263 SiP Inorganic materials 0.000 claims description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 8
- 238000010586 diagram Methods 0.000 description 6
- 239000000463 material Substances 0.000 description 6
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- 229910004298 SiO 2 Inorganic materials 0.000 description 2
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- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 1
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- 238000001312 dry etching Methods 0.000 description 1
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- 229910000041 hydrogen chloride Inorganic materials 0.000 description 1
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- 239000002184 metal Substances 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
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- H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
Abstract
本发明涉及源极/漏极中带有底部SiGe层的FinFET,提供了一种FinFET包括:衬底;鳍结构,位于衬底上;源极,位于鳍结构中;漏极,位于鳍结构中;沟道,位于鳍结构中,在源极与漏极之间;栅极介电层,位于沟道上方;以及栅极,位于栅极介电层上方。源极和漏极中的至少一个包括底部SiGe层。
Description
技术领域
本发明总体上涉及半导体器件,更具体地,涉及一种FinFET。
背景技术
在一些FinFET器件中,随着器件尺寸的减小,弱驱动电流和短沟道效应是具有挑战的问题。具有改进的驱动电流并减弱短沟道效应的FinFET是人们的期望。
发明内容
为解决上述问题,本发明提供了一种FinFET,包括:衬底;鳍结构,位于所述衬底上;源极,位于所述鳍结构中;漏极,位于所述鳍结构中;沟道,在所述鳍结构中位于所述源极与所述漏极之间;栅极介电层,位于所述沟道上方;以及栅极,位于所述栅极介电层上方,其中,所述源极和所述漏极中的至少一个包括底部SiGe层。
该FinFET进一步包括侧壁SiGe层,位于所述源极和所述漏极中的至少一个中。
其中,所述源极和所述漏极包括具有SiP或SiCP的第一层,所述第一层布置在所述底部SiGe层上方。
其中,SiGe与SiP的体积比或SiGe与SiCP的体积比的范围在10%到40%之间。
其中,所述第一层的磷的浓度范围在5e20cm-3到1e22cm-3之间。
其中,所述第一层包括SiCP并且所述第一层的碳掺杂百分比范围在0.5%到2%之间。
其中,所述源极和所述漏极进一步包括具有SiP或SiCP的第二层,所述第二层沉积在所述第一层上方,并且所述第二层的磷的浓度比所述第一层的磷的浓度更高。
其中,所述第一层的磷的浓度范围在5e20cm-3到2e21cm-3之间。
其中,所述第二层的磷的浓度范围在1e21cm-3到1e22cm-3之间。
其中,所述鳍结构的高度X、所述源极或所述漏极的高度Y、和所述底部SiGe层的高度Z的关系是Z≤Y-X。
该FinFET进一步包括邻近所述栅极的隔离件。
其中,所述隔离件包括SiN、SiCN、或SiCON。
此外,还提供了一种形成FinFET的方法,包括:在衬底上形成鳍结构;形成源极和漏极,所述源极和所述漏极中的至少一个包括底部SiGe层;在所述源极和所述漏极之间的沟道上方形成栅极介电层;以及在所述栅极介电层上方形成栅极。
其中,形成所述源极和所述漏极包括在所述源极和所述漏极中的至少一个中形成侧壁SiGe层。
其中,形成所述源极和所述漏极包括形成具有SiP或SiCP的第一层,并且所述第一层布置在所述底部SiGe层上方。
其中,所述第一层的磷的浓度范围在5e20cm-3到1e22cm-3之间。
其中,形成所述源极和所述漏极进一步包括在所述第一层上方形成第二层,所述第二层包括SiP或SiCP,并且所述第二层的磷的浓度比所述第一层的磷的浓度更高。
其中,所述第一层的磷的浓度范围在5e20cm-3到2e21cm-3之间,所述第二层的磷的浓度范围在1e21cm-3到1e22cm-3之间。
该方法进一步包括形成邻近所述栅极的隔离件。
此外,还提供了一种FinFET,包括:衬底;鳍结构,位于所述衬底上;源极,位于所述鳍结构中;漏极,位于所述鳍结构中;沟道,在所述鳍结构中位于所述源极与所述漏极之间;栅极介电层,位于所述沟道上方;以及栅极,位于所述栅极介电层上方,其中,所述源极和所述漏极中的至少一个包括具有SiP或SiCP的顶层、底部SiGe层、和侧壁SiGe层。
附图说明
下面将结合附图进行下列说明,其中:
图1是根据一些实施例的示例性的FinFET的原理图;
图2是根据一些实施例的沟道应变(strain)与图1中示例性FinFET的鳍顶距离的曲线图;
图3A是根据一些实施例的驱动电流与图1中示例性FinFET的栅极长度的曲线图;
图3B是根据一些实施例的总电阻与图1中示例性FinFET的栅极长度的曲线图;
图4是根据一些实施例的另一个示例性FinFET的原理图;
图5是根据一些实施例的又一个示例性FinFET的原理图;以及
图6A至图6E是根据一些实施例的制造图4中示例性FinFET的中间步骤。
具体实施方式
各种实施例的制造和使用的细节讨论如下。应该理解,本发明提供了许多可以在各种具体环境中实现的可应用的创新概念。所讨论的具体实施例仅仅示出制造和使用本发明的具体方式,而不用于限制本公开的范围。
另外,本发明可在各个实例中重复参考标记和/或字母。该重复是为了简明和清楚,而且其本身没有规定所述各种实施例和/或结构之间的关系。而且,在本公开中一个部件上的结构、连接、和/或耦合另一个部件,可以包括直接形成连接部件的实施例,也可以包括在部件之间插入形成附加部件的实施例,这样两部件就不能直接连接。另外,在本公开中,空间连接词,例如,“低于”、“高于”、“水平”、“垂直”、“上方”、“以上”、“以下”、“在下方”、“上”、“下”、“顶端”、“底端:、等以上词的派生词(例如,“水平的”、“向下的”、“向上的”等)用于简便描述一个部件与另一个部件的关系。空间连接词意在涵盖包括部件的不同方向的器件。
图1是根据一些实施例的示例性的FinFET100的原理图。FinFET100包括衬底101、在衬底上形成的鳍结构102、在鳍结构102中形成的源极103和漏极105、在鳍结构102中源极103和漏极105间的沟道111。栅极介电层109在沟道上方形成,栅极108在栅极介电层109上方形成。源极103和漏极105中的至少一个包括底部SiGe层106。邻近栅极108形成隔离件110。在一些实施例中,FinFET100可以通过浅沟槽隔离(STI)结构与邻近的器件隔离开。
在一些实施例中,FinFET100是N型FinFET。衬底包括Si或任意其他合适的材料。源极103和漏极105包括具有SiP、SiCP、或任意其他合适材料的第一层104。第一层104沉积在底部SiGe层106上方。在一些实施例中,底部SiGe层106是在包括SiP或SiCP的第一层104底部形成的外延层。隔离件110包括SiN、SiCN、SiCON、其他电介质、或任意其他合适的材料。
在一些实施例中,底部SiGe层106中和第一层104(SiP或SiCP)中的SiGe的体积比的范围为10%到40%。在一些实施例中,第一层104中磷(P)的浓度范围在5e20cm-3到1e22cm-3之间。在一些实施例中,第一层104包括SiCP,并且碳掺杂的比例范围从0.5%到2%。
在一些实施例中,鳍结构102的高度X、源极103或漏极105的高度Y、和底部SiGe层106的高度Z的关系是Z≤Y-X。在一些实施例中,X的范围为30nm到40nm,Y的范围为45nm到60nm,Z的范围为5nm到15nm,以及栅极108的长度范围为15nm到30nm。在一些实施例中,源极103和漏极105的顶部可以比鳍结构102高5nm到20nm。在一些实施例中,源极103和漏极105的底部可以低于在衬底101上形成的凹槽中的鳍结构102。FinFET100的尺寸可以根据器件的设计和应用进行改变。
图2是根据一些实施例的沟道应变与图1中示例性FinFET100的鳍顶距离的曲线图。沟道111包括Si并且底部SiGe层106将压缩应力加载到沟道111的邻近区域(从鳍结构102顶部的大约30nm到40nm处)(图2中所示的正应变值)。底部SiGe层106将拉伸应力引导到沟道111的上部区域(从鳍结构102顶部的0nm到20nm处)(图2中所示的负应变值)。引导的拉伸应力可以使沟道111的上部区域具有更好的迁移率增益(mobility gain)。
图3A是根据一些实施例的驱动电流与图1中示例性FinFET100的栅极长度的曲线图。与一些其他FinFET的曲线304相比,针对各种栅极108的长度(L),FinFET100的曲线302显示出驱动电流(Idsat)性能得到了改进,从而获得了更好的迁移率收益。
图3B是根据一些实施例的总电阻与图1中示例性FinFET100的栅极长度的曲线图。总电阻(Rtot)是沟道电阻和接触电阻的和。与一些其他FinFET的曲线308相比,针对各种栅极108的长度(L),FinFET100的曲线306显示出总电阻(Rtot)有所减小。
因此,在一些实施例中,当N型器件掺杂高浓度的磷时,FinFET100表现出性能改善以克服短沟道效应。在一些实施例中,第一层104的磷(P)的浓度范围从5e20cm-3到1e22cm-3。在一些实施例中,第一层104的磷(P)的浓度范围从1e21cm-3到4e21cm-3。
图4是根据一些实施例的另一个示例性FinFET400的原理图。FinFET400与图1中FinFET100相似,并且源极103a和漏极105a中的至少一个包括SiGe层106a。FinFET400的源极103a/漏极105a包括侧壁SiGe层及底部SiGe层,以形成SiGe层106a。在一些实施例中,外延SiGe层106a形成包括SiP或SiCP的第一层104a的侧壁和底部。
图5是根据一些实施例的又一个示例性FinFET的原理图。FinFET500与图4中的FinFET400相似,并且源极103b和漏极105b中的至少一个包括SiGe层106a。FinFET500的源极103b/漏极105b包括侧壁SiGe层及底部SiGe层,以形成SiGe层106a。
另外,FinFET500的源极103b/漏极105b进一步包括在第一层104a上方的第二层104b。第二层104b比第一层104a具有更高的掺杂浓度。在一些实施例中,第一层104a和第二层104b包括SiP或SiCP,并且第一层104a的磷的浓度范围为5e20cm-3到2e21cm-3,而第二层104b的磷的浓度范围为1e21cm-3到1e22cm-3。
在一些实施例中,第一层104a的磷的浓度范围为7e20cm-3到1e21cm-3,而第二层104b的磷的浓度范围为1e21cm-3到4e21cm-3。在一些实施例中,第一层104a和第二层104b包括SiCP,并且碳掺杂的百分比范围为0.5%到2%。
图6A至图6E是根据一些实施例的制造图4中示例性FinFET的中间步骤。例如,在图6A中,鳍结构102和浅沟槽隔离结构602通过干式蚀刻和化学汽相沉积(CVD)在衬底101上形成。(为了简便,衬底101未在接下来的步骤中示出。)在一些实施例中,衬底101包括Si且STI包括SiO2。
例如,在图6B中,STI通过使用氯化氢的湿式蚀刻来蚀刻STI,以形成鳍结构102。
在图6C中,形成栅极介电层109和栅极108。例如,诸如SiO2或任意其他合适材料的栅极介电层109可以通过高温CVD形成。诸如多晶硅或金属的栅极108可以通过CVD或原子层(AL)CVD形成。
例如,在图6D中,邻近栅极108的隔离件110通过使用ALCVD或高温CVD沉积SiN形成,并且通过等离子体蚀刻来蚀刻出鳍结构102中(和衬底101中)的凹槽604。
在图6E中,形成源极103a和漏极105a。例如,SiGe层106a(包括底部SiGe和侧壁SiGe)通过CVD沉积。然后第一层104a(例如SiP)通过CVD沉积。
尽管示出了在图6A至图6E中作为示例性制造步骤的图4中FinFET400,但图1中的FinFET100和图5中的FinFET500也可以通过相似的步骤制造。
根据一些实施例,一种FinFET包括:衬底;鳍结构,位于衬底上;源极,位于鳍结构中;漏极,位于鳍结构中;沟道,位于鳍结构中,在源极与漏极之间;栅极介电层,位于沟道上方;以及栅极,位于栅极介电层上方。源极和漏极中的至少一个包括底部SiGe层。
根据一些实施例,一种形成FinFET的方法包括:在衬底上形成鳍结构。形成源极和漏极,源极和漏极中的至少一个包括底部SiGe层。在源极与漏极之间的沟道上方形成栅极介电层。在栅极介电层上方形成栅极。
本领域中的技术人员应该理解,可以存在本发明的多个实施例的变型例。尽管已经详细地描述了实施例及其部件,但应该理解,可以在不背离本实施例的主旨和范围的情况下,做各种不同的改变,替换和更改。而且,本申请的范围并不仅限于本说明书中描述的工艺、机器、制造、材料组分、装置、方法和步骤的特定实施例。作为本领域普通技术人员应理解,通过本实施例,现有的或今后开发的用于执行与本文所述相应实施例基本相同的功能或获得基本相同结果的工艺、机器、制造,材料组分、装置、方法或步骤根据本发明可以被使用。
以上方法实施例示出了示例性步骤,但是不需要一定按照所示顺序实施。根据本发明的实施例的主旨和范围,可以适当地增加,替换,改变顺序和/或删除步骤。包括不同权利要求的实施例和/或不同实施例在本发明的范围内,并且本领域中的技术人员在审阅本发明以后,可以理解这些实施例和/或不同实施例。
Claims (10)
1.一种FinFET,包括:
衬底;
鳍结构,位于所述衬底上;
源极,位于所述鳍结构中;
漏极,位于所述鳍结构中;
沟道,在所述鳍结构中位于所述源极与所述漏极之间;
栅极介电层,位于所述沟道上方;以及
栅极,位于所述栅极介电层上方,
其中,所述源极和所述漏极中的至少一个包括底部SiGe层。
2.根据权利要求1所述的FinFET,进一步包括侧壁SiGe层,位于所述源极和所述漏极中的至少一个中。
3.根据权利要求1所述的FinFET,其中,所述源极和所述漏极包括具有SiP或SiCP的第一层,所述第一层布置在所述底部SiGe层上方。
4.根据权利要求3所述的FinFET,其中,SiGe与SiP的体积比或SiGe与SiCP的体积比的范围在10%到40%之间。
5.根据权利要求3所述的FinFET,其中,所述第一层的磷的浓度范围在5e20cm-3到1e22cm-3之间。
6.根据权利要求3所述的FinFET,其中,所述第一层包括SiCP并且所述第一层的碳掺杂百分比范围在0.5%到2%之间。
7.根据权利要求3所述的FinFET,其中,所述源极和所述漏极进一步包括具有SiP或SiCP的第二层,所述第二层沉积在所述第一层上方,并且所述第二层的磷的浓度比所述第一层的磷的浓度更高。
8.根据权利要求7所述的FinFET,其中,所述第一层的磷的浓度范围在5e20cm-3到2e21cm-3之间。
9.一种形成FinFET的方法,包括:
在衬底上形成鳍结构;
形成源极和漏极,所述源极和所述漏极中的至少一个包括底部SiGe层;
在所述源极和所述漏极之间的沟道上方形成栅极介电层;以及
在所述栅极介电层上方形成栅极。
10.一种FinFET,包括:
衬底;
鳍结构,位于所述衬底上;
源极,位于所述鳍结构中;
漏极,位于所述鳍结构中;
沟道,在所述鳍结构中位于所述源极与所述漏极之间;
栅极介电层,位于所述沟道上方;以及
栅极,位于所述栅极介电层上方,
其中,所述源极和所述漏极中的至少一个包括具有SiP或SiCP的顶层、底部SiGe层、和侧壁SiGe层。
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CN101097956B (zh) * | 2006-06-29 | 2012-06-27 | 国际商业机器公司 | 一种FinFET结构和制作FinFET结构的方法 |
CN101986423A (zh) * | 2009-07-28 | 2011-03-16 | 台湾积体电路制造股份有限公司 | 形成高锗浓度的硅锗应力源的方法及集成电路晶体管结构 |
US20130001591A1 (en) * | 2011-06-30 | 2013-01-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Finfet design and method of fabricating same |
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CN107123680A (zh) * | 2016-02-25 | 2017-09-01 | 台湾积体电路制造股份有限公司 | 鳍式场效应晶体管及其制造方法 |
CN107123680B (zh) * | 2016-02-25 | 2022-03-08 | 台湾积体电路制造股份有限公司 | 鳍式场效应晶体管及其制造方法 |
CN108281481A (zh) * | 2017-01-05 | 2018-07-13 | 三星电子株式会社 | 半导体装置 |
CN108281481B (zh) * | 2017-01-05 | 2023-04-28 | 三星电子株式会社 | 半导体装置 |
CN112018179A (zh) * | 2019-05-28 | 2020-12-01 | 三星电子株式会社 | 半导体器件及其制造方法 |
Also Published As
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US20150137180A1 (en) | 2015-05-21 |
US9911829B2 (en) | 2018-03-06 |
KR20140112347A (ko) | 2014-09-23 |
US20160163836A1 (en) | 2016-06-09 |
KR101492719B1 (ko) | 2015-02-11 |
US8963258B2 (en) | 2015-02-24 |
DE102013105735B4 (de) | 2017-09-21 |
CN104051525B (zh) | 2016-12-28 |
US9293581B2 (en) | 2016-03-22 |
US20140264590A1 (en) | 2014-09-18 |
DE102013105735A1 (de) | 2014-09-18 |
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