KR20130048155A - Semiconductor device - Google Patents

Abstract

PURPOSE: A semiconductor device is provided to prevent the diffusion of a first and a second metal element in a glass substrate and to secure a transistor having a stable electrical property. CONSTITUTION: A gate electrode layer(401) is formed on a glass substrate(400) including at least one metal element. A first gate insulating layer(436) is formed on the gate electrode layer. A second gate insulating layer(402) is formed on the first gate insulating layer. An oxide semiconductor layer(403) is formed on the second gate insulating layer. A source electrode layer(405a) and a drain electrode layer(405b) are formed on the oxide semiconductor layer.

Description

Semiconductor device {SEMICONDUCTOR DEVICE}

The present invention relates to a semiconductor device and a method of manufacturing a semiconductor device.

In this specification, a semiconductor device refers to the entire device that can function by utilizing semiconductor characteristics, and the electro-optical device, the semiconductor circuit, and the electronic device are all semiconductor devices.

A technique for constructing a transistor (also referred to as a thin film transistor (TFT)) using a semiconductor thin film formed on a substrate having an insulating surface has attracted attention. The transistor is widely applied to electronic devices such as an integrated circuit (IC) and an image display device (display device). Although silicon-based semiconductor materials are widely known as semiconductor thin films that can be applied to transistors, oxide semiconductors have attracted attention as other materials.

In the display device, a glass substrate is suitably used as the light transmitting member.

For example, Patent Document 1 discloses a transistor using a semiconductor layer made of amorphous oxide (In-Ga-Zn-O based amorphous oxide) containing indium (In), gallium (Ga), and zinc (Zn) on a glass substrate. Is described.

Japanese Laid-Open Patent Application No. 2011-181801

By the way, in order to commercialize the semiconductor device which has a transistor using an oxide semiconductor, it is important to achieve high reliability.

In particular, fluctuations or deterioration in electrical characteristics of semiconductor devices cause deterioration of reliability.

In view of these problems, it is one of the problems to provide a highly reliable semiconductor device having a transistor using an oxide semiconductor.

A semiconductor device having a staggered transistor of a bottom-gate structure provided on a glass substrate, wherein at least a first gate insulating film and a second gate insulating film are provided between the gate electrode layer and the oxide semiconductor film. The composition of the first gate insulating film provided on the gate electrode layer side and the composition of the second gate insulating film provided on the oxide semiconductor film side are different. Further, at the interface between the first gate insulating film and the second gate insulating film, the concentration of the first metal element contained in the glass substrate is 5 × 10 ¹⁸ atoms / cm ³ or less (preferably 1 × 10 ¹⁸ atoms / cm ^3). Or less).

A thin film nitride insulating film can be used for the first gate insulating film. For example, a silicon nitride film, a silicon nitride oxide film, etc. are mentioned. The first gate insulating film may be either a single layer structure or a laminated structure. The film thickness of a 1st gate insulating film can be made thin, and can be 30 nm or more and 50 nm or less.

Since the first gate insulating film is provided between the glass substrate and the second gate insulating film and the oxide semiconductor film, it is possible to prevent the first metal element contained in the glass substrate from diffusing into the second gate insulating film and the oxide semiconductor film. .

A semiconductor device having a staggered transistor having a lower gate structure provided over a glass substrate, comprising: a second insulating film contained in the glass substrate at an interface between the gate electrode layer and the gate insulating film by providing a protective insulating film between the glass substrate and the gate electrode layer; The concentration of the metal element is 5 × 10 ¹⁸ atoms / cm ³ or less (preferably 1 × 10 ¹⁸ atoms / cm ³ or less).

A nitride insulating film can be used for the protective insulating film. For example, a silicon nitride film, a silicon nitride oxide film, etc. are mentioned. The protective insulating film may be either a single layer structure or a laminated structure. For example, the nitride insulating film and the oxide insulating film may be laminated in this order from the glass substrate side.

Since a protective insulating film is provided between the glass substrate and the transistor, it is possible to prevent the second metal element contained in the glass substrate from diffusing into the transistor.

Said "1st metal element contained in a glass substrate" is an element other than the main element which comprises a 1st gate insulating film and a 2nd gate insulating film, and refers to the element diffused from a glass substrate.

The "second metal element contained in the glass substrate" is an element other than the main elements constituting the gate electrode layer and the gate insulating film, and refers to an element diffused from the glass substrate.

The first metal element and the second metal element to be reduced in order not to lower the reliability (stability of the characteristic) of the transistor are sodium, aluminum, magnesium, calcium, strontium, barium, and further other elements contained in the glass substrate. It is desirable to reduce silicon and boron to the same level.

Since the diffusion of the 1st metal element or the 2nd metal element contained in a glass substrate which become a factor which causes the fall or the fluctuation | variation of the electrical characteristics of a transistor can be prevented, stable electrical characteristics can be provided to a transistor.

Accordingly, a highly reliable semiconductor device including a transistor having stable electrical characteristics using an oxide semiconductor film can be provided.

One embodiment of the configuration of the invention described in the present specification is a second gate insulating film having a composition different from that of the first gate insulating film sequentially stacked on the glass substrate, the gate electrode layer, the first gate insulating film on the gate electrode layer, and the first gate insulating film. , An oxide semiconductor film, and a source electrode layer and a drain electrode layer, and at an interface between the first gate insulating film and the second gate insulating film, the concentration of the first metal element contained in the glass substrate is 5 × 10 ¹⁸ atoms / cm ³ or less. , Semiconductor device.

Another form of the structure of this invention described in this specification is the 2nd gate whose composition differs from a 1st gate insulating film sequentially laminated on the gate electrode layer on a glass substrate, a 1st gate insulating film on a gate electrode layer, and a 1st gate insulating film. An insulating layer, an oxide semiconductor film, an insulating layer in contact with the oxide semiconductor film superimposed with the gate electrode layer, and a source electrode layer and a drain electrode layer, each of which is contained in a glass substrate at an interface between the first gate insulating film and the second gate insulating film. The concentration of one metal element is a semiconductor device which is 5 × 10 ¹⁸ atoms / cm ³ or less.

One embodiment of the configuration of the invention described in this specification includes a protective insulating film on a glass substrate, a gate electrode layer on the protective insulating film, a gate insulating film, an oxide semiconductor film, a source electrode layer, and a drain electrode layer sequentially stacked on the gate electrode layer, At the interface between the gate electrode layer and the gate insulating film, the concentration of the second metal element contained in the glass substrate is 5 × 10 ¹⁸ atoms / cm ³ or less.

Another embodiment of the configuration of the present invention described in this specification is an oxide semiconductor film overlapping a gate insulating film, an oxide semiconductor film, and a gate electrode layer sequentially stacked on a protective substrate on a glass substrate, a gate electrode layer on the protective insulating film, and a gate electrode layer. And a source electrode layer and a drain electrode layer, the semiconductor device having a concentration of a second metal element contained in the glass substrate at 5 × 10 ¹⁸ atoms / cm ³ or less at an interface between the gate electrode layer and the gate insulating film. to be.

One embodiment of the present invention relates to a semiconductor device having a transistor or a circuit including the transistor. For example, the present invention relates to a transistor in which a channel formation region is formed of an oxide semiconductor, or a semiconductor device having a circuit including the transistor. For example, an LSI, a CPU, a power device mounted in a power supply circuit, a semiconductor integrated circuit including a memory, a thyristor, a converter, an image sensor, or the like, an electro-optical device represented by a liquid crystal display panel, or light emission The present invention relates to an electronic apparatus equipped with a light emitting display device having elements.

A highly reliable semiconductor device having a transistor using an oxide semiconductor is provided.

1A is a plan view illustrating one embodiment of a semiconductor device, and FIG. 1B is a cross-sectional view illustrating one embodiment of a semiconductor device.
2A to 2E are cross-sectional views illustrating one embodiment of a method of manufacturing a semiconductor device.
3A is a plan view illustrating one embodiment of a semiconductor device, and FIG. 3B is a cross-sectional view illustrating one embodiment of a semiconductor device.
4A is a plan view illustrating one embodiment of a semiconductor device, and FIG. 4B is a cross-sectional view illustrating one embodiment of a semiconductor device.
5A to 5C are plan views illustrating one embodiment of a semiconductor device.
6A is a plan view illustrating one embodiment of a semiconductor device, and FIG. 6B is a cross-sectional view illustrating one embodiment of a semiconductor device.
7A and 7B are cross-sectional views showing one embodiment of a semiconductor device.
8A is a circuit diagram illustrating one embodiment of a semiconductor device, and FIG. 8B is a cross-sectional view illustrating one embodiment of a semiconductor device.
9A-9C illustrate electronic devices.
10A to 10C illustrate electronic devices.
11A is a plan view illustrating one embodiment of a semiconductor device, and FIG. 11B is a cross-sectional view illustrating one embodiment of a semiconductor device.
12A to 12E are cross-sectional views illustrating one embodiment of a method of manufacturing a semiconductor device.
13A is a plan view illustrating one embodiment of a semiconductor device, and FIG. 13B is a cross-sectional view illustrating one embodiment of a semiconductor device.
14A is a plan view illustrating one embodiment of a semiconductor device, and FIG. 14B is a cross-sectional view illustrating one embodiment of a semiconductor device.
15A is a plan view illustrating one embodiment of a semiconductor device, and FIG. 15B is a cross-sectional view illustrating one embodiment of a semiconductor device.
16A and 16B are sectional views showing one embodiment of a semiconductor device.
17A is a circuit diagram illustrating one embodiment of a semiconductor device, and FIG. 17B is a cross-sectional view illustrating one embodiment of a semiconductor device.

EMBODIMENT OF THE INVENTION Hereinafter, embodiment of this invention shown in this specification is described in detail using drawing. However, the invention presented in this specification is not limited to the following description, and it can be easily understood by those skilled in the art that various changes in form and details thereof can be made. In addition, invention presented in this specification is limited to the content of embodiment described below, and is not interpreted. In addition, the ordinal numbers attached by "1st" and "2nd" are used for convenience, and do not represent a process order or lamination order. In addition, in this specification, as a matter for specifying invention, the original name is not shown.

(Embodiment 1)

In this embodiment, one embodiment of the semiconductor device and the manufacturing method of the semiconductor device will be described with reference to FIGS. 1A and 1B. In this embodiment, a transistor having an oxide semiconductor film is presented as an example of a semiconductor device.

The transistor may be either a single gate structure in which one channel formation region is formed, a double gate structure in which two channel formation regions are formed, or a triple gate structure in which three channel formation regions are formed. Alternatively, a dual gate type may be provided having two gate electrode layers disposed above and below the channel formation region with a gate insulating film interposed therebetween.

The transistor 440 shown in FIGS. 1A and 1B is one example of a bottom gate structure and is an example of a transistor, also referred to as an inverted-staggered transistor. FIG. 1A is a plan view, and a cross section of a portion cut along the dashed-dotted line V-Z shown in FIG. 1A corresponds to FIG. 1B.

As shown in FIG. 1B, which is a cross-sectional view of the transistor 440 in the channel length direction, the semiconductor device including the transistor 440 may be formed to cover the gate electrode layer 401 and the gate electrode layer 401 on the glass substrate 400. A first gate insulating film 436 is provided, and has a second gate insulating film 402, an oxide semiconductor film 403, a source electrode layer 405a, and a drain electrode layer 405b over the first gate insulating film 436. In addition, an insulating film 407 covering the transistor 440 is provided.

At least a first gate insulating film 436 and a second gate insulating film 402 are provided between the gate electrode layer 401 and the oxide semiconductor film 403. The composition of the first gate insulating film 436 provided on the gate electrode layer 401 side and the composition of the second gate insulating film 402 provided on the oxide semiconductor film 403 side are different. Further, at the interface between the first gate insulating film 436 and the second gate insulating film 402, the concentration of the first metal element contained in the glass substrate 400 is 5 × 10 ¹⁸ atoms / cm ³ or less (preferably Is 1 × 10 ¹⁸ atoms / cm ³ or less). The 'first metal element contained in the glass substrate 400' is an element other than the main elements constituting the first gate insulating film 436 and the second gate insulating film 402 and is diffused from the glass substrate 400. Point to.

The concentration of the first metal element contained in the glass substrate 400 is measured by using secondary ion mass spectrometry (SIMS).

A thin film nitride insulating film may be used for the first gate insulating film 436. For example, a silicon nitride film, a silicon nitride oxide film, etc. are mentioned. The film thickness of the first gate insulating film 436 can be thin, and can be 30 nm or more and 50 nm or less. The first gate insulating film 436 may be either a single layer structure or a stacked structure.

In addition, as the first gate insulating film 436 to prevent diffusion of impurities from the glass substrate 400, titanium (Ti), molybdenum (Mo), tungsten (W), hafnium (Hf), tantalum (Ta), Metal oxide insulating films containing any one or more metal elements selected from lanthanum (La), zirconium (Zr), nickel (Ni), magnesium (Mg), barium (Ba), and aluminum (Al) (e.g., , An aluminum oxide film, an aluminum oxynitride film, a hafnium oxide film, a magnesium oxide film, a zirconium oxide film, a lanthanum oxide film, a barium oxide film), or a metal nitride insulating film (aluminum nitride film, oxynitride) containing the above-described metal element Aluminum film) can be used. A gallium oxide film, an In—Zr—Zn oxide film, an In—Fe—Zn oxide film, an In—Ce—Zn oxide film, or the like may also be used for the first gate insulating film 436.

Examples of the first metal element contained in the glass substrate 400 include the following elements. For example, when the glass substrate 400 is soda-lime glass, the components of the soda lime glass are silicon oxide (SiO ₂ ), sodium carbonate (Na ₂ CO ₃ ), and calcium carbonate (CaCO ₃ ). For this reason, elements, such as sodium and calcium, are an object as a metal element. In addition, if the class is called a glass substrate 400 (glass are soda is used) are so-called free (無) alkaline glass is used in a display panel such as a liquid crystal display, the component is SiO _2, Al ₂ O _3, B ₂ O ₃ and RO (R is a metal element having a valence of 2 and magnesium, calcium, strontium and barium), and aluminum, magnesium, calcium, strontium and barium as the metal elements are the target elements.

In any case, the metal elements to be reduced in order not to lower the reliability (stability of the characteristics) of the transistors are sodium, aluminum, magnesium, calcium, strontium and barium, and even silicon and boron, which are other elements contained in the glass substrate, are the same. It is desirable to reduce the level to.

Since the first gate insulating film 436 is provided between the glass substrate 400, the second gate insulating film 402, and the oxide semiconductor film 403, the first metal element contained in the glass substrate 400 is formed. Diffusion to the two gate insulating film 402 and the oxide semiconductor film 403 can be prevented.

In addition, by providing a dense insulating film such as a silicon nitride film in the first gate insulating film 436, it is possible to prevent diffusion of movable ions such as sodium contained in the glass substrate 400 into the transistor 440. .

Since the diffusion of the first metal element contained in the glass substrate 400, which causes the deterioration or fluctuation of the electrical characteristics of the transistor 440, can be prevented, it is possible to give the transistor 440 stable electrical characteristics. Can be.

When these metal elements exist in the vicinity of the gate electrode layer, a defect is generated at the interface between the gate insulating film or the gate electrode layer and the gate insulating film, and the charge is trapped therein, which is considered to cause variation in the electrical characteristics of the transistor. For example, if a positive charge is trapped around the gate electrode layer, it is feared that the electrical characteristics of the transistor will change in the direction of normally on. In addition, when movable ions such as sodium are contained in the gate insulating film, the positive movable ions move to the interface between the gate insulating film and the oxide semiconductor film when a positive bias is applied to the gate electrode layer, so that the electrical characteristics of the transistor are normally It causes a fluctuation in the on direction. Therefore, in order to stabilize the electrical characteristics of the transistor, it is effective to prevent metal elements, which are thought to have such adverse effects, from invading from the glass substrate to the gate insulating film side.

Therefore, a highly reliable semiconductor device including the transistor 440 having stable electrical characteristics using the oxide semiconductor film 403 can be provided.

The oxide semiconductor used for the oxide semiconductor film 403 contains at least indium (In). It is particularly preferable to include In and zinc (Zn). In addition, it is preferable to have gallium (Ga) in addition to In and Zn as a stabilizer for reducing the variation of the electrical characteristics of the transistor using the oxide semiconductor film. Further, it is preferable to have tin (Sn) as a stabilizer. Further, it is preferable to have hafnium (Hf) as a stabilizer. Further, it is preferable to have aluminum (Al) as a stabilizer. Further, it is preferable to have zirconium (Zr) as a stabilizer.

In addition, as other stabilizers, lanthanides such as lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd) and terbium (Tb) Or any one or a plurality of dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), and lutetium (Lu).

For example, indium oxide, tin oxide, zinc oxide, In-Zn-based oxides, In-Mg-based oxides, In-Ga-based oxides, and In-Ga- oxides of ternary metals as oxide semiconductors. Zn oxide (also referred to as IGZO), In-Al-Zn oxide, In-Sn-Zn oxide, In-Hf-Zn oxide, In-La-Zn oxide, In-Ce-Zn oxide, In-Pr-Zn oxide, In-Nd-Zn oxide, In-Sm-Zn oxide, In-Eu-Zn oxide, In-Gd-Zn oxide, In-Tb-Zn oxide, In- Dy-Zn oxide, In-Ho-Zn oxide, In-Er-Zn oxide, In-Tm-Zn oxide, In-Yb-Zn oxide, In-Lu-Zn oxide, quaternary metal In-Sn-Ga-Zn oxides, In-Hf-Ga-Zn oxides, In-Al-Ga-Zn oxides, In-Sn-Al-Zn oxides, In-Sn-Hf-Zn oxides An oxide and an In-Hf-Al-Zn type oxide can be used.

In addition, an In-Ga-Zn type oxide means the oxide which has In, Ga, and Zn as a main component here, for example, and the ratio of In, Ga, and Zn is irrespective. Moreover, metallic elements other than In, Ga, and Zn may be contained.

As the oxide semiconductor, a material denoted by InMO ₃ (ZnO) _m (m> 0, and m is not an integer) may be used. In addition, M represents one metal element or a plurality of metal elements selected from Ga, Fe, Mn, and Co. As the oxide semiconductor, a material represented by In ₂ SnO ₅ (ZnO) _n (n> 0, where n is an integer) may be used.

For example, the atomic ratio is In: Ga: Zn = 1: 1: 1 (= 1/3: 1/3: 1/3), In: Ga: Zn = 2: 2: 1 (= 2/5: 2/5: 1/5), or In-Ga-Zn-based oxide having In: Ga: Zn = 3: 1: 2 (= 1/2: 1/6: 1/3) or having a composition near thereto Oxides can be used. Alternatively, the atomic ratio is In: Sn: Zn = 1: 1: 1 (= 1/3: 1/3: 1/3), In: Sn: Zn = 2: 1: 3 (= 1/3: 1 / 6: 1/2) or In: Sn: Zn = 2: 1: 5 (= 1/4: 1/8: 5/8) In-Sn-Zn-based oxide or an oxide having a composition adjacent thereto Do it.

However, the oxide semiconductor containing at least indium is not limited to the above-described one, and one having an appropriate composition may be used depending on the required semiconductor characteristics (mobility, threshold value, deviation, and the like). In addition, in order to obtain necessary semiconductor characteristics, it is preferable to appropriately set the carrier concentration, the impurity concentration, the defect density, the atomic ratio of the metal element and oxygen, the interatomic distance, the density, and the like.

For example, when In-Sn-Zn-based oxides are used, high mobility can be obtained relatively easily. However, even when In-Ga-Zn-based oxides are used, mobility can be improved by reducing the defect density in the bulk.

For example, the composition of the oxide whose atomic ratio of In, Ga, and Zn is In: Ga: Zn = a: b: c (a + b + c = 1) has the atomic ratio of In: Ga: Zn = A: B: C The vicinity of the composition of the oxide of (A + B + C = 1) indicates that a, b, and c satisfy (aA) ² + (bB) ² + (cC) ² ≤ r ² . r may be 0.05, for example. This also applies to other oxides.

The oxide semiconductor film 403 takes a state of single crystal, polycrystal (also called polycrystal), or amorphous.

Preferably, the oxide semiconductor film is a CA Axis-O (C Axis Aligned Crystalline Oxide Semiconductor) film.

The CAAC-OS film is neither a perfect single crystal nor a perfect amorphous. The CAAC-OS film is an oxide semiconductor film having a crystal-amorphous mixed phase structure having a crystal part in an amorphous phase. In addition, the crystal part is often the size that one side is contained in a cube of less than 100nm. In addition, on the observation by a transmission electron microscope (TEM), the boundary between the amorphous part and the crystal part included in the CAAC-OS film is not clear. In addition, on the observation by TEM, grain boundaries (also called grain boundaries) are not confirmed on the CAAC-OS film. Therefore, it can be said that the CAAC-OS film suppresses the decrease in electron mobility due to grain boundaries.

The crystal part included in the CAAC-OS film has a c-axis aligned in a direction parallel to the normal vector of the surface to be formed of the CAAC-OS film or the normal vector of the surface, and also has a triangular or hexagonal atomic arrangement as viewed from the direction perpendicular to the ab plane. And the metal atoms are arranged in layers, or the metal atoms and oxygen atoms are arranged in layers as viewed from the direction perpendicular to the c-axis. In addition, the directions of the a-axis and the b-axis may be different between the different crystal parts. In this specification, when simply described as "vertical", the range of 85 degrees or more and 95 degrees or less shall also be included. In addition, when simply described as "parallel", the range of -5 degrees or more and 5 degrees or less shall also be included.

In addition, the distribution of crystal parts in the CAAC-OS film may not be uniform. For example, in the case of crystal growth from the surface side of the oxide semiconductor film during the formation of the CAAC-OS film, the proportion of the crystal portion in the surface vicinity may be higher than in the vicinity of the formation surface. In addition, by adding an impurity to the CAAC-OS film, a crystal part may be amorphous in the impurity addition region.

Since the c-axis of the crystal part included in the CAAC-OS film is aligned in a direction parallel to the normal vector of the surface to be formed of the CAAC-OS film or the normal vector of the surface, the shape of the CAAC-OS film (the cross-sectional shape of the surface to be formed or Depending on the cross-sectional shape), they can face different directions. In addition, the c-axis direction of the crystal part becomes a direction parallel to the normal vector of the surface to be formed or the normal vector of the surface when the CAAC-OS film is formed. The crystal part is formed by film formation or by crystallization treatment such as heat treatment after film formation.

The transistor using the CAAC-OS film can reduce variations in electrical characteristics due to irradiation of visible or ultraviolet light. Thus, the transistor is highly reliable.

Further, a part of oxygen constituting the oxide semiconductor film may be substituted with nitrogen.

In addition, in oxide semiconductors having crystal parts such as CAAC-OS, defects in bulk can be further reduced, and mobility of the oxide semiconductor in an amorphous state can be obtained by increasing the flatness of the surface. In order to increase the flatness of the surface, it is preferable to form an oxide semiconductor on a flat surface, specifically, the average surface roughness Ra may be formed on the surface of 1 nm or less, preferably 0.3 nm or less, more preferably 0.1 nm or less. .

Ra is a three-dimensional extension of the arithmetic mean roughness defined in JIS B 0601: 2001 (ISO4287: 1997) to be applied to curved surfaces, and is defined as 'average of the absolute value of the deviation from the reference plane to the specified plane'. Can be expressed and is defined by the following equation.

[Formula 1]

Here, the designated surface is a surface to be subjected to roughness measurement, and coordinates (x ₁ , y ₁ , f (x ₁ , y ₁ )), (x ₁ , y ₂ , f (x ₁ , y ₂ )), (x ₂ , y ₁ , f (x ₂ , y ₁ )), (x ₂ , y ₂ , f (x ₂ , y ₂ )) to form a rectangular area formed by connecting four points, and project the specified surface onto the xy plane. The area of one rectangle is S ₀ , and the height of the reference plane (average height of the designated plane) is Z ₀ . Ra can be measured using Atomic Force Microscope (AFM).

However, since the transistor 440 described in the present embodiment has a lower gate type, a glass substrate 400, a gate electrode layer 401, and a second gate insulating film 402 exist below the oxide semiconductor film. Therefore, in order to obtain the flat surface, after the gate electrode layer 401 and the second gate insulating film 402 are formed, a planarization process such as a CMP process may be performed.

The film thickness of the oxide semiconductor film 403 is 1 nm or more and 30 nm or less (preferably 5 nm or more and 10 nm or less), and sputtering method, MBE (Molecular Beam Epitaxy) method, CVD method, pulse laser deposition method, ALD (Atomic Layer) Deposition) etc. can be used suitably. Further, the oxide semiconductor film 403 may be formed using a sputtering apparatus that forms a film in a state where a plurality of substrate surfaces are set substantially perpendicular to the sputtering target surface.

A CAAC-OS film is formed by the sputtering method using the target for oxide semiconductor sputtering which is polycrystal, for example. When ions collide with the sputtering target, crystal regions included in the sputtering target are cleaved from the ab plane, and flat or pellet-shaped sputtering particles having a plane parallel to the ab plane are peeled off. There is a case. In this case, a CAAC-OS film can be formed by reaching the board | substrate with the said flat sputtering particle | grains maintaining a crystalline state.

In addition, the following conditions are preferably applied to form the CAAC-OS film.

By reducing the incorporation of impurities in the formation of the film, it is possible to suppress the disturbance of the crystal state due to the impurities. For example, the impurity concentration (hydrogen, water, carbon dioxide, nitrogen, etc.) present in the deposition chamber may be reduced. Moreover, what is necessary is just to reduce the impurity concentration in film-forming gas. Specifically, a film forming gas having a dew point of −80 ° C. or lower, preferably −100 ° C. or lower is used.

Furthermore, by raising the substrate heating temperature at the time of forming the film, migration of sputtered particles occurs after reaching the substrate. Specifically, a film is formed at a substrate heating temperature of 100 ° C. or higher and 740 ° C. or lower, preferably 200 ° C. or higher and 500 ° C. or lower. By raising the substrate heating temperature at the time of forming the film, when the flat sputtered particles reach the substrate, migration occurs on the substrate, and the flat surface of the sputtered particles adheres to the substrate.

In addition, it is preferable to reduce the damage due to the plasma received when forming the film by increasing the oxygen ratio in the deposition gas and optimizing the electric power. The oxygen ratio in the film forming gas is 30 vol.% Or more, preferably 100 vol.%.

As an example of the sputtering target, an In—Ga—Zn—O compound target is described below.

In-Ga-Zn-O compound which is polycrystalline by mixing InO _X powder, GaO _Y powder, and ZnO _Z powder in a predetermined mol ratio, and performing heat treatment at a temperature of 1000 ° C. to 1500 ° C. Create a target. In addition, X, Y, and Z are arbitrary integers. Herein, the predetermined molar number ratio is, for example, InO _X powder, GaO _Y powder, and ZnO _Z powder, for example, 2: 2: 1, 8: 4: 3, 3: 1: 1, 1: 1: 1, 4 : 2: 3, or 3: 1: 2. In addition, what is necessary is just to change suitably the kind of powder and the mol number ratio which mix these with the target for sputtering to produce.

2A to 2E illustrate an example of a method of manufacturing a semiconductor device having a transistor 440.

There is no particular limitation as to the substrate that can be used as the glass substrate 400, but it is necessary that the glass substrate has at least a degree of heat resistance that can withstand the heat treatment performed later. For example, barium borosilicate glass, aluminoborosilicate glass, etc. can be used.

The glass substrate 400 may be heated. For example, the heat treatment may be performed at 650 ° C. for 1 minute to 5 minutes by a GRTA (Gas Rapid Thermal Anneal) apparatus which is heated using a hot gas. As the hot gas used for GRTA, an inert gas such as rare gas such as argon or an inert gas such as nitrogen that does not react with the object to be processed by heat treatment is used. Moreover, you may heat-process at 500 degreeC for 30 minutes-1 hour with an electric furnace.

Next, a conductive film is formed on the glass substrate 400, and the conductive film is etched to form a gate electrode layer 401 (see FIG. 2A). For etching the conductive film, either dry etching or wet etching may be used, or both may be used.

The gate electrode layer 401 can be formed using a metal material such as molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, scandium, or an alloy material containing these as a main material. As the gate electrode layer 401, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus, or a silicide film such as nickel silicide may be used. The gate electrode layer 401 may have a single layer structure or a laminated structure.

The material of the gate electrode layer 401 is indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, and oxidation Electroconductive materials, such as indium zinc oxide and indium tin oxide which added the silicon oxide, can also be applied. Moreover, it can also be set as the laminated structure of the said electroconductive material and the said metal material.

Further, as the gate electrode layer 401, a metal oxide film containing nitrogen, specifically, an In-Ga-Zn-O film containing nitrogen, an In-Sn-O film containing nitrogen, or containing nitrogen In-Ga-O film, In-Zn-O film containing nitrogen, Sn-O film containing nitrogen, In-O film containing nitrogen, or metal nitride film (InN, SnN, etc.) can be used. Can be. These films have a work function of 5 eV (electron volts), preferably 5.5 eV (electron volts) or more, and when used as a gate electrode layer, the threshold voltage of the electrical characteristics of the transistor can be made positive, so-called normal off switching. The element can be realized.

In this embodiment, a tungsten film having a thickness of 100 nm is formed by the sputtering method.

In addition, after the gate electrode layer 401 is formed, heat treatment may be performed on the glass substrate 400 and the gate electrode layer 401. For example, the GRTA apparatus may perform heat treatment at 650 ° C. for 1 minute to 5 minutes. Moreover, you may perform heat processing for 30 minutes-1 hour at 500 degreeC by an electric furnace.

Next, a first gate insulating film 436 is provided to cover the gate electrode layer 401 (see FIG. 2B).

As the first gate insulating film 436, a nitride insulating film formed by plasma CVD, sputtering, or the like can be used. For example, a silicon nitride film, a silicon nitride oxide film, etc. are mentioned. The first gate insulating film 436 may be either a single layer structure or a stacked structure.

In addition, as the first gate insulating film 436 to prevent diffusion of impurities from the glass substrate 400, titanium (Ti), molybdenum (Mo), tungsten (W), hafnium (Hf), tantalum (Ta), Metal oxide insulating films containing any one or more metal elements selected from lanthanum (La), zirconium (Zr), nickel (Ni), magnesium (Mg), barium (Ba), and aluminum (Al) (e.g., , An aluminum oxide film, an aluminum oxynitride film, a hafnium oxide film, a magnesium oxide film, a zirconium oxide film, a lanthanum oxide film, a barium oxide film), or a metal nitride insulating film (aluminum nitride film, oxynitride) containing the above-described metal element Aluminum film) can be used. A gallium oxide film, an In—Zr—Zn oxide film, an In—Fe—Zn oxide film, an In—Ce—Zn oxide film, or the like may also be used for the first gate insulating film 436.

In this embodiment, as the first gate insulating film 436, a silicon nitride film having a thickness of 30 nm formed by the plasma CVD method is used.

Next, a second gate insulating film 402 is formed over the first gate insulating film 436.

Since the gate electrode layer 401 is covered with the first gate insulating film 436, the first metal element contained in the glass substrate 400 adheres to the surface of the gate electrode layer 401 in the etching process of forming the gate electrode layer 401. Even if it is, the diffusion to the second gate insulating film 402 can be prevented.

The second gate insulating film 402 has a film thickness of 1 nm or more and 20 nm or less, and can be formed using a sputtering method, an MBE method, a CVD method, a pulse laser deposition method, an ALD method, or the like as appropriate. Further, the second gate insulating film 402 may be formed using a sputtering apparatus that forms a film in a state where a plurality of substrate surfaces are set substantially perpendicular to the sputtering target surface.

As the material of the second gate insulating film 402, a silicon oxide film, a gallium oxide film, an aluminum oxide film, a silicon nitride film, a silicon oxynitride film, an aluminum oxynitride film, or a silicon nitride oxide film can be formed.

As the material of the second gate insulating film 402, a hafnium oxide film, an yttrium oxide film, a hafnium silicate film (HfSi _x O _y (x> 0, y> 0)), and a hafnium silicate film (HfSiO _x N) to which nitrogen was added _The gate leakage current can be reduced by using high-k materials such as _y (x> 0, y> 0)), hafnium aluminate films (HfAl _x O _y (x> 0, y> 0)), and lanthanum oxide films. Can be. In addition, the second gate insulating film 402 may have either a single layer structure or a stacked structure.

The second gate insulating film 402 preferably contains oxygen in a portion in contact with the oxide semiconductor film 403. In particular, the second gate insulating film 402 preferably contains oxygen in an amount exceeding at least the stoichiometric composition in the film (in the bulk). For example, when the silicon oxide film is used as the second gate insulating film 402. Is set to SiO _{2 + α} (but α> 0).

A second gate insulating film 402 containing a large amount (or excess) of oxygen, which is a source of oxygen, is formed in contact with the oxide semiconductor film 403 to form an oxide semiconductor film 403 from the second gate insulating film 402. Oxygen can be supplied. Oxygen may be supplied to the oxide semiconductor film 403 by heat treatment in a state where at least a portion of the oxide semiconductor film 403 and the second gate insulating film 402 are in contact with each other.

By supplying oxygen to the oxide semiconductor film 403, oxygen vacancies in the film can be preserved. In addition, it is preferable to form the second gate insulating film 402 in consideration of the size of the transistor to be manufactured and the step coverage of the second gate insulating film 402.

In this embodiment, a silicon oxynitride film having a thickness of 200 nm is formed by using a high density plasma CVD method.

After the second gate insulating film 402 is formed, heat treatment may be performed on the glass substrate 400, the gate electrode layer 401, the first gate insulating film 436, and the second gate insulating film 402. For example, the GRTA apparatus may perform heat treatment at 650 ° C. for 1 minute to 5 minutes. Moreover, you may perform heat processing for 30 minutes-1 hour at 500 degreeC by an electric furnace.

Next, an oxide semiconductor film 403 is formed over the second gate insulating film 402 (see FIG. 2C).

In the formation process of the oxide semiconductor film 403, in order to prevent hydrogen or water from being contained in the oxide semiconductor film 403 as much as possible, in a preheating chamber of the sputtering apparatus as a process before the oxide semiconductor film 403 is formed. By preheating the substrate on which the second gate insulating film 402 is formed, it is preferable that the dopant, such as hydrogen or moisture, adsorbed on the substrate and the second gate insulating film 402 is removed and exhausted. In addition, the exhaust means provided to the preheating chamber is preferably a cryo pump.

The planarization process may be performed on the region formed by the oxide semiconductor film 403 in contact with the second gate insulating film 402. Although it does not specifically limit as a planarization process, Polishing process (for example, chemical mechanical polishing (CMP)), dry etching process, and plasma process can be used.

As the plasma treatment, for example, reverse sputtering that introduces argon gas to generate plasma can be performed. Reverse sputtering is a method of modifying a surface by applying a voltage to the substrate using an RF power source under an argon atmosphere to form a plasma near the substrate. In addition, nitrogen, helium, oxygen, or the like may be used instead of the argon atmosphere. When reverse sputtering is performed, the powdery substance (also called particles or dust) adhering to the surface of the second gate insulating layer 402 may be removed.

As the planarization treatment, a plurality of polishing treatments, dry etching treatments, and plasma treatments may be performed, or a combination thereof may be performed. In addition, when performing a combination of processes, the process order is not specifically limited, either, According to the uneven | corrugated state of the surface of the 2nd gate insulating film 402, it can set suitably.

In addition, the oxide semiconductor film 403 is formed under a condition that contains a large amount of oxygen during film formation (for example, a film is formed by a sputtering method in an atmosphere of 100% oxygen) to contain a large amount of oxygen (preferably Is preferably a film containing a region in which the oxygen content is greater than the stoichiometric composition of the oxide semiconductor in the crystalline state.

In this embodiment, an In—Ga—Zn based oxide film (IGZO film) having a thickness of 35 nm is formed by the sputtering method using a sputtering apparatus having an AC power supply device as the oxide semiconductor film 403. In the present embodiment, an In—Ga—Zn-based oxide target having an atomic ratio of In: Ga: Zn = 1: 1: 1 (= 1/3: 1/3: 1/3) is used. In addition, film-forming conditions are made into oxygen and argon atmosphere (oxygen flow rate ratio 50%), a pressure of 0.6 Pa, a power supply of 5 kW, and a substrate temperature of 170 ° C. The film formation rate under these film formation conditions is 16 nm / min.

As the sputtering gas used to form the oxide semiconductor film 403, it is preferable to use a high purity gas from which impurities such as hydrogen, water, hydroxyl groups, or hydrides are removed.

The substrate is held in the deposition chamber maintained at a reduced pressure. The sputtering gas from which hydrogen and moisture have been removed is introduced while removing the moisture remaining in the film formation chamber, and the oxide semiconductor film 403 is formed on the glass substrate 400 using the target. In order to remove the residual moisture in the film formation chamber, it is preferable to use an adsorption type vacuum pump, for example, a cryopump, an ion pump, or a titanium servation pump. As the exhaust means, a cold trap may be added to the turbomolecular pump. The film formation chamber evacuated using a cryopump is formed by exhausting a compound containing a hydrogen atom such as a hydrogen atom or water (H ₂ O) (more preferably, a compound containing a carbon atom), and the like. The concentration of impurities contained in the oxide semiconductor film 403 formed in the chamber can be reduced.

In addition, it is preferable to form the second gate insulating film 402 and the oxide semiconductor film 403 continuously without exposing the second gate insulating film 402 to the atmosphere. If the second gate insulating film 402 and the oxide semiconductor film 403 are continuously formed without exposing the second gate insulating film 402 to the atmosphere, impurities such as hydrogen and moisture are adsorbed onto the surface of the second gate insulating film 402. Can be prevented.

The oxide semiconductor film 403 can be formed by processing a film-shaped oxide semiconductor film into an island-shaped oxide semiconductor film by a photolithography process.

Further, a resist mask for forming the island-shaped oxide semiconductor film 403 may be formed by the inkjet method. When the resist mask is formed by the inkjet method, the photomask is not used, so that the manufacturing cost can be reduced.

The etching of the oxide semiconductor film may be either dry etching or wet etching, or both may be used. For example, as an etching liquid used for wet etching of an oxide semiconductor film, the solution etc. which mixed phosphoric acid, acetic acid, and nitric acid can be used. Further, ITO-07N (manufactured by KANTO CHEMICAL Co., Inc.) may be used. Further, the etching may be performed by dry etching called an ICP (Inductively Coupled Plasma) etching method.

Further, a heat treatment for removing (dehydrating or dehydrogenating) hydrogen (including water and hydroxyl groups) contained in the oxide semiconductor film 403 in excess may be performed. The temperature of heat processing shall be 300 degreeC or more and 700 degrees C or less, or less than the strain point of a board | substrate. The heat treatment can be carried out under reduced pressure or under a nitrogen atmosphere.

In addition, when using a crystalline oxide semiconductor film as the oxide semiconductor film 403, heat treatment for crystallization may be performed.

In this embodiment, a substrate is introduced into an electric furnace which is one of the heat treatment apparatuses, and the oxide semiconductor film 403 is subjected to heat treatment for 1 hour at 450 ° C. under nitrogen atmosphere and 450 ° C. under nitrogen and oxygen atmosphere for 1 hour. Heat treatment is carried out.

In addition, the heat processing apparatus is not limited to an electric furnace, You may use the apparatus which heats a to-be-processed object by heat conduction or heat radiation from a heat generating body, such as a resistance heating element. For example, a Rapid Thermal Anneal (RTA) device such as a Gas Rapid Thermal Anneal (GRTA) device or a Lamp Rapid Thermal Anneal (LRTA) device may be used. The LRTA apparatus is an apparatus for heating a target object by radiation of light (electromagnetic waves) emitted from lamps such as halogen lamps, metal halide lamps, xenon arc lamps, carbon arc lamps, high pressure sodium lamps, and high pressure mercury lamps. GRTA apparatus is a apparatus which performs heat processing using hot gas. As the hot gas, a rare gas such as argon or an inert gas that does not react with the object by heat treatment such as nitrogen is used.

For example, as a heat treatment, a substrate may be placed in an inert gas heated to a high temperature of 650 ° C to 700 ° C, heated for a few minutes, and then GRTA may be taken out of the inert gas.

Moreover, in heat processing, it is preferable that nitrogen, or rare gases, such as helium, neon, argon, do not contain water, hydrogen, etc. Nitrogen, or rare gas such as helium, neon, argon, or the like introduced into the heat treatment apparatus to a purity of 6N (99.9999%) or more, preferably 7N (99.99999%) or more (i.e., an impurity concentration of 1 ppm or less, ppm or less).

In addition, after the oxide semiconductor film 403 is heated by heat treatment, high purity oxygen gas, high purity dinitrogen monoxide gas, or ultra-dry air (CRDS (cavity ring down laser spectroscopy)) is heated in the same furnace. 20 ppm (-55 degreeC in conversion of dew point) or less, Preferably it is 1 ppm or less, More preferably, 10 ppm or less of air may be introduced. It is preferable that water, hydrogen, etc. are not contained in oxygen gas or dinitrogen monoxide gas. Alternatively, the purity of the oxygen gas or dinitrogen monoxide gas introduced into the heat treatment apparatus is 6N or more, preferably 7N or more (that is, the impurity concentration in the oxygen gas or the dinitrogen monoxide gas is 1 ppm or less, preferably 0.1 ppm or less). desirable. The oxide semiconductor film 403 is made of high purity by supplying oxygen, which is a main component material constituting the oxide semiconductor, simultaneously reduced by an exclusion process using a dehydration or dehydrogenation treatment due to the action of oxygen gas or dinitrogen monoxide gas. Fire and type I (intrinsic).

The timing for performing the heat treatment for dehydration or dehydrogenation may be at any timing after the formation of the oxide semiconductor film in the form of a film or after the formation of the island-shaped oxide semiconductor film 403.

In addition, the heat processing for dehydration or dehydrogenation may be performed in multiple times, and may also combine with other heat processing.

When the heat treatment for dehydration or dehydrogenation is performed in a state where the oxide semiconductor film having a film shape before being processed into an island shape as the oxide semiconductor film 403 covers the second gate insulating film 402, the second gate insulating film 402 It is preferable because the oxygen contained in can be prevented from being released by heat treatment.

In addition, oxygen (containing at least one of oxygen radicals, oxygen atoms, and oxygen ions) may be introduced into the oxide semiconductor film 403 subjected to the dehydration or dehydrogenation treatment to supply oxygen into the film.

In addition, there is a fear that oxygen, which is a main component material constituting the oxide semiconductor, is simultaneously released and reduced by dehydration or dehydrogenation treatment. In the oxide semiconductor film, an oxygen deficiency exists in the portion where oxygen is released, and a donor level that causes variation in electrical characteristics of the transistor occurs due to the oxygen deficiency.

Therefore, it is preferable to supply oxygen (containing at least one of oxygen radicals, oxygen atoms, and oxygen ions) to the oxide semiconductor film subjected to the dehydration or dehydrogenation treatment. By supplying oxygen to the oxide semiconductor film, oxygen vacancies in the film can be preserved.

By introducing oxygen into the oxide semiconductor film 403 subjected to the dehydration or dehydrogenation process and supplying oxygen into the film, the oxide semiconductor film 403 can be made highly purified and made I-type (intrinsic). The transistor having the highly purified and I-type (intrinsic) oxide semiconductor film 403 is electrically stable because variations in electrical characteristics are suppressed.

As the method for introducing oxygen, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, a plasma treatment, or the like can be used.

When oxygen is introduced into the oxide semiconductor film 403, the oxygen introduction step may be introduced directly into the oxide semiconductor film 403, or may be introduced into the oxide semiconductor film 403 through another film such as the insulating film 407. In the case where oxygen is introduced through another film, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, or the like may be used. In the case where oxygen is directly introduced into the exposed oxide semiconductor film 403, a plasma treatment or the like may also be used. .

The introduction of oxygen into the oxide semiconductor film 403 is preferably performed after the dehydration or dehydrogenation treatment, but is not particularly limited. In addition, the introduction of oxygen into the oxide semiconductor film 403 subjected to the dehydration or dehydrogenation treatment may be performed a plurality of times.

Preferably, the oxide semiconductor film provided to the transistor may be a film including a region in which the oxygen content is excessive compared to the stoichiometric composition of the oxide semiconductor in the crystalline state. In this case, the content of oxygen is such that it exceeds the stoichiometric composition of the oxide semiconductor. Alternatively, the content of oxygen is such that it exceeds the amount of oxygen in the case of a single crystal. Oxygen may exist between the lattice of an oxide semiconductor.

By removing hydrogen or water from the oxide semiconductor to make it as high as possible in order not to contain impurities, and supplying oxygen to preserve oxygen deficiency, it can be made into type I (intrinsic) oxide semiconductor or oxide semiconductor very close to type I (intrinsic). have. By doing in this way, the Fermi level Ef of an oxide semiconductor can be made to the same level as the intrinsic Fermi level Ei. Thus, by using the semiconductor film and the oxide in the transistors it is possible to reduce the deviation, the shift of the threshold voltage (ΔV _th) of the threshold voltage (V _th) of the transistor due to oxygen deficiency.

Next, the gate electrode layer 401, the first gate insulating film 436, the second gate insulating film 402, and the source electrode layer and the drain electrode layer (the wiring formed of the same layer as this) are included on the oxide semiconductor film 403. To form a conductive film.

As the conductive film, a material that can withstand the heat treatment to be performed later is used. As the conductive film used for the source electrode layer and the drain electrode layer, for example, a metal film containing an element selected from Al, Cr, Cu, Ta, Ti, Mo, W, or a metal nitride film containing the above-described element as a component (titanium nitride) Film, molybdenum nitride film, tungsten nitride film) and the like. Further, a high melting point metal film such as Ti, Mo, W, or a metal nitride film thereof (titanium nitride film, molybdenum nitride film, tungsten nitride film) is laminated on one or both of the bottom or top of the metal film such as Al and Cu. It is good also as a structure made. The conductive film used for the source electrode layer and the drain electrode layer may be formed of a conductive metal oxide. Examples of the conductive metal oxide include indium oxide (In ₂ O ₃ ), tin oxide (SnO ₂ ), zinc oxide (ZnO), indium tin oxide (In ₂ O ₃ -SnO ₂ ), and indium zinc oxide (In ₂ O ₃ − ZnO) or those in which silicon oxide is contained in these metal oxide materials can be used.

A resist mask is formed on the conductive film by a photolithography process and is selectively etched to form a source electrode layer 405a and a drain electrode layer 405b (see FIG. 2D). After the source electrode layer 405a and the drain electrode layer 405b are formed, the resist mask is removed.

Ultraviolet rays, KrF laser light, ArF laser light, or the like may be used for exposure when forming a resist mask. The channel length L of the transistor 440 formed later is determined according to the gap width between the lower end of the source electrode layer 405a and the lower end of the drain electrode layer 405b adjacent to each other on the oxide semiconductor film 403. In addition, when performing exposure of channel length L = 25 nm or less, exposure at the time of forming a resist mask may be performed using the ultra-ultraviolet (Extreme Ultraviolet) which is very short in several nm-tens of nm, for example. Exposure by ultra-ultraviolet rays has high resolution and a large depth of focus. Therefore, the channel length L of the transistor formed later can be 10 nm or more and 1000 nm or less, and the operation speed of a circuit can be speeded up.

In addition, in order to reduce the number of photomasks used in the photolithography step and the number of steps, the etching step may be performed using a resist mask formed by a multi-gradation mask that is an exposure mask whose transmitted light has a plurality of intensities. The resist mask formed by using the multi gradation mask becomes a shape having a plurality of film thicknesses, and the shape can be further modified by performing etching, so that the resist mask can be used in a plurality of etching steps for processing into different patterns. Therefore, the resist mask corresponding to at least two or more types of different patterns can be formed with one multi-tone mask. Therefore, since the number of exposure masks can be reduced and the corresponding photolithography process can also be reduced, the process can be simplified.

In the present embodiment, a gas containing chlorine is used for etching the conductive film, for example, a gas containing chlorine (Cl ₂ ), boron trichloride (BCl ₃ ), silicon tetrachloride (SiCl ₄ ), carbon tetrachloride (CCl ₄ ), or the like. Can be used. In addition, a gas containing fluorine such as carbon tetrafluoride (CF ₄ ), sulfur hexafluoride (SF ₆ ), nitrogen trifluoride (NF ₃ ), trifluoromethane (CHF ₃ ), or the like may be used. Can be. Moreover, the gas etc. which rare gas, such as helium (He) and argon (Ar), were added to these gases, can be used.

As the etching method, a parallel plate-type reactive ion etching (RIE) method or an inductively coupled plasma (ICP) etching method can be used. Etching conditions (the amount of power applied to the coil type electrode, the amount of power applied to the electrode on the substrate side, the electrode temperature on the substrate side, etc.) are appropriately adjusted so as to be etched into a desired processing shape.

In the present embodiment, a laminate of a titanium film with a thickness of 100 nm, an aluminum film with a thickness of 400 nm, and a titanium film with a thickness of 100 nm formed by the sputtering method is used as the conductive film. As the etching of the conductive film, a stack of a titanium film, an aluminum film, and a titanium film is etched by a dry etching method to form a source electrode layer 405a and a drain electrode layer 405b.

In the present embodiment, two layers of the titanium film and the aluminum film are etched under the first etching condition, and then the remaining titanium film single layer is removed under the second etching condition. Furthermore, the first etching conditions, the etching gas and the _{(BCl 3: 150sccm: Cl 2} = 750sccm) to use, the bias power 1500W, ICP 0W power Power, pressure was 2.0Pa. As the second etching condition, an etching gas (BCl ₃ : Cl ₂ = 700 sccm: 100 sccm) is used, the bias power is 750 W, the ICP power supply power is 0 W, and the pressure is 2.0 Pa.

In addition, it is preferable to optimize the etching conditions so that the oxide semiconductor film 403 is not etched and parted during the etching process of the conductive film. However, it is difficult to obtain a condition in which only the conductive film is etched and the oxide semiconductor film 403 is not etched at all. Only a part of the oxide semiconductor film 403 is etched at the time of etching the conductive film, so that the oxide has a groove portion (concave portion). It may also be a semiconductor film.

Through the above-described process, the transistor 440 of this embodiment is manufactured.

In this embodiment, an insulating film 407 in contact with the oxide semiconductor film 403 is formed on the source electrode layer 405a and the drain electrode layer 405b (see FIG. 2E).

The insulating film 407 has a film thickness of at least 1 nm or more, and can be formed by appropriately using a method in which impurities such as water and hydrogen are not mixed in the insulating film 407 such as sputtering. When hydrogen is contained in the insulating film 407, the hydrogen penetrates into the oxide semiconductor film 403, or oxygen in the oxide semiconductor film is extracted due to hydrogen, and the back channel of the oxide semiconductor film 403 becomes low resistance ( N-type) to form a parasitic channel. Therefore, in order to make the insulating film 407 a film which does not contain hydrogen as much as possible, it is important not to use hydrogen in the film formation method.

The insulating film 407 is typically a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, an aluminum oxynitride film, a hafnium oxide film, a gallium oxide film, a silicon nitride film, an aluminum nitride film, a silicon nitride oxide film, or an aluminum nitride oxide film. A single layer or a stack of inorganic insulating films such as a film can be used.

When the heating process is performed as the dehydration or dehydrogenation treatment, it is preferable to supply oxygen to the oxide semiconductor film 403. By supplying oxygen to the oxide semiconductor film 403, oxygen vacancies in the film can be preserved.

In this embodiment, since oxygen is supplied to the oxide semiconductor film 403 using the insulating film 407 as a source, an oxide insulating film containing oxygen (for example, a silicon oxide film or a silicon oxynitride film) is used as the insulating film 407. An example of use is given. In the case where the insulating film 407 is a source of oxygen, the insulating film 407 is a film containing a large amount (excess) of oxygen (preferably a region having an excessive oxygen content as compared with the stoichiometric composition in the crystalline state). Contained film) can be suitably functioned as a source of oxygen.

In this embodiment, a silicon oxide film having a thickness of 300 nm is formed as the insulating film 407 by the sputtering method. The substrate temperature at the time of forming a film may be room temperature or more and 300 degrees C or less, and is 100 degreeC in this embodiment. The formation of the silicon oxide film by the sputtering method can be performed in a rare gas (typically argon) atmosphere, in an oxygen atmosphere, or in a mixed atmosphere of the rare gas and oxygen. Moreover, a silicon oxide target or a silicon target can be used as a target. For example, a silicon oxide film can be formed by sputtering in an atmosphere containing oxygen using a silicon target.

As in the case of forming the oxide semiconductor film 403, in order to remove residual moisture in the film formation chamber of the insulating film 407, it is preferable to use an adsorption type vacuum pump (such as a cryo pump). If the insulating film 407 is formed in the film formation chamber exhausted using the cryopump, the concentration of impurities contained in the insulating film 407 can be reduced. As the exhaust means for removing residual water in the film formation chamber of the insulating film 407, a cold trap may be attached to the turbomolecular pump.

As the sputtering gas used for forming the insulating film 407, a high purity gas from which impurities such as hydrogen and water are removed is preferable.

Next, a heating process is performed on the oxide semiconductor film 403 with a part (channel formation region) in contact with the insulating film 407.

The temperature of a heating process may be 250 degreeC or more and 700 degrees C or less, 400 degreeC or more and 700 degrees C or less, or less than the strain point of a board | substrate. For example, a substrate is introduced into an electric furnace, which is one of heat treatment apparatuses, and a heating process is performed at 250 ° C. for 1 hour on an oxide semiconductor film under a nitrogen atmosphere.

This heating process can use the heating method and heating apparatus similar to the heating process which performs a dehydration or a dehydrogenation process.

The heating step is 20 ppm or less (-55 ° C in terms of dew point) when the water content is measured under a reduced pressure or measured using a dew point meter of nitrogen, oxygen, or ultra-dry air (CRDS (cavity ring down laser spectroscopy) method, preferably 1 ppm or less, preferably 10 ppm or less air) or a rare gas (argon, helium, etc.), but may be performed in an atmosphere such as nitrogen, oxygen, ultra-dry air, or a rare gas such that water, hydrogen, etc. are not included. It is preferable. Further, the purity of nitrogen, oxygen, or rare gas introduced into the heat treatment apparatus is 6N (99.9999%) or more, preferably 7N (99.99999%) or more (that is, impurity concentration is 1 ppm or less, preferably 0.1 ppm or less). It is preferable.

In addition, since the heating step is performed while the oxide semiconductor film 403 and the insulating film 407 containing oxygen are in contact with each other, the main component material constituting the oxide semiconductor film 403 simultaneously reduced by the removal of impurities. Oxygen, which is one of them, can be supplied from the insulating film 407 containing oxygen to the oxide semiconductor film 403.

In addition, a highly dense inorganic insulating film may be further provided over the insulating film 407. For example, an aluminum oxide film is formed on the insulating film 407 by sputtering. By making the aluminum oxide film high density (film density of 3.2 g / cm ³ or more, preferably 3.6 g / cm ³ or more), stable electrical characteristics can be imparted to the transistor 440. The film density can be measured by Rutherford Backscattering Spectrometry (RBS) or X-ray Reflection (XRR).

The aluminum oxide film that can be used as the insulating film 407 provided over the transistor 440 has a high effect (block effect) of blocking the film from passing through both impurities such as hydrogen, moisture, and oxygen.

Accordingly, in the aluminum oxide film, oxygen, which is a main component material constituting the oxide semiconductor, or impurities such as hydrogen and moisture, which are factors of variation in electrical characteristics, are formed during or after the fabrication process. It functions as a protective film which prevents it from being emitted from.

In addition, a planarization insulating film may be formed to reduce surface irregularities caused by the transistor 440. As the planarization insulating film, organic materials such as polyimide resin, acrylic resin and benzocyclobutene resin can be used. In addition to the above organic materials, low dielectric constant materials (low-k materials) and the like can be used. The planarization insulating film may be formed by stacking a plurality of insulating films formed of these materials.

For example, an acrylic resin film having a thickness of 1500 nm may be formed as the planarization insulating film. The acrylic resin film may be formed by coating an acrylic resin on the transistor 440 using a coating method and then firing (for example, 1 hour at 250 ° C. under a nitrogen atmosphere).

After the planarization insulating film is formed, heat treatment may be performed. For example, heat treatment is performed at 250 ° C. for 1 hour under a nitrogen atmosphere.

After the transistor 440 is formed in this manner, heat treatment may be performed. In addition, you may perform heat processing in multiple times.

Since the first gate insulating film 436 is provided between the glass substrate 400, the second gate insulating film 402, and the oxide semiconductor film 403, the first metal element contained in the glass substrate 400 is formed. Diffusion to the two gate insulating film 402 and the oxide semiconductor film 403 can be prevented.

Since it is possible to prevent diffusion of the first metal element contained in the glass substrate 400 which causes deterioration or fluctuation of the electrical characteristics of the transistor 440, stable electrical characteristics can be given to the transistor 440. have.

Therefore, a highly reliable semiconductor device including the transistor 440 having stable electrical characteristics using the oxide semiconductor film 403 can be provided. In addition, high productivity can be achieved by manufacturing a highly reliable semiconductor device with high yield.

(Embodiment 2)

In this embodiment, another embodiment of the semiconductor device and the manufacturing method of the semiconductor device will be described with reference to FIGS. 3A and 3B. Portions and processes having the same or the same function as the above-described embodiment can be performed in the same manner as the above-described embodiment, and repeated description is omitted. In addition, detailed description of the same part is abbreviate | omitted.

The transistor 430 shown in Figs. 3A and 3B is one of a lower gate structure called a channel protection type (also called a channel stop type), and is an example of a transistor also called an inverted staggered transistor. FIG. 3A is a plan view, and a cross section of a portion cut along the dashed-dotted line X1-Y1 shown in FIG. 3A corresponds to FIG. 3B.

As shown in FIG. 3B, which is a cross-sectional view of the transistor 430 in the channel length direction, the semiconductor device including the transistor 430 may be formed to cover the gate electrode layer 401 and the gate electrode layer 401 on the glass substrate 400. A first gate insulating film 436 is provided, and has a second gate insulating film 402, an oxide semiconductor film 403, a source electrode layer 405a, and a drain electrode layer 405b over the first gate insulating film 436. In addition, the insulating layer 413 is in contact with the oxide semiconductor film 403.

At least a first gate insulating film 436 and a second gate insulating film 402 are provided between the gate electrode layer 401 and the oxide semiconductor film 403. The composition of the first gate insulating film 436 provided on the gate electrode layer 401 side and the composition of the second gate insulating film 402 provided on the oxide semiconductor film 403 side are different. Further, at the interface between the first gate insulating film 436 and the second gate insulating film 402, the concentration of the first metal element contained in the glass substrate 400 is 5 × 10 ¹⁸ atoms / cm ³ or less (preferably Is 1 × 10 ¹⁸ atoms / cm ³ or less).

A thin film nitride insulating film may be used for the first gate insulating film 436. For example, a silicon nitride film, a silicon nitride oxide film, etc. are mentioned. The first gate insulating film 436 may be either a single layer structure or a stacked structure. The film thickness of the first gate insulating film 436 can be thin, and can be 30 nm or more and 50 nm or less.

In order to reduce the reliability (stability of the characteristic) of the transistor 430, the metal elements to be reduced are sodium, aluminum, magnesium, calcium, strontium, and barium, and further, silicon, which is another element contained in the glass substrate 400. It is preferable to reduce boron and boron to the same level.

The insulating layer 413 in contact with the oxide semiconductor film 403 is provided over the channel formation region of the oxide semiconductor film 403 overlapping with the gate electrode layer 401 and functions as a channel protective film.

The cross-sectional shape of the insulating layer 413 superimposed on the channel formation region, specifically, the cross-sectional shape (taper angle, film thickness, etc.) of the end portion as shown below, thereby providing the end of the drain electrode layer 405b. It is possible to alleviate the electric field concentration that may be generated in the vicinity, and suppress deterioration in switching characteristics of the transistor 430.

Specifically, the cross-sectional shape of the insulating layer 413 overlapping the channel formation region is trapezoidal or triangular, and the taper angle of the lower end of the cross-sectional shape is 60 ° or less, preferably 45 ° or less, more preferably 30 °. Let it be as follows. By setting the angle in such a range, when the high gate voltage is applied to the gate electrode layer 401, the electric field concentration that may be generated near the end of the drain electrode layer 405b can be alleviated.

Further, the film thickness of the insulating layer 413 overlying the channel formation region is 0.3 μm or less, preferably 5 nm or more and 0.1 μm or less. By setting the film thickness in such a range, it is possible to reduce the peak of the electric field intensity or to generate a plurality of portions where the electric field concentration is dispersed and the electric field is concentrated, and as a result, there is a possibility that it is generated near the end of the drain electrode layer 405b. It can alleviate electric field concentration.

Below, an example of the manufacturing method of the semiconductor device which has the transistor 430 is shown.

A conductive film is formed on the glass substrate 400 having an insulating surface, and the gate film 401 is formed by etching the conductive film. In this embodiment, a tungsten film having a thickness of 100 nm is formed by the sputtering method.

Next, a first gate insulating film 436 is provided to cover the gate electrode layer 401.

As the first gate insulating film 436, a nitride insulating film formed by plasma CVD, sputtering, or the like can be used. For example, a silicon nitride film, a silicon nitride oxide film, etc. are mentioned. The first gate insulating film 436 may be either a single layer structure or a stacked structure.

In addition, as the first gate insulating film 436 to prevent diffusion of impurities from the glass substrate 400, titanium (Ti), molybdenum (Mo), tungsten (W), hafnium (Hf), tantalum (Ta), Metal oxide insulating films containing any one or more metal elements selected from lanthanum (La), zirconium (Zr), nickel (Ni), magnesium (Mg), barium (Ba), and aluminum (Al) (e.g., , An aluminum oxide film, an aluminum oxynitride film, a hafnium oxide film, a magnesium oxide film, a zirconium oxide film, a lanthanum oxide film, a barium oxide film), or a metal nitride insulating film (aluminum nitride film, oxynitride) containing the above-described metal element Aluminum film) can be used. A gallium oxide film, an In—Zr—Zn oxide film, an In—Fe—Zn oxide film, an In—Ce—Zn oxide film, or the like may also be used for the first gate insulating film 436.

In this embodiment, as the first gate insulating film 436, a silicon nitride film having a thickness of 30 nm formed by the plasma CVD method is used.

Since the gate electrode layer 401 is covered with the first gate insulating film 436, the first metal element contained in the glass substrate 400 adheres to the surface of the gate electrode layer 401 in the etching process of forming the gate electrode layer 401. Even if it is, the diffusion to the second gate insulating film 402 can be prevented.

A second gate insulating film 402 is formed on the first gate insulating film 436. In this embodiment, a silicon oxynitride film having a thickness of 300 nm is formed by using plasma CVD.

An oxide semiconductor film 403 is formed over the second gate insulating film 402. In this embodiment, an In—Ga—Zn based oxide film (IGZO film) having a thickness of 35 nm is formed by a sputtering method using a sputtering device having an AC power supply device as the oxide semiconductor film 403. In the present embodiment, an In—Ga—Zn-based oxide target having an atomic ratio of In: Ga: Zn = 1: 1: 1 (= 1/3: 1/3: 1/3) is used. In addition, film-forming conditions are made into oxygen and argon atmosphere (oxygen flow rate ratio 50%), a pressure of 0.6 Pa, a power supply of 5 kW, and a substrate temperature of 170 ° C. The film formation rate under these film formation conditions is 16 nm / min.

Further, a heat treatment for removing (dehydrating or dehydrogenating) hydrogen (including water and hydroxyl groups) contained in the oxide semiconductor film 403 in excess may be performed. In this embodiment, the substrate is introduced into an electric furnace which is one of the heat treatment apparatuses, and the oxide semiconductor film 403 is heated at 450 ° C. for 1 hour in a nitrogen atmosphere, and at 450 ° C. for 1 hour in a nitrogen and oxygen atmosphere. Heat treatment is carried out.

Next, an insulating layer 413 is formed over the channel formation region of the oxide semiconductor film 403 overlapping with the gate electrode layer 401.

The insulating layer 413 can be formed by processing an insulating film formed by plasma CVD or sputtering by etching. As the insulating layer 413, typically, a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, an aluminum oxynitride film, a hafnium oxide film, a gallium oxide film, a silicon nitride film, an aluminum nitride film, a silicon nitride oxide film, or an oxynitride A single layer or lamination of an inorganic insulating film such as an aluminum film can be used.

When the insulating layer 413 in contact with the oxide semiconductor film 403 (the film in contact with the oxide semiconductor film 403 in the case where the insulating layer 413 has a laminated structure) contains a large amount of oxygen, the oxide semiconductor film It can function suitably as a supply source which supplies oxygen to 403.

In this embodiment, a silicon oxide film having a thickness of 200 nm is formed by the sputtering method as the insulating layer 413. The silicon oxide film is selectively etched to form an insulating layer 413 whose cross-sectional shape is trapezoidal or triangular, and the taper angle of the lower end of the cross-sectional shape is 60 ° or less, preferably 45 ° or less, more preferably 30 ° or less. do. In addition, the planar shape of the insulating layer 413 is rectangular. In this embodiment, a resist mask is formed on the silicon oxide film by a photolithography step, and selectively etched to make the taper angle of the lower end of the insulating layer 413 approximately 30 degrees.

After the insulating layer 413 is formed, heat treatment may be performed. In this embodiment, heat processing is performed at 300 degreeC for 1 hour in nitrogen atmosphere.

Next, a conductive film serving as a source electrode layer and a drain electrode layer is formed over the gate electrode layer 401, the first gate insulating film 436, the second gate insulating film 402, the oxide semiconductor film 403, and the insulating layer 413. .

In the present embodiment, a laminate of a titanium film with a thickness of 100 nm, an aluminum film with a thickness of 400 nm, and a titanium film with a thickness of 100 nm formed by the sputtering method is used as the conductive film. As the etching of the conductive film, a stack of a titanium film, an aluminum film, and a titanium film is etched by a dry etching method to form a source electrode layer 405a and a drain electrode layer 405b.

In the present embodiment, two layers of the titanium film and the aluminum film are etched under the first etching condition, and then the remaining titanium film single layer is removed under the second etching condition. Furthermore, the first etching conditions, the etching gas and the _{(BCl 3: 150sccm: Cl 2} = 750sccm) to use, the bias power 1500W, ICP 0W power Power, pressure was 2.0Pa. As the second etching condition, an etching gas (BCl ₃ : Cl ₂ = 700 sccm: 100 sccm) is used, the bias power is 750 W, the ICP power supply power is 0 W, and the pressure is 2.0 Pa.

Through the above process, the transistor 430 of this embodiment is manufactured.

An insulating film may be formed on the source electrode layer 405a and the drain electrode layer 405b.

The insulating film can be formed using the same material and method as the insulating layer 413. For example, a silicon oxynitride film having a thickness of 400 nm is formed by CVD. In addition, heat treatment may be performed after the insulating film is formed. For example, heat treatment is performed at 300 ° C. for 1 hour in a nitrogen atmosphere.

In addition, a planarization insulating film may be formed to reduce surface irregularities caused by the transistor 430.

For example, an acrylic resin film having a thickness of 1500 nm may be formed as a planarization insulating film on the insulating film. The acrylic resin film may be formed by coating an acrylic resin on the transistor 430 using a coating method and then firing (for example, at 250 ° C. for 1 hour in a nitrogen atmosphere).

After the planarization insulating film is formed, heat treatment may be performed. For example, heat treatment is performed at 250 ° C. for 1 hour under a nitrogen atmosphere.

As described above, since the first gate insulating film 436 is provided between the glass substrate 400, the second gate insulating film 402, and the oxide semiconductor film 403, the agent contained in the glass substrate 400. It is possible to prevent the first metal element from diffusing into the second gate insulating film 402 and the oxide semiconductor film 403.

Since it is possible to prevent diffusion of the first metal element contained in the glass substrate 400 which causes deterioration or fluctuation of the electrical characteristics of the transistor 430, it is possible to give the transistor 430 stable electrical characteristics. have.

Therefore, a highly reliable semiconductor device including the transistor 430 having stable electrical characteristics using the oxide semiconductor film 403 can be provided. In addition, high productivity can be achieved by manufacturing a highly reliable semiconductor device with high yield.

(Embodiment 3)

In this embodiment, another embodiment of the semiconductor device and the manufacturing method of the semiconductor device will be described with reference to FIGS. 4A and 4B. Portions and processes having the same or the same function as the above-described embodiment can be performed in the same manner as the above-described embodiment, and repeated description is omitted. In addition, detailed description of the same part is abbreviate | omitted.

The transistor 420 shown in Figs. 4A and 4B is one of the lower gate structures called the channel protection type (also called the channel stop type), and is an example of a transistor also called an inverted staggered transistor. FIG. 4A is a plan view, and a cross section of the portion cut along the dashed-dotted line X2-Y2 shown in FIG. 4A corresponds to FIG. 4B.

As shown in FIG. 4B, which is a cross-sectional view of the transistor 420 in the channel length direction, the semiconductor device including the transistor 420 is formed so as to cover the gate electrode layer 401 and the gate electrode layer 401 on the glass substrate 400. A first gate insulating film 436 is provided, and a second gate insulating film 402, an oxide semiconductor film 403, an insulating layer 423, a source electrode layer 405a, and a drain electrode layer 405b are disposed on the first gate insulating film 436. Has

The insulating layer 423 reaches the oxide semiconductor film 403 and has openings 425a and 425b formed so that the source electrode layer 405a or the drain electrode layer 405b covers the inner wall. Therefore, the peripheral portion of the oxide semiconductor film 403 is covered with the insulating layer 423, and the insulating layer 423 also functions as an interlayer insulating film. By arranging not only the second gate insulating film 402 but also the insulating layer 423 as the interlayer insulating film at the intersection of the gate wiring and the source wiring, parasitic capacitance can be reduced.

In the transistor 420, the oxide semiconductor film 403 is configured to be covered with the insulating layer 423, the source electrode layer 405a, and the drain electrode layer 405b.

The insulating layer 423 can be formed by processing an insulating film formed by plasma CVD or sputtering by etching. In addition, the inner walls of the openings 425a and 425b of the insulating layer 423 have a tapered shape.

The insulating layer 423 is provided over the oxide semiconductor film 403 including at least on the channel formation region of the oxide semiconductor film 403 overlapping with the gate electrode layer 401, and a part functions as a channel protective film.

At least a first gate insulating film 436 and a second gate insulating film 402 are provided between the gate electrode layer 401 and the oxide semiconductor film 403. The composition of the first gate insulating film 436 provided on the gate electrode layer 401 side and the composition of the second gate insulating film 402 provided on the oxide semiconductor film 403 side are different. Further, at the interface between the first gate insulating film 436 and the second gate insulating film 402, the concentration of the first metal element contained in the glass substrate 400 is 5 × 10 ¹⁸ atoms / cm ³ or less (preferably Is 1 × 10 ¹⁸ atoms / cm ³ or less).

A thin film nitride insulating film may be used for the first gate insulating film 436. For example, a silicon nitride film, a silicon nitride oxide film, etc. are mentioned. The first gate insulating film 436 may be either a single layer structure or a stacked structure. The film thickness of the first gate insulating film 436 can be thin, and can be 30 nm or more and 50 nm or less.

In addition, as the first gate insulating film 436 to prevent diffusion of impurities from the glass substrate 400, titanium (Ti), molybdenum (Mo), tungsten (W), hafnium (Hf), tantalum (Ta), Metal oxide insulating films containing any one or more metal elements selected from lanthanum (La), zirconium (Zr), nickel (Ni), magnesium (Mg), barium (Ba), and aluminum (Al) (e.g., , An aluminum oxide film, an aluminum oxynitride film, a hafnium oxide film, a magnesium oxide film, a zirconium oxide film, a lanthanum oxide film, a barium oxide film), or a metal nitride insulating film (aluminum nitride film, oxynitride) containing the above-described metal element Aluminum film) can be used. A gallium oxide film, an In—Zr—Zn oxide film, an In—Fe—Zn oxide film, an In—Ce—Zn oxide film, or the like may also be used for the first gate insulating film 436.

In order to reduce the reliability (stability of the characteristic) of the transistor 420, the metal elements to be reduced are sodium, aluminum, magnesium, calcium, strontium, and barium, and further, silicon, which is another element contained in the glass substrate 400. It is preferable to reduce boron and boron to the same level.

As described above, since the first gate insulating film 436 is provided between the glass substrate 400, the second gate insulating film 402, and the oxide semiconductor film 403, the agent contained in the glass substrate 400. It is possible to prevent the first metal element from diffusing into the second gate insulating film 402 and the oxide semiconductor film 403.

Since it is possible to prevent diffusion of the first metal element contained in the glass substrate 400 which causes deterioration or fluctuation of the electrical characteristics of the transistor 420, it is possible to give the transistor 420 stable electrical characteristics. have.

Therefore, a highly reliable semiconductor device including the transistor 420 having stable electrical characteristics using the oxide semiconductor film 403 can be provided. In addition, high productivity can be achieved by manufacturing a highly reliable semiconductor device with high yield.

(Fourth Embodiment)

In this embodiment, another embodiment of the method of manufacturing the semiconductor device and the semiconductor device will be described with reference to FIGS. 11A and 11B. Portions and processes having the same or the same function as the above-described embodiment can be performed in the same manner as the above-described embodiment, and repeated description is omitted. In addition, detailed description of the same part is abbreviate | omitted. In this embodiment, a transistor having an oxide semiconductor film is presented as an example of a semiconductor device.

The transistor may be a single gate structure in which one channel formation region is formed, a double gate structure in which two channel formation regions are formed, or may be a triple gate structure in which three channel formation regions are formed. Alternatively, the dual gate type may be provided having two gate electrode layers disposed above and below the channel formation region via a gate insulating film.

The transistor 1440 shown in Figs. 11A and 11B is one of the lower gate structures, and is an example of a transistor also called an inverted staggered transistor. FIG. 11A is a plan view, and a cross section of a portion cut in dashed-dotted line A-B shown in FIG. 11A corresponds to FIG. 11B.

As shown in FIG. 11B, which is a cross-sectional view of the transistor 1440 in the channel length direction, in the semiconductor device including the transistor 1440, a protective insulating film 450 is provided on the glass substrate 400, and a gate is formed on the protective insulating film 450. The electrode layer 401, the gate insulating film 452, the oxide semiconductor film 403, the source electrode layer 405a, and the drain electrode layer 405b are provided. In addition, an insulating film 407 covering the transistor 1440 is provided.

By providing the protective insulating film 450 between the glass substrate 400 and the gate electrode layer 401, the second metal contained in the glass substrate 400 at the interface between the gate electrode layer 401 and the gate insulating film 452. The concentration of the element is 5 × 10 ¹⁸ atoms / cm ³ or less (preferably 1 × 10 ¹⁸ atoms / cm ³ or less). The second metal element contained in the glass substrate 400 is an element other than the main elements constituting the gate electrode layer 401 and the gate insulating film 452, and refers to an element diffused from the glass substrate 400. .

The concentration of the second metal element contained in the glass substrate 400 is measured by secondary ion mass spectrometry (SIMS).

Examples of the second metal element contained in the glass substrate 400 include the following elements. For example, since the glass substrate 400, a soda-lime glass, soda-lime-silicon oxide (SiO ₂₎ component of the glass case of, sodium carbonate (Na ₂ CO _3), calcium carbonate (CaCO _3), as a metal element Elements such as sodium and calcium are targeted. Further, if called, so-called glass substrate 400 is used in the liquid crystal panel such as a liquid crystal display free (無) alkaline glass (glass soda is not used), the component is _{SiO 2, Al 2 O 3,} B 2 O ₃ and RO (R is a metal element having a valence of 2 and magnesium, calcium, strontium and barium), and aluminum, magnesium, calcium, strontium and barium as the metal elements are the target elements.

In any case, the metal elements to be reduced in order not to lower the reliability (stability of the characteristics) of the transistors are sodium, aluminum, magnesium, calcium, strontium and barium, and even silicon and boron, which are other elements contained in the glass substrate, are the same. It is desirable to reduce the level to.

A nitride insulating film may be used for the protective insulating film 450. For example, a silicon nitride film, a silicon nitride oxide film, etc. are mentioned. The protective insulating film 450 may be either a single layer structure or a laminated structure.

Further, as a protective insulating film 450 for preventing the diffusion of impurities from the glass substrate 400, titanium (Ti), molybdenum (Mo), tungsten (W), hafnium (Hf), tantalum (Ta), and lanthanum ( Metal oxide insulating films containing any one or more metal elements selected from La), zirconium (Zr), nickel (Ni), magnesium (Mg), barium (Ba), and aluminum (Al) (e.g., oxidation Aluminum film, aluminum oxynitride film, hafnium oxide film, magnesium oxide film, zirconium oxide film, lanthanum oxide film, barium oxide film) or metal nitride insulating film (aluminum nitride film, aluminum nitride oxide film) containing the above-described metal element as a component ) Can be used. In addition, a gallium oxide film, an In—Zr—Zn oxide film, an In—Fe—Zn oxide film, an In—Ce—Zn oxide film, or the like may be used for the protective insulating film 450.

The protective insulating film 450 may be formed by stacking another oxide insulating film in addition to the metal nitride insulating film or the metal oxide insulating film. For example, the protective insulating film 450 may be formed by laminating a silicon nitride film and a silicon oxynitride film from the glass substrate 400 side.

Since the protective insulating film 450 is provided between the glass substrate 400 and the transistor 1440, it is possible to prevent the second metal element contained in the glass substrate 400 from diffusing into the transistor 1440.

In addition, when a dense insulating film such as a silicon nitride film is provided for the protective insulating film 450, it is also possible to prevent diffusion of movable ions such as sodium contained in the glass substrate 400 into the transistor 1440.

Since the diffusion of the second metal element contained in the glass substrate which causes the deterioration or fluctuation of the electrical characteristics of the transistor 1440 can be prevented, stable electrical characteristics can be given to the transistor 1440.

When these metal elements exist in the vicinity of the gate electrode layer, a defect is generated at the interface between the gate insulating film or the gate electrode layer and the gate insulating film, and the charge is trapped therein, which is considered to cause variation in the electrical characteristics of the transistor. For example, if a positive charge is trapped around the gate electrode layer, it is feared that the electrical characteristics of the transistor will change in the direction of normally on. In addition, when movable ions such as sodium are contained in the gate insulating film, the positive movable ions move to the interface between the gate insulating film and the oxide semiconductor film when a positive bias is applied to the gate electrode layer, so that the electrical characteristics of the transistor are normally It causes a fluctuation in the on direction. Therefore, in order to stabilize the electrical characteristics of the transistor, it is effective to prevent metal elements, which are thought to have such adverse effects, from invading from the glass substrate to the gate insulating film side.

Therefore, a highly reliable semiconductor device including the transistor 1440 having stable electrical characteristics using the oxide semiconductor film 403 can be provided.

12A to 12E illustrate an example of a method of manufacturing a semiconductor device having a transistor 1440.

There is no particular limitation regarding the substrate that can be used as the glass substrate 400, but it is necessary that the glass substrate has at least a heat resistance that can withstand the heat treatment performed later. For example, barium borosilicate glass, aluminoborosilicate glass, etc. can be used.

A protective insulating film 450 is provided as an underlayer so as to cover the glass substrate 400 (see Fig. 12A).

The nitride insulating film formed by the plasma CVD method or the sputtering method can be used for the protective insulating film 450. For example, a silicon nitride film, a silicon nitride oxide film, etc. are mentioned. The protective insulating film 450 may be either a single layer structure or a laminated structure.

In this embodiment, as the protective insulating film 450, a lamination of a silicon nitride film having a thickness of 100 nm and a silicon oxide film having a thickness of 150 nm is formed using the plasma CVD method.

The glass substrate 400 or the glass substrate 400 and the protective insulating film 450 may be subjected to heat treatment. For example, the heat treatment may be performed at 650 ° C. for 1 minute to 5 minutes by a GRTA (Gas Rapid Thermal Anneal) apparatus which is heated using a hot gas. As the hot gas used in GRTA, a rare gas such as argon or an inert gas that does not react with the object by heat treatment such as nitrogen is used. Moreover, you may heat-process at 500 degreeC for 30 minutes-1 hour with an electric furnace.

Next, a conductive film is formed over the protective insulating film 450, and the conductive film is etched to form a gate electrode layer 401 (see FIG. 12B). For etching the conductive film, either dry etching or wet etching may be used, or both may be used.

In this embodiment, a tungsten film having a thickness of 100 nm is formed by the sputtering method as the conductive film.

Since the glass substrate 400 is covered with the protective insulating layer 450, the glass substrate 400 is not exposed even when the etching process for forming the gate electrode layer 401 is performed. Therefore, the second metal element contained in the glass substrate 400 can be prevented from adhering to the surface of the gate electrode layer 401.

After the gate electrode layer 401 is formed, heat treatment may be performed on the glass substrate 400, the protective insulating film 450, and the gate electrode layer 401. For example, the GRTA apparatus may perform heat treatment at 650 ° C. for 1 minute to 5 minutes. Moreover, you may perform heat processing for 30 minutes-1 hour at 500 degreeC by an electric furnace.

Next, a gate insulating film 452 is formed over the gate electrode layer 401.

In addition, in order to improve the covering property of the gate insulating film 452, a planarization treatment may be performed on the surface of the gate electrode layer 401. In particular, when an insulating film having a thin film thickness is used as the gate insulating film 452, it is preferable that the flatness of the surface of the gate electrode layer 401 is good.

The gate insulating film 452 has a film thickness of 1 nm or more and 20 nm or less, and can be formed using a sputtering method, an MBE method, a CVD method, a pulse laser deposition method, an ALD method, or the like as appropriate. Further, the gate insulating film 452 may be formed using a sputtering apparatus that forms a film in a state where a plurality of substrate surfaces are set substantially perpendicular to the sputtering target surface.

As the material of the gate insulating film 452, a silicon oxide film, a gallium oxide film, an aluminum oxide film, a silicon nitride film, a silicon oxynitride film, an aluminum oxynitride film, or a silicon nitride oxide film can be formed.

In addition, as a material of the gate insulating film 452, a hafnium oxide film, an yttrium oxide film, a hafnium silicate film (HfSi _x O _y (x> 0, y> 0)), and a hafnium silicate film (HfSiO _x N _y ( gate leakage current can be reduced by using high-k materials such as x> 0, y> 0)), hafnium aluminate films (HfAl _x O _y (x> 0, y> 0)), and lanthanum oxide films. . In addition, the gate insulating film 452 may have either a single layer structure or a stacked structure.

The gate insulating film 452 preferably contains oxygen in a portion in contact with the oxide semiconductor film 403. In particular, the gate insulating film 452 preferably contains oxygen in an amount exceeding at least the stoichiometric composition in the film (in bulk). For example, in the case of using a silicon oxide film as the gate insulating film 452, SiO is used. _{2 + α} (but α> 0).

By forming the gate insulating film 452 containing a large amount (excess) of oxygen as a source of oxygen in contact with the oxide semiconductor film 403, oxygen can be supplied from the gate insulating film 452 to the oxide semiconductor film 403. have. Oxygen may be supplied to the oxide semiconductor film 403 by heat treatment while at least a portion of the oxide semiconductor film 403 and the gate insulating film 452 are in contact with each other.

By supplying oxygen to the oxide semiconductor film 403, oxygen vacancies in the film can be preserved. In addition, the gate insulating film 452 is preferably formed in consideration of the size of the transistor to be manufactured and the step coverage of the gate insulating film 452.

In this embodiment, a silicon oxynitride film having a thickness of 200 nm is formed by using a high density plasma CVD method.

After the gate insulating film 452 is formed, heat treatment may be performed on the glass substrate 400, the gate electrode layer 401, and the gate insulating film 452. For example, the GRTA apparatus may perform heat treatment at 650 ° C. for 1 minute to 5 minutes. Moreover, you may perform heat processing for 30 minutes-1 hour at 500 degreeC by an electric furnace.

Next, an oxide semiconductor film 403 is formed over the gate insulating film 452 (see Fig. 12C).

The planarization process may be performed on the area | region formed by the oxide semiconductor film 403 in contact with the gate insulating film 452. FIG. Although it does not specifically limit as a planarization process, Polishing process (for example, chemical mechanical polishing (CMP)), dry etching process, and plasma process can be used.

As the planarization treatment, a plurality of polishing treatments, dry etching treatments, and plasma treatments may be performed, or a combination thereof may be performed. In addition, when performing a combination of processes, the process order is not specifically limited, either, According to the uneven | corrugated state of the surface of the gate insulating film 452, it can set suitably.

In this embodiment, an In—Ga—Zn based oxide film (IGZO film) having a thickness of 35 nm is formed by the sputtering method using a sputtering apparatus having an AC power supply device as the oxide semiconductor film 403. In the present embodiment, an In—Ga—Zn-based oxide target having an atomic ratio of In: Ga: Zn = 1: 1: 1 (= 1/3: 1/3: 1/3) is used. In addition, film-forming conditions are made into oxygen and argon atmosphere (oxygen flow rate ratio 50%), a pressure of 0.6 Pa, a power supply of 5 kW, and a substrate temperature of 170 ° C. The film formation rate under these film formation conditions is 16 nm / min.

In addition, the gate insulating film 452 and the oxide semiconductor film 403 are preferably formed continuously without exposing the gate insulating film 452 to the atmosphere. By continuously forming the gate insulating film 452 and the oxide semiconductor film 403 without exposing the gate insulating film 452 to the atmosphere, it is possible to prevent impurities such as hydrogen and moisture from adsorbing onto the surface of the gate insulating film 452. .

The oxide semiconductor film 403 can be formed by processing a film-shaped oxide semiconductor film into an island-shaped oxide semiconductor film by a photolithography process.

Further, a heat treatment for removing (dehydrating or dehydrogenating) hydrogen (including water and hydroxyl groups) contained in the oxide semiconductor film 403 in excess may be performed.

In this embodiment, a substrate is introduced into an electric furnace which is one of the heat treatment apparatuses, and the oxide semiconductor film 403 is subjected to heat treatment for 1 hour at 450 ° C. under nitrogen atmosphere and 450 ° C. under nitrogen and oxygen atmosphere for 1 hour. Heat treatment is carried out.

Next, a conductive film is formed on the gate electrode layer 401, the gate insulating film 452, and the oxide semiconductor film 403 to form a source electrode layer and a drain electrode layer (including wiring formed of the same layer as this).

A resist mask is formed on the conductive film by a photolithography process, and is selectively etched to form the source electrode layer 405a and the drain electrode layer 405b (see FIG. 12D). After the source electrode layer 405a and the drain electrode layer 405b are formed, the resist mask is removed.

In the present embodiment, a laminate of a titanium film with a thickness of 100 nm, an aluminum film with a thickness of 400 nm, and a titanium film with a thickness of 100 nm formed by the sputtering method is used as the conductive film. As the etching of the conductive film, a stack of a titanium film, an aluminum film, and a titanium film is etched by a dry etching method to form a source electrode layer 405a and a drain electrode layer 405b.

In the present embodiment, two layers of the titanium film and the aluminum film are etched under the first etching condition, and then the remaining titanium film single layer is removed under the second etching condition. Furthermore, the first etching conditions, the etching gas and the _{(BCl 3: 150sccm: Cl 2} = 750sccm) to use, the bias power 1500W, ICP 0W power Power, pressure was 2.0Pa. As the second etching condition, an etching gas (BCl ₃ : Cl ₂ = 700 sccm: 100 sccm) is used, the bias power is 750 W, the ICP power supply power is 0 W, and the pressure is 2.0 Pa.

Through the above-described process, the transistor 1440 of this embodiment is manufactured.

In this embodiment, an insulating film 407 in contact with the oxide semiconductor film 403 is formed on the source electrode layer 405a and the drain electrode layer 405b (see FIG. 12E).

In this embodiment, a silicon oxide film having a thickness of 300 nm is formed as the insulating film 407 by the sputtering method.

Next, a heating process is performed on the oxide semiconductor film 403 with a part (channel formation region) in contact with the insulating film 407.

This heating process can use the heating method and heating apparatus similar to the heating process which performs a dehydration or a dehydrogenation process.

In addition, since the heating step is performed while the oxide semiconductor film 403 and the insulating film 407 containing oxygen are in contact with each other, the main component material constituting the oxide semiconductor film 403 simultaneously reduced by the removal of impurities. Oxygen, which is one of them, can be supplied from the insulating film 407 containing oxygen to the oxide semiconductor film 403.

In addition, a highly dense inorganic insulating film may be further provided over the insulating film 407. For example, an aluminum oxide film is formed on the insulating film 407 by sputtering.

In addition, a planarization insulating film may be formed in order to reduce surface irregularities caused by the transistor 1440.

For example, an acrylic resin film having a thickness of 1500 nm may be formed as the planarization insulating film. The acrylic resin film may be formed by coating an acrylic resin on the transistor 1440 using a coating method and then firing (for example, 1 hour at 250 ° C. under a nitrogen atmosphere).

After the planarization insulating film is formed, heat treatment may be performed. For example, heat treatment is performed at 250 ° C. for 1 hour under a nitrogen atmosphere.

After the transistor 1440 is formed in this manner, a heat treatment may be performed. In addition, you may perform heat processing in multiple times.

Since the protective insulating film 450 is provided between the glass substrate 400 and the transistor 1440, it is possible to prevent the second metal element contained in the glass substrate 400 from diffusing into the transistor 1440.

Since the diffusion of the second metal element contained in the glass substrate 400 which causes the deterioration or fluctuation of the electrical characteristics of the transistor 1440 can be prevented, it is possible to give the transistor 1440 stable electrical characteristics. have.

Therefore, a highly reliable semiconductor device including the transistor 1440 having stable electrical characteristics using the oxide semiconductor film 403 can be provided. In addition, high productivity can be achieved by manufacturing a highly reliable semiconductor device with high yield.

(Embodiment 5)

In this embodiment, another embodiment of the semiconductor device and the manufacturing method of the semiconductor device will be described with reference to FIGS. 13A and 13B. Portions and processes having the same or the same function as the above-described embodiment can be performed in the same manner as the above-described embodiment, and repeated description is omitted. In addition, detailed description of the same location is abbreviate | omitted.

The transistor 1430 shown in Figs. 13A and 13B is one of a lower gate structure called a channel protection type (also called a channel stop type) and is an example of a transistor also called an inverted staggered transistor. FIG. 13A is a plan view, and a cross section of a portion cut at dashed-dotted line C1-D1 shown in FIG. 13A corresponds to FIG. 13B.

As shown in FIG. 13B, which is a cross-sectional view of the transistor 1430 in the channel length direction, the semiconductor device including the transistor 1430 includes a gate electrode layer 401 and a gate insulating film on a glass substrate 400 provided with a protective insulating film 450. 452, an oxide semiconductor film 403, an insulating layer 413, a source electrode layer 405a, and a drain electrode layer 405b. The insulating layer 413 is in contact with the oxide semiconductor film 403.

By providing the protective insulating film 450 between the glass substrate 400 and the gate electrode layer 401, the second metal contained in the glass substrate 400 at the interface between the gate electrode layer 401 and the gate insulating film 452. The concentration of the element is 5 × 10 ¹⁸ atoms / cm ³ or less (preferably 1 × 10 ¹⁸ atoms / cm ³ or less).

A nitride insulating film may be used for the protective insulating film 450. For example, a silicon nitride film, a silicon nitride oxide film, etc. are mentioned. The protective insulating film 450 may be either a single layer structure or a laminated structure.

Further, as a protective insulating film 450 for preventing the diffusion of impurities from the glass substrate 400, titanium (Ti), molybdenum (Mo), tungsten (W), hafnium (Hf), tantalum (Ta), and lanthanum ( Metal oxide insulating films containing any one or more metal elements selected from La), zirconium (Zr), nickel (Ni), magnesium (Mg), barium (Ba), and aluminum (Al) (e.g., oxidation Aluminum film, aluminum oxynitride film, hafnium oxide film, magnesium oxide film, zirconium oxide film, lanthanum oxide film, barium oxide film) or metal nitride insulating film (aluminum nitride film, aluminum nitride oxide film) containing the above-described metal element as a component ) Can be used. In addition, a gallium oxide film, an In—Zr—Zn oxide film, an In—Fe—Zn oxide film, an In—Ce—Zn oxide film, or the like may be used for the protective insulating film 450.

The protective insulating film 450 may be formed by stacking another oxide insulating film in addition to the metal nitride insulating film or the metal oxide insulating film. For example, the protective insulating film 450 may be formed by laminating a silicon nitride film and a silicon oxynitride film from the glass substrate 400 side.

In order to reduce the reliability (stability of characteristics) of the transistor 1430, the metal elements to be reduced are sodium, aluminum, magnesium, calcium, strontium, and barium, and further, silicon, which is another element contained in the glass substrate 400. It is preferable to reduce boron and boron to the same level.

The insulating layer 413 in contact with the oxide semiconductor film 403 is provided over the channel formation region of the oxide semiconductor film 403 overlapping with the gate electrode layer 401 and functions as a channel protective film.

Below, an example of the manufacturing method of the semiconductor device which has the transistor 1430 is shown.

The protective insulating film 450 is formed on the glass substrate 400 having the insulating surface. In this embodiment, as the protective insulating film 450, a lamination of a silicon nitride film having a thickness of 100 nm and a silicon oxide film having a thickness of 150 nm is formed using the plasma CVD method.

A conductive film is formed on the protective insulating film 450, and the gate electrode layer 401 is formed by etching the conductive film. In this embodiment, a tungsten film having a thickness of 100 nm is formed by the sputtering method.

A gate insulating film 452 is formed on the gate electrode layer 401. In this embodiment, a silicon oxynitride film having a thickness of 200 nm is formed by using a high density plasma CVD method.

An oxide semiconductor film 403 is formed over the gate insulating film 452. In this embodiment, an In—Ga—Zn based oxide film (IGZO film) having a thickness of 35 nm is formed by a sputtering method using a sputtering device having an AC power supply device as the oxide semiconductor film 403. In the present embodiment, an In—Ga—Zn-based oxide target having an atomic ratio of In: Ga: Zn = 1: 1: 1 (= 1/3: 1/3: 1/3) is used. In addition, film-forming conditions are made into oxygen and argon atmosphere (oxygen flow rate ratio 50%), a pressure of 0.6 Pa, a power supply of 5 kW, and a substrate temperature of 170 ° C. The film formation rate under these film formation conditions is 16 nm / min.

The heat treatment for removing (dehydrating or dehydrogenating) hydrogen (including water and hydroxyl groups) contained in the oxide semiconductor film 403 in excess may be performed. In this embodiment, a substrate is introduced into an electric furnace which is one of the heat treatment apparatuses, and the oxide semiconductor film 403 is subjected to heat treatment for 1 hour at 450 ° C. under nitrogen atmosphere and 450 ° C. under nitrogen and oxygen atmosphere for 1 hour. Heat treatment is carried out.

Next, an insulating layer 413 is formed over the channel formation region of the oxide semiconductor film 403 overlapping with the gate electrode layer 401.

In this embodiment, a silicon oxide film having a thickness of 200 nm is formed by the sputtering method as the insulating layer 413. The silicon oxide film is selectively etched to form an insulating layer 413 whose cross-sectional shape is trapezoidal or triangular, and the taper angle of the lower end of the cross-sectional shape is 60 ° or less, preferably 45 ° or less, more preferably 30 ° or less. do. In addition, the planar shape of the insulating layer 413 is rectangular. In this embodiment, a resist mask is formed on the silicon oxide film by a photolithography step, and selectively etched to make the taper angle of the lower end of the insulating layer 413 approximately 30 degrees.

After the insulating layer 413 is formed, heat treatment may be performed. In this embodiment, heat processing is performed at 300 degreeC for 1 hour in nitrogen atmosphere.

Next, a conductive film serving as a source electrode layer and a drain electrode layer is formed over the gate electrode layer 401, the gate insulating film 452, the oxide semiconductor film 403, and the insulating layer 413.

In the present embodiment, a laminate of a titanium film with a thickness of 100 nm, an aluminum film with a thickness of 400 nm, and a titanium film with a thickness of 100 nm formed by the sputtering method is used as the conductive film. As the etching of the conductive film, a stack of a titanium film, an aluminum film, and a titanium film is etched by a dry etching method to form a source electrode layer 405a and a drain electrode layer 405b.

In the present embodiment, two layers of the titanium film and the aluminum film are etched under the first etching condition, and then the remaining titanium film single layer is removed under the second etching condition. Furthermore, the first etching conditions, the etching gas and the _{(BCl 3: 150sccm: Cl 2} = 750sccm) to use, the bias power 1500W, ICP 0W power Power, pressure was 2.0Pa. As the second etching condition, an etching gas (BCl ₃ : Cl ₂ = 700 sccm: 100 sccm) is used, the bias power is 750 W, the ICP power supply power is 0 W, and the pressure is 2.0 Pa.

Through the above process, the transistor 1430 of this embodiment is manufactured.

An insulating film may be formed on the source electrode layer 405a and the drain electrode layer 405b.

The insulating film can be formed using the same material and method as the insulating layer 413. For example, a silicon oxynitride film having a thickness of 400 nm is formed by CVD. In addition, heat treatment may be performed after the insulating film is formed. For example, heat treatment is performed at 300 ° C. for 1 hour in a nitrogen atmosphere.

In addition, a planarization insulating film may be formed to reduce surface irregularities caused by the transistor 1430.

For example, an acrylic resin film having a thickness of 1500 nm may be formed as a planarization insulating film on the insulating film. The acrylic resin film may be formed by coating an acrylic resin on the transistor 1430 by using a coating method, followed by baking (for example, at 250 ° C. under a nitrogen atmosphere for 1 hour).

After the planarization insulating film is formed, heat treatment may be performed. For example, heat treatment is performed at 250 ° C. for 1 hour under a nitrogen atmosphere.

As described above, since the protective insulating film 450 is provided between the glass substrate 400 and the transistor 1430, the second metal element contained in the glass substrate 400 is prevented from diffusing into the transistor 1430. can do.

Since it is possible to prevent the diffusion of the second metal element contained in the glass substrate which causes the deterioration or fluctuation of the electrical characteristics of the transistor 1430, it is possible to give the transistor 1430 stable electrical characteristics.

Therefore, a highly reliable semiconductor device including the transistor 1430 having stable electrical characteristics using the oxide semiconductor film 403 can be provided. In addition, high productivity can be achieved by manufacturing a highly reliable semiconductor device with high yield.

(Embodiment 6)

In this embodiment, another embodiment of the method of manufacturing the semiconductor device and the semiconductor device will be described with reference to FIGS. 14A and 14B. Portions and processes having the same or the same function as the above-described embodiment can be performed in the same manner as the above-described embodiment, and repeated description is omitted. In addition, detailed description of the same part is abbreviate | omitted.

The transistor 1420 shown in Figs. 14A and 14B is one of the lower gate structures called the channel protection type (also called the channel stop type), and is an example of a transistor also called an inverted staggered transistor. FIG. 14A is a plan view, and a cross section of a portion cut in dashed-dotted line C2-D2 shown in FIG. 14A corresponds to FIG. 14B.

As shown in FIG. 14B, which is a cross-sectional view of the transistor 1420 in the channel length direction, the semiconductor device including the transistor 1420 includes a gate electrode layer 401 and a gate insulating film on a glass substrate 400 provided with a protective insulating film 450. 452, an oxide semiconductor film 403, an insulating layer 423, a source electrode layer 405a, and a drain electrode layer 405b.

The insulating layer 423 is provided over the oxide semiconductor film 403 including at least the channel formation region of the oxide semiconductor film 403 overlapping with the gate electrode layer 401, and functions as a channel protective film. The insulating layer 423 has openings 425a and 425b formed to reach the oxide semiconductor film 403 and the source electrode layer 405a or the drain electrode layer 405b to cover the inner wall. Therefore, the peripheral part of the oxide semiconductor film 403 is covered with the insulating layer 423, and also functions as an interlayer insulating film. By arranging not only the gate insulating film 452 but also the insulating layer 423 as the interlayer insulating film at the intersection of the gate wiring and the source wiring, parasitic capacitance can be reduced.

In the transistor 1420, the oxide semiconductor film 403 is configured to be covered with the insulating layer 423, the source electrode layer 405a, and the drain electrode layer 405b.

The insulating layer 423 can be formed by processing an insulating film formed by plasma CVD or sputtering by etching. In addition, the inner walls of the openings 425a and 425b of the insulating layer 423 have a tapered shape.

The insulating layer 423 is provided over the oxide semiconductor film 403 including at least on the channel formation region of the oxide semiconductor film 403 overlapping with the gate electrode layer 401, and a part functions as a channel protective film.

By providing the protective insulating film 450 between the glass substrate 400 and the gate electrode layer 401, the second metal contained in the glass substrate 400 at the interface between the gate electrode layer 401 and the gate insulating film 452. The concentration of the element is 5 × 10 ¹⁸ atoms / cm ³ or less (preferably 1 × 10 ¹⁸ atoms / cm ³ or less).

A nitride insulating film may be used for the protective insulating film 450. For example, a silicon nitride film, a silicon nitride oxide film, etc. are mentioned. The protective insulating film 450 may be either a single layer structure or a laminated structure.

Further, as a protective insulating film 450 for preventing the diffusion of impurities from the glass substrate 400, titanium (Ti), molybdenum (Mo), tungsten (W), hafnium (Hf), tantalum (Ta), and lanthanum ( A metal oxide insulating film containing any one or more metal elements selected from La), zirconium (Zr), nickel (Ni), magnesium (Mg), barium (Ba), and aluminum (Al) (e.g., aluminum oxide Film, aluminum oxynitride film, hafnium oxide film, magnesium oxide film, zirconium oxide film, lanthanum oxide film, barium oxide film) or metal nitride insulating film (aluminum nitride film, aluminum nitride oxide film) containing the above-described metal element as a component Can be used. In addition, a gallium oxide film, an In—Zr—Zn oxide film, an In—Fe—Zn oxide film, an In—Ce—Zn oxide film, or the like may be used for the protective insulating film 450.

The protective insulating film 450 may be formed by stacking another oxide insulating film in addition to the metal nitride insulating film or the metal oxide insulating film. For example, the protective insulating film 450 may be formed by laminating a silicon nitride film and a silicon oxynitride film from the glass substrate 400 side.

In order to reduce the reliability (stability of characteristics) of the transistor 1420, the metal elements to be reduced are sodium, aluminum, magnesium, calcium, strontium, and barium, and further, silicon, which is another element contained in the glass substrate 400. It is preferable to reduce boron and boron to the same level.

As described above, since the protective insulating film 450 is provided between the glass substrate 400 and the transistor 1420, the second metal element contained in the glass substrate 400 is prevented from diffusing into the transistor 1420. can do.

Since it is possible to prevent the diffusion of the second metal element contained in the glass substrate which causes the deterioration or fluctuation of the electrical characteristics of the transistor 1420, the stable electrical characteristics can be given to the transistor 1420.

Therefore, a highly reliable semiconductor device including the transistor 1420 having stable electrical characteristics using the oxide semiconductor film 403 can be provided. In addition, high productivity can be achieved by manufacturing a highly reliable semiconductor device with high yield.

(Seventh Embodiment)

A semiconductor device (also referred to as a display device) having a display function can be manufactured using the transistors described in any one of the first to sixth embodiments. In addition, a part or all of the driving circuit including the transistor may be integrally formed on the same substrate as the pixel portion to form a system on panel.

In FIG. 5A, a sealant 4005 is provided to enclose a pixel portion 4002 provided on a glass substrate 4001 and sealed with a substrate 4006. In FIG. 5A, a scan line driver circuit 4004 and a signal line driver circuit formed of a single crystal semiconductor film or a polycrystalline semiconductor film on an IC chip or a substrate separately provided in a region different from the region surrounded by the seal member 4005 on the glass substrate 4001. 4003 is mounted. In addition, various signals and potentials supplied to the separately formed signal line driver circuit 4003 and the scan line driver circuit 4004 or the pixel portion 4002 are supplied from the FPC (Flexible Printed Circuit) 4018a and 4018b.

5B and 5C, a seal member 4005 is provided to surround the pixel portion 4002 and the scan line driver circuit 4004 provided on the glass substrate 4001. In addition, a substrate 4006 is provided over the pixel portion 4002 and the scan line driver circuit 4004. Therefore, the pixel portion 4002 and the scan line driver circuit 4004 are sealed together with the display element by the glass substrate 4001, the seal member 4005, and the substrate 4006. 5B and 5C, a signal line driver circuit 4003 formed of a single crystal semiconductor film or a polycrystalline semiconductor film on an IC chip or a separately provided substrate is mounted in a region different from the region surrounded by the seal member 4005 on the glass substrate 4001. It is. 5B and 5C, various signals and potentials supplied to the signal line driver circuit 4003 and the scan line driver circuit 4004 or the pixel portion 4002 formed separately are supplied from the FPC 4018.

In addition, although the signal line drive circuit 4003 was formed separately and was mounted on the glass substrate 4001 in FIG. 5B and 5C, it is not limited to this structure. The scan line driver circuit may be separately formed and mounted, or only a part of the signal line driver circuit or a part of the scan line driver circuit may be separately formed and mounted.

In addition, the connection method of the drive circuit formed separately is not specifically limited, A COG (Chip On Glass) method, a wire bonding method, the Tape Automated Bonding (TAB) method, etc. can be used. 5A is an example in which the signal line driver circuit 4003 and the scan line driver circuit 4004 are mounted by the COG method, and FIG. 5B is an example in which the signal line driver circuit 4003 is mounted by the COG method, and FIG. 5C is a signal line by the TAB method. This is an example in which the drive circuit 4003 is mounted.

The display device also includes a panel in which the display element is sealed, and a module in which an IC including a controller is mounted on the panel.

In addition, the display device in this specification refers to an image display device, a display device, or a light source (including an illumination device). Also displays all connectors, such as FPC or TAB tape, or modules with TCP, modules with printed wiring boards at the end of TAB tape or TCP, or modules with integrated circuits (ICs) mounted directly on display elements in a COG manner. It shall be included in.

The pixel portion and the scan line driver circuit provided on the glass substrate have a plurality of transistors, and the transistors described in any of the first to sixth embodiments can be applied.

As a display element formed in a display apparatus, a liquid crystal element (also called liquid crystal display element) and a light emitting element (also called light emitting display element) can be used. The light emitting device includes, in its category, an element whose luminance is controlled by current or voltage, and specifically includes an inorganic EL (Electro Luminescence), an organic EL, and the like. It is also possible to apply a display medium whose contrast ratio changes due to an electrical action such as electronic ink.

One embodiment of the semiconductor device will be described with reference to FIGS. 7A, 7B, 16A, and 16B. 7A, 7B, 16A, and 16B correspond to sectional views of the M-N portion shown in Fig. 5B.

As shown in FIGS. 7A, 7B, 16A, and 16B, the semiconductor device has a connecting terminal electrode 4015 and a terminal electrode 4016, and the connecting terminal electrode 4015 and the terminal electrode 4016 It is electrically connected to the terminal which the FPC 4018 has through the anisotropic conductive film 4019.

The connecting terminal electrode 4015 is formed of the same conductive film as the first electrode layer 4030, and the terminal electrode 4016 is formed of the same conductive film as the source electrode layer and the drain electrode layer of the transistors 4010, 4011, 4040, 4041. It is.

In addition, the pixel portion 4002 and the scan line driver circuit 4004 formed on the glass substrate 4001 have a plurality of transistors, and the transistors included in the pixel portion 4002 in FIGS. 7A, 7B, 16A, and 16B are illustrated. 4010 or the transistor 4040 and the transistor 4011 or the transistor 4041 included in the scanning line driver circuit 4004 are illustrated. In FIGS. 7A, 7B, 16A, and 16B, an insulating film 4020 is provided over the transistor 4010, the transistor 4011, or the transistor 4040, the transistor 4041, and FIGS. 7A, 7B, and 16A. And FIG. 16B, an insulating film 4021 is further provided.

As the transistor 4010, the transistor 4011, the transistor 4040, and the transistor 4041, the transistors described in any of Embodiments 1 to 6 can be used. In the present embodiment, a transistor having the same structure as that of the transistor 430 described in the second embodiment is applied to the transistor 4010 and the transistor 4011, and the transistor 4040 and the transistor 4041 are the same as those described in the fifth embodiment. An example in which a transistor having the same structure as the transistor 1430 is applied will be described. The transistor 4010, the transistor 4011, the transistor 4040, and the transistor 4041 are staggered transistors of a lower gate structure provided with an insulating layer serving as a channel protective film on the oxide semiconductor film.

The gate electrode layers of the transistor 4010 and the transistor 4011 are covered with the first gate insulating film 4023, and the second gate insulating film and the oxide semiconductor film of the transistor 4010 and the transistor 4011 are contained in the glass substrate 4001. It is protected from contamination by the first metal element. Therefore, at the interface between the transistor 4010, the first gate insulating film 4023 of the transistor 4011, and the second gate insulating film, the concentration of the first metal element contained in the glass substrate 4001 is 5 × 10 ¹⁸ atoms. It can be / cm ³ or less (preferably 1x10 ¹⁸ atoms / cm ³ or less).

A thin film nitride insulating film may be used for the first gate insulating film 4023. For example, a silicon nitride film, a silicon nitride oxide film, etc. are mentioned. The film thickness of the first gate insulating film 4023 can be thin, and can be 30 nm or more and 50 nm or less. The first gate insulating film 4023 may be either a single layer structure or a stacked structure. In this embodiment, a silicon nitride film is used as the first gate insulating film 4023.

In the semiconductor device shown in FIGS. 16A and 16B, a protective insulating film 4053 is provided between the glass substrate 4001, the transistor 4040, and the transistor 4041. The protective insulating film 4053 is an insulating film functioning as an underlayer. A nitride insulating film can be used for the protective insulating film 4053. For example, a silicon nitride film, a silicon nitride oxide film, etc. are mentioned. The protective insulating film 4053 may be either a single layer structure or a laminated structure. In this embodiment, a silicon nitride film is used as the protective insulating film 4053.

The transistors 4040 and 4041 are provided on the glass substrate 4001 covered with the protective insulating film 4053, and are protected from contamination by the second metal element contained in the glass substrate 4001. Therefore, at the interface between the transistor 4040, the gate electrode layer of the transistor 4041 and the gate insulating film, the concentration of the second metal element contained in the glass substrate 4001 is 5 × 10 ¹⁸ atoms / cm ³ or less (preferably Can be 1 × 10 ¹⁸ atoms / cm ³ or less).

Therefore, the transistor 4010, the transistor 4011, or the transistor 4040, the transistor 4041 having stable electrical characteristics using the oxide semiconductor film of the present embodiment shown in Figs. 7A, 7B, 16A, and 16B. A semiconductor device having high reliability can be manufactured as a semiconductor device including a semiconductor device. In addition, high productivity can be achieved by fabricating such a highly reliable semiconductor device with high yield.

The conductive layer may be further provided at positions overlapping with the channel formation region of the oxide semiconductor film of the driver circuit transistors 4011 and 4041. By providing the conductive layer at a position overlapping with the channel formation region of the oxide semiconductor film, it is possible to further reduce the amount of change in the threshold voltage of the transistors 4011 and 4041 before and after the bias-thermal stress test (BT test). The conductive layer may be either of the same as or different from the gate electrode layers of the transistors 4011 and 4041, and may function as a second gate electrode layer. Further, the potential of the conductive layer may be GND, 0 V, or in a floating state.

In addition, the conductive layer also has a function of shielding an external electric field, that is, a function of preventing the external electric field from acting on the inside (circuit including a transistor) (especially an electrostatic shielding function against static electricity). By the shielding function of the conductive layer, it is possible to prevent variations in the electrical characteristics of the transistor due to the influence of an external electric field such as static electricity.

The transistors 4010 and 4040 provided in the pixel portion 4002 are electrically connected to the display elements to form a display panel. The display element is not limited to a particular one as long as it can display, and various display elements can be used.

7A and 16A show an example of a liquid crystal display device using a liquid crystal element as the display element. 7A and 16A, the liquid crystal element 4013, which is a display element, includes a first electrode layer 4030, a second electrode layer 4031, and a liquid crystal composition 4008. In addition, insulating films 4032 and 4033 functioning as alignment films are formed to sandwich the liquid crystal composition 4008. The second electrode layer 4031 is provided on the substrate 4006 side, and the first electrode layer 4030 and the second electrode layer 4031 are laminated with the liquid crystal composition 4008 interposed therebetween.

In addition, the spacer 4035 is a columnar spacer obtained by selectively etching an insulating film, and is formed in order to control the thickness (cell gap) of the liquid crystal composition 4008. In addition, a spherical spacer may be used.

When a liquid crystal element is used as the display element, a thermotropic liquid crystal, a low molecular liquid crystal, a polymer liquid crystal, a polymer dispersed liquid crystal, a ferroelectric liquid crystal, an antiferroelectric liquid crystal, or the like can be used. These liquid crystal materials (liquid crystal composition) show a cholesteric phase, a smectic phase, a cubic phase, a chiral nematic phase, an isotropic phase, etc. according to conditions.

In addition, you may use the liquid crystal composition which expresses the blue phase which does not use an alignment film for the liquid crystal composition 4008. In this case, the liquid crystal composition 4008 and the first electrode layer 4030 and the second electrode layer 4031 are in contact with each other. The blue phase is one of the liquid crystal phases, and when the cholesteric liquid crystal is continuously heated, the blue phase is a phase which is expressed immediately before transition from the cholesteric phase to the isotropic phase. A blue phase can be expressed using the liquid crystal composition which mixed the liquid crystal and a chiral agent. In addition, in order to widen the temperature range in which the blue phase is expressed, a liquid crystal composition may be formed by adding a polymerizable monomer, a polymerization initiator, or the like to the liquid crystal composition expressing the blue phase, and subjecting the polymer to stabilization. Since the liquid crystal composition which expresses a blue phase has a short response speed and is optically isotropic, an orientation process is unnecessary and a viewing angle dependency is small. In addition, since the alignment film does not have to be provided, the rubbing process is also unnecessary, so that electrostatic breakage due to the rubbing process can be prevented, and defects or breakage of the liquid crystal display device during the manufacturing process can be reduced. Therefore, the productivity of the liquid crystal display device can be improved. In the transistor using the oxide semiconductor film, the electrical characteristics of the transistor are significantly changed due to the influence of static electricity, which may deviate from the design range. Therefore, it is more effective to use the liquid crystal composition which expresses a blue phase in the liquid crystal display device which has a transistor using an oxide semiconductor film.

The resistivity of the liquid crystal material is 1 × 10 ⁹ Ω · cm or more, preferably 1 × 10 ¹¹ Ω · cm or more, and more preferably 1 × 10 ¹² Ω · cm or more. In addition, the value of specific resistance in this specification is made into the value measured at 20 degreeC.

The size of the storage capacitor formed in the liquid crystal display device is set so that the charge can be maintained for a predetermined period in consideration of leakage current and the like of the transistor disposed in the pixel portion. The size of the holding capacitor may be set in consideration of the off current of the transistor and the like. By using a transistor having an oxide semiconductor film as described herein, it is sufficient to form a storage capacitor having a size of 1/3 or less, preferably 1/5 or less of the liquid crystal capacitance in each pixel.

In the transistor using the oxide semiconductor film described herein, the current value (off current value) in the off state can be controlled to be low. Therefore, the holding time of an electrical signal such as an image signal can be lengthened, and the recording interval can also be set long when the power supply is turned on. Therefore, since the frequency of the refresh operation can be reduced, there is an effect of suppressing power consumption.

In addition, the transistor using the oxide semiconductor film described herein can be driven at high speed because a relatively high field effect mobility can be obtained. For example, by using such a transistor capable of high speed driving in a liquid crystal display device, a switching transistor of a pixel portion and a driver transistor for use in a driving circuit portion can be formed on the same substrate. That is, since there is no need to use a semiconductor device formed of a silicon wafer or the like separately as a driving circuit, the number of components of the semiconductor device can be reduced. In addition, by using a transistor capable of high-speed driving in the pixel portion, it is possible to provide a high quality image.

Liquid crystal displays include twisted nematic (TN) mode, in-plane-switching (IPS) mode, fringe field switching (FSF) mode, axially symmetric aligned micro-cell (ASM) mode, optically compensated birefringence (OCB) mode, and FLC (FLC) Ferroelectric Liquid Crystal mode, Antiferroelectric Liquid Crystal (AFLC) mode, and the like can be used.

Further, a normally black liquid crystal display device, for example, a transmissive liquid crystal display device employing a vertical alignment (VA) mode may be used. Examples of the vertical alignment mode include some examples, and for example, a multi-domain vertical alignment (MVA) mode, a patterned vertical alignment (PVA) mode, an advanced super view (ASV) mode, and the like can be used. Moreover, it can also be applied to VA type liquid crystal display device. The VA type liquid crystal display device is one of methods of controlling the arrangement of liquid crystal molecules in the liquid crystal display panel. The VA liquid crystal display is a system in which liquid crystal molecules are directed in a direction perpendicular to the panel surface when no voltage is applied. In addition, a method called multi-domainization or multi-domain design may be used, which is configured to divide a pixel (pixel) into several regions (sub pixels) and orient molecules in different directions, respectively.

In the display device, an optical member (optical substrate) such as a black matrix (light shielding layer), a polarizing member, a retardation member, an antireflection member, or the like is appropriately provided. For example, circularly polarized light by a polarizing substrate and a phase difference substrate may be used. Further, a back light, a side light, or the like may be used as the light source.

As the display method in the pixel portion, a progressive method, an interlace method, or the like can be used. In color display, the color elements controlled by the pixel are not limited to three colors of RGB (R represents red, G represents green, and B represents blue). For example, RGBW (W represents white) or RGB, yellow, cyan, magenta, etc., have added one or more colors. Further, the size of the display area may be different for each color element dot. However, the present invention is not limited to the display device of the color display, but may be applied to the display device of the monochrome display.

In addition, as a display element included in the display device, a light emitting element using an electroluminescence can be applied. The light emitting element using the electroluminescence is classified according to whether the light emitting material is an organic compound or an inorganic compound, and in general, the former is called an organic EL element, and the latter is called an inorganic EL element.

By applying a voltage to the light emitting element, the organic EL element is injected with electrons and holes from the pair of electrodes into the layer containing the luminescent organic compound, respectively, and a current flows. Then, by recombination of these carriers (electrons and holes), the luminescent organic compound forms an excited state and emits light when the excited state returns to the ground state. Due to this mechanism, such a light emitting element is called a current excited type light emitting element. In this embodiment, an example in which an organic EL element is used as a light emitting element is presented.

The inorganic EL element is classified into a dispersion-type inorganic EL element and a thin-film inorganic EL element according to its element structure. The dispersed inorganic EL device has a light emitting layer in which particles of a light emitting material are dispersed in a binder, and the light emitting mechanism is donor-acceptor recombination type light emission using a donor level and an acceptor level. The thin-film inorganic EL device has a structure in which a dielectric layer sandwiches a light emitting layer and sandwiches it between electrodes, and the light emitting mechanism is localized light emission using an inner-shell electron transition of metal ions. In addition, the example which used the organic electroluminescent element as a light emitting element is demonstrated here.

In the light emitting element, one of the at least one pair of electrodes may have a light transmitting property in order to extract light emission. Then, a transistor and a light emitting element are formed on the substrate, and the upper surface ejection extracts light emission from the surface on the opposite side from the substrate, the lower surface ejection extracts light emission from the surface on the substrate side, from the surface on the side opposite to the substrate and the substrate. There exists a light emitting element of the double-sided injection structure which extracts light emission, and the light emitting element of any injection structure can be applied.

6A, 6B, 7B, 15A, 15B, and 16B show examples of light emitting devices using light emitting elements as display elements.

FIG. 6A is a plan view of the light emitting device, and a cross section of a portion cut in dashed-dotted lines V1-W1, V2-W2, and V3-W3 shown in FIG. 6A corresponds to FIG. 6B. 6A, the electroluminescent layer 542 and the second electrode layer 543 are not illustrated.

6A and 6B have a transistor 510, a capacitor 520, and a wiring layer intersection 530 on the glass substrate 500, and the transistor 510 is electrically connected to the light emitting element 540. Is connected. 6A and 6B illustrate a light emitting device having a bottom emission type structure that extracts light from the light emitting element 540 through the glass substrate 500.

As the transistor 510, the transistor described in any of Embodiments 1 to 6 can be used. In this embodiment, an example in which a transistor having the same structure as that of the transistor 420 described in the third embodiment is applied. The transistor 510 is a staggered transistor of a lower gate structure provided with an insulating layer serving as a channel protective film over the oxide semiconductor film.

The transistor 510 is a conductive layer 513a or 513b that functions as a gate electrode layer 511a or 511b, a first gate insulating film 501, a second gate insulating film 502, an oxide semiconductor film 512, a source electrode layer or a drain electrode layer. ).

The gate electrode layer of the transistor 510 is covered with the first gate insulating film 501, so that the second gate insulating film 502 and the oxide semiconductor film 512 of the transistor 510 are included in the glass substrate 500. It is protected from contamination by elements. Therefore, at the interface between the first gate insulating film 501 and the second gate insulating film 502, the concentration of the first metal element contained in the glass substrate 500 is 5 × 10 ¹⁸ atoms / cm ³ or less (preferably Can be 1 × 10 ¹⁸ atoms / cm ³ or less).

A thin film nitride insulating film may be used for the first gate insulating film 501. For example, a silicon nitride film, a silicon nitride oxide film, etc. are mentioned. The film thickness of the first gate insulating film 501 can be thin, and can be 30 nm or more and 50 nm or less. The first gate insulating film 501 may be either a single layer structure or a stacked structure. In this embodiment, a silicon nitride film is used as the first gate insulating film 501.

Therefore, a highly reliable semiconductor device can be provided as a semiconductor device including the transistor 510 having stable electrical characteristics using the oxide semiconductor film 512 of this embodiment shown in Figs. 6A and 6B. In addition, high productivity can be achieved by fabricating such a highly reliable semiconductor device with high yield.

The capacitor 520 includes the conductive layers 521a and 521b, the second gate insulating layer 502, the oxide semiconductor film 522, and the conductive layer 523, and the conductive layers 521a and 521b and the conductive layer 523. ) Is formed by sandwiching the second gate insulating film 502 and the oxide semiconductor film 522.

The wiring layer intersection 530 is an intersection of the gate electrode layers 511a and 511b and the conductive layer 533, and the gate electrode layers 511a and 511b and the conductive layer 533 are formed of the second gate insulating film 502 and the first gate. The insulating film 501 is interposed therebetween. According to the structure shown in Embodiment 3, the wiring layer crossing portion 530 also includes not only the second gate insulating film 502 but also the first gate insulating film 501 between the gate electrode layers 511a and 511b and the conductive layer 533. As a result, parasitic capacitance generated between the gate electrode layers 511a and 511b and the conductive layer 533 can be reduced.

FIG. 15A is a plan view of the light emitting device, and a cross section of a portion cut in dashed-dotted lines V4-W4, V5-W5, and V6-W6 shown in FIG. 15A corresponds to FIG. 15B. In the plan view of FIG. 15A, the electroluminescent layer 542 and the second electrode layer 543 are not illustrated.

15A and 15B have a transistor 1510, a capacitor 1520, and a wiring layer intersection 1530 on a glass substrate 500 provided with a protective insulating film 550 functioning as an underlayer, The transistor 1510 is electrically connected to the light emitting element 540. 15A and 15B illustrate a light emitting device having a bottom emission type structure that extracts light from the light emitting element 540 through the glass substrate 500.

A nitride insulating film may be used for the protective insulating film 550. For example, a silicon nitride film, a silicon nitride oxide film, etc. are mentioned. The protective insulating film 550 may be either a single layer structure or a laminated structure. In this embodiment, a silicon nitride film is used as the protective insulating film 550.

As the transistor 1510, the transistor described in any of Embodiments 1 to 6 can be used. In this embodiment, an example in which a transistor having the same structure as that of the transistor 1420 shown in Embodiment 6 is applied. The transistor 1510 is a staggered transistor of a bottom gate structure provided with an insulating layer serving as a channel protective film over the oxide semiconductor film.

The transistor 1510 includes gate electrode layers 511a and 511b, a gate insulating film 592, an oxide semiconductor film 512, an insulating layer 503, and conductive layers 513a and 513b that function as source or drain electrode layers. .

The transistor 1510 is provided over the oxide semiconductor film 512 including an insulating layer 503 serving as a channel protective film over the channel formation region of the oxide semiconductor film 512 overlapping at least the gate electrode layers 511a and 511b. Further, the conductive layers 513a and 513b that reach the oxide semiconductor film 512 and function as the source electrode layer or the drain electrode layer have an opening formed to cover the inner wall.

The transistor 1510 is provided on the glass substrate 500 covered with the protective insulating film 550, and is protected from contamination due to the second metal element included in the glass substrate 500. Therefore, at the interface between the gate electrode layers 511a and 511b of the transistor 1510 and the gate insulating film 592, the concentration of the second metal element contained in the glass substrate 500 is 5 × 10 ¹⁸ atoms / cm ³ or less. (Preferably 1 * 10 <^18> atoms / cm <^3> or less).

Therefore, a highly reliable semiconductor device can be provided as a semiconductor device including the transistor 1510 having stable electrical characteristics using the oxide semiconductor film 512 of this embodiment shown in Figs. 15A and 15B. In addition, high productivity can be achieved by fabricating such a highly reliable semiconductor device with high yield.

The capacitor 1520 includes conductive layers 521a and 521b, a gate insulating film 592, an oxide semiconductor film 522, and a conductive layer 523, and the conductive layers 521a and 521b and the conductive layer 523 are formed. The capacitor is formed by sandwiching the gate insulating film 592 and the oxide semiconductor film 522.

The wiring layer intersection 1530 is an intersection of the gate electrode layers 511a and 511b and the conductive layer 533, and the gate electrode layers 511a and 511b and the conductive layer 533 are the gate insulating film 592 and the insulating layer 503. Intersect with. In the structure shown in Embodiment 3, since the wiring layer crossing portion 1530 can arrange not only the gate insulating film 592 but also the insulating layer 503 between the gate electrode layers 511a and 511b and the conductive layer 533. The parasitic capacitance generated between the gate electrode layers 511a and 511b and the conductive layer 533 can be reduced.

In this embodiment, a titanium film having a thickness of 30 nm is used as the gate electrode layer 511a and the conductive layer 521a, and a copper thin film having a thickness of 200 nm is used as the gate electrode layer 511b and the conductive layer 521b. Therefore, the gate electrode layer has a laminated structure of a titanium film and a copper thin film.

As the oxide semiconductor films 512 and 522, an IGZO film having a thickness of 25 nm is used.

An interlayer insulating film 504 is formed on the transistors 510 and 1510, the capacitors 520 and 1520, and the wiring layer intersections 530 and 1530, and is formed in the region overlapping the light emitting device 540 on the interlayer insulating film 504. A color filter layer 505 is provided. On the interlayer insulating film 504 and the color filter layer 505, an insulating film 506 serving as a planarization insulating film is provided.

A light emitting device 540 including a stacked structure in which the first electrode layer 541, the electroluminescent layer 542, and the second electrode layer 543 are stacked on the insulating film 506 is provided. The light emitting element 540 and the transistor 510 or the transistor 1510 have the first electrode layer 541 and the conductive layer 513a at the opening formed in the insulating film 506 and the interlayer insulating film 504 reaching the conductive layer 513a. It is electrically connected by contacting. In addition, a partition 507 is provided to cover a portion of the first electrode layer 541 and the opening.

As the interlayer insulating film 504, a silicon oxynitride film having a thickness of 200 nm or more and 600 nm or less formed by plasma CVD can be used. As the insulating film 506, a photosensitive acrylic film having a film thickness of 1500 nm and a photosensitive polyimide film having a film thickness of 1500 nm can be used for the partition wall 507.

As the color filter layer 505, for example, colored light transmitting resin can be used. Photochromic and non-photosensitive organic resins can be used as the colored light-transmissive resin. However, when the photosensitive organic resin layer is used, the number of resist masks can be reduced and the process is simplified.

The chromatic color is a color except for achromatic colors such as black, gray, and white, and the color filter layer is formed of a material that transmits only colored chromatic light. Red, green, blue, etc. can be used as a chromatic color. Cyan, magenta, yellow, or the like may also be used. "Transmitting only colored pigmented light" means that the transmitted light in the color filter layer has a peak at the wavelength of the colored light. What is necessary is just to control the film thickness of a color filter layer suitably so that it may become an optimal film thickness in consideration of the relationship between the density | concentration of the coloring material to be included, and light transmittance. For example, the thickness of the color filter layer 505 may be 1500 nm or more and 2000 nm or less.

In the light emitting devices shown in FIGS. 7B and 16B, the light emitting element 4513, which is a display element, is electrically connected to the transistor 4010 or the transistor 4040 provided in the pixel portion 4002. The configuration of the light emitting element 4513 is not limited to a structure in which the first electrode layer 4030, the electroluminescent layer 4511, and the second electrode layer 4031 are stacked as shown in the drawing. The configuration of the light emitting element 4513 can be appropriately changed in accordance with the direction of light to be extracted from the light emitting element 4513.

The partitions 4510 and 507 are formed using an organic insulating material or an inorganic insulating material. In particular, it is preferable to form partition walls using a photosensitive resin material, to form openings on the first electrode layers 4030 and 541, and to form sidewalls of the openings so as to be inclined surfaces having a continuous curvature.

The electroluminescent layers 4511 and 542 may be constituted by a single layer or may be configured so that a plurality of layers are stacked.

A protective film may be formed on the second electrode layers 4031 and 543 and the partitions 4510 and 507 to prevent oxygen, hydrogen, moisture, carbon dioxide, or the like from penetrating into the light emitting elements 4513 and 540. As the protective film, a silicon nitride film, a silicon nitride oxide film, a DLC film, or the like can be formed.

In addition, a layer containing an organic compound covering the light emitting elements 4513 and 540 may be formed by a vapor deposition method so that oxygen, hydrogen, moisture, carbon dioxide, or the like does not enter the light emitting elements 4513 and 540.

In addition, a filler 4414 is formed and sealed in the space sealed by the glass substrate 4001, the substrate 4006, and the seal member 4005. Thus, it is preferable to package (seal) the light emitting element 4513 with a protective film (bonding film, an ultraviolet curable resin film, etc.) or a cover material with high airtightness and few degassing so that it is not exposed to external air.

As the filler 4514, in addition to an inert gas such as nitrogen or argon, an ultraviolet curable resin or a thermosetting resin can be used, and PVC (polyvinyl chloride), acrylic resin, polyimide resin, epoxy resin, silicone resin, PVB (polyvinyl butyral), or EVA (ethylene vinyl acetate) can be used. For example, nitrogen may be used as a filler.

In addition, if necessary, an optical film such as a polarizing plate or a circular polarizing plate (including an elliptical polarizing plate), a retardation plate (λ / 4 wave plate, a λ / 2 wave plate), and a color filter may be appropriately provided on the emitting surface of the light emitting element. Also good. In addition, an anti-reflection film may be provided on the polarizing plate or the circular polarizing plate. For example, anti-glare treatment may be performed to diffuse reflected light according to unevenness of the surface to reduce glare.

It is also possible to provide an electronic paper for driving the electronic ink as the display device. Electronic paper is also called an electrophoretic display (electrophoretic display), has the advantage of being able to read like a paper, and has the advantage of low power consumption, thin and light shape compared to other display devices.

As an electrophoretic display device, various forms can be considered, but a plurality of microcapsules containing a first particle having a positive charge and a second particle having a negative charge are dispersed in a solvent or a solute. By applying an electric field to the microcapsules, the particles in the microcapsules are moved in opposite directions to display only the color of the particles collected on one side. The first particle or the second particle contains a dye and does not move when there is no electric field. In addition, the color of a 1st particle | grain and the color of a 2nd particle shall be different colors (including colorlessness).

As such, the electrophoretic display is a display using a so-called dielectric electrophoretic effect, in which a material having a high dielectric constant moves to a high electric field region.

The dispersion of the microcapsules in a solvent is called an electronic ink, which can be printed on the surface of glass, plastic, fabric, paper, and the like. Moreover, color display is also possible by using the particle | grains which have a color filter or a pigment | dye.

As the first particles and the second particles in the microcapsules, one kind of material selected from a conductor material, an insulator material, a semiconductor material, a magnetic material, a liquid crystal material, a ferroelectric material, an electroluminescent material, an electrochromic material, and a magnetophoretic material What is necessary is just to form using the material which mixed these.

Moreover, the display apparatus which uses the twist ball display system as an electronic paper is also applicable. The twisted ball display method is arranged between the first electrode layer and the second electrode layer, which are electrode layers used for display elements, of the spherical particles colored in white and black, respectively, and generates a potential difference between the first electrode layer and the second electrode layer to produce spherical particles. By controlling the direction, the display is performed.

In addition, in FIGS. 5A-7B and 15A-16B, as a glass substrate 4001 and 500 and the board | substrate 4006, the board | substrate which has flexibility can also be used, for example, the plastic which has transparency Substrates and the like can be used. As the plastic, a fiberglass-reinforced plastics (FRP) plate, a polyvinyl fluoride (PVF) film, a polyester film or an acrylic resin film can be used. If light transmittance is not required, a metal substrate (metal film) such as aluminum or stainless steel may be used. For example, the sheet | seat of the structure which interposed aluminum foil between PVF film or a polyester film can also be used.

In this embodiment, an aluminum oxide film is used as the insulating film 4020. The insulating film 4020 can be formed by sputtering or plasma CVD.

The aluminum oxide film formed as the insulating film 4020 on the oxide semiconductor film has a high blocking effect (block effect) to prevent the film from permeating to both impurities such as hydrogen and moisture and oxygen.

Therefore, in the aluminum oxide film, impurities such as hydrogen and water, which are factors of variation in electrical characteristics, are mixed into the oxide semiconductor film during the fabrication process and after the fabrication, and oxygen, which is a main component material constituting the oxide semiconductor, is released from the oxide semiconductor film. It functions as a protective film that prevents the damage.

As the insulating films 4021 and 506 functioning as planarization insulating films, organic materials having heat resistance such as acrylic resins, polyimide resins, benzocyclobutene resins, polyamide resins, epoxy resins and the like can be used. In addition to the above organic materials, a low dielectric constant material (low-k material), siloxane-based resin, PSG (phosphorous glass), BPSG (boron glass) and the like can be used. In addition, the insulating film may be formed by stacking a plurality of insulating films formed of these materials.

The method of forming the insulating films 4021 and 506 is not particularly limited, and depending on the material, the sputtering method, the spin coating method, the dip method, the spray coating method, the droplet ejection method (inkjet method, etc.), the printing method (screen printing, offset printing, etc.), Doctor knife, roll coater, curtain coater, knife coater and the like can be used.

The display device transmits light from a light source or a display element to perform display. Therefore, all the thin films, such as a board | substrate, an insulating film, and a conductive film which are formed in the pixel part through which light permeate | transmits, shall be translucent to permeate | transmit the light of the wavelength range of visible light.

In the first electrode layer and the second electrode layer (also referred to as a pixel electrode layer, a common electrode layer, a counter electrode layer, etc.) for applying a voltage to the display element, the light transmittance may vary depending on the direction of light to be extracted, the place where the electrode layer is provided, and the pattern structure of the electrode layer. It is good to select reflectivity.

The first electrode layers 4030 and 541 and the second electrode layers 4031 and 543 are indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide and indium tin oxide containing titanium oxide. Conductive materials having light transmissivity, such as oxides, indium tin oxides, indium zinc oxides, and indium tin oxides added with silicon oxide and graphene, can be used.

In addition, the first electrode layers 4030 and 541 and the second electrode layers 4031 and 543 may include tungsten (W), molybdenum (Mo), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), Metals such as tantalum (Ta), chromium (Cr), cobalt (Co), nickel (Ni), titanium (Ti), platinum (Pt), aluminum (Al), copper (Cu), silver (Ag), or these It can be formed using one kind or plural kinds of alloys of these or these metal nitrides.

In the present embodiment, since the light emitting devices shown in Figs. 6A, 6B, 15A, and 15B are bottom injection type, the first electrode layer 541 is transparent and the second electrode layer 543 is reflective. Therefore, when the metal film is used for the first electrode layer 541, the film thickness is made thin enough to maintain the light transmittance, and when the conductive film having the light transmissivity is used for the second electrode layer 543, the reflective conductive film is laminated. good.

The first electrode layers 4030 and 541 and the second electrode layers 4031 and 543 can be formed using a conductive composition containing a conductive polymer (also called a conductive polymer). As the conductive polymer, a so-called π-electron conjugated conductive polymer can be used. For example, polyaniline or derivatives thereof, polypyrrole or derivatives thereof, polythiophene or derivatives thereof, or a copolymer consisting of two or more of aniline, pyrrole and thiophene or derivatives thereof and the like can be given.

In addition, since the transistor is easily broken due to static electricity or the like, it is preferable to provide a protection circuit for protecting the driving circuit. It is preferable to comprise a protection circuit using a nonlinear element.

As described above, the semiconductor device having various functions can be provided by applying the transistors described in any one of the first to sixth embodiments.

The structure, method, etc. which were shown in this embodiment can be used suitably in combination with the structure, method, etc. which are shown in another embodiment.

(Embodiment 8)

The semiconductor device which has an image sensor function which reads the information of a target object can be manufactured using the transistor shown in any one of Embodiment 1-6.

8A, 8B, 17A, and 17B show an example of a semiconductor device having an image sensor function. 8A and 17A are equivalent circuits of the photo sensor, and FIGS. 8B and 17B are sectional views showing a part of the photo sensor.

In the photodiode 602, one electrode is connected to the photodiode reset signal line 658, and the other electrode is electrically connected to the transistor 640 or the gate of the transistor 1640. The transistor 640 or the transistor 1640 has one of a source and a drain electrically connected to the photo sensor reference signal line 672, and the other of the source and the drain is one of the source and the drain of the transistor 656 or the transistor 1656. It is electrically connected to one. The transistor 656 or transistor 1656 has a gate electrically connected to the gate signal line 659, and the other of the source and the drain is electrically connected to the photo sensor output signal line 671.

In the circuit diagram of the present specification, the symbol of the transistor using the oxide semiconductor film is described as 'OS' so that the transistor can be clearly identified as a transistor using the oxide semiconductor film. In the present embodiment, the transistors 640, 656, 1640, and 1656 can use the transistors described in any one of the first to sixth embodiments, and an oxide semiconductor film is used. It is a transistor. 8A and 8B show an example in which a transistor having the same structure as the transistor 430 shown in Embodiment 2 is applied, and FIGS. 17A and 17B have the same structure as the transistor 1430 shown in Embodiment 5. An example in which a transistor is applied is shown. The transistors 640 and 1640 are staggered transistors of a lower gate structure provided with an insulating layer serving as a channel protective film on the oxide semiconductor film.

FIG. 8B is a cross-sectional view of the photodiode 602 and the transistor 640 included in the photosensor, and the photodiode 602 and the transistor 640 are provided on the glass substrate 601 as a sensor. The substrate 613 is provided on the photodiode 602 and the transistor 640 by using an adhesive layer 608.

The gate electrode layer of the transistor 640 is covered with the first gate insulating layer 636, and a thin nitride insulating layer may be used for the first gate insulating layer 636. For example, a silicon nitride film, a silicon nitride oxide film, etc. are mentioned. The film thickness of the first gate insulating film 636 can be thin, and can be 30 nm or more and 50 nm or less. The first gate insulating film 636 may be either a single layer structure or a stacked structure. In this embodiment, a silicon nitride film is used as the first gate insulating film 636.

FIG. 17B is a cross-sectional view of the photodiode 602 and the transistor 1640 included in the photosensor, wherein the photodiode 602 and the transistor 1640 functioning as sensors on the glass substrate 601 provided with the protective insulating film 646. It is provided. The substrate 613 is provided on the photodiode 602 and the transistor 1640 by using an adhesive layer 608.

A nitride insulating film can be used for the protective insulating film 646. For example, a silicon nitride film, a silicon nitride oxide film, etc. are mentioned. The protective insulating film 646 may be either a single layer structure or a laminated structure. In this embodiment, a silicon nitride film is used as the protective insulating film 646.

An insulating film 631, an interlayer insulating film 633, and an interlayer insulating film 634 are provided on the transistor 640 or the transistor 1640. The photodiode 602 is provided on the interlayer insulating film 633, and is interposed between the electrode layers 641a and 641b formed on the interlayer insulating film 633 and the electrode layer 642 provided on the interlayer insulating film 634. It has a structure which laminated | stacked the 1st semiconductor film 606a, the 2nd semiconductor film 606b, and the 3rd semiconductor film 606c sequentially from the side.

The electrode layer 641b is electrically connected to the conductive layer 643 formed on the interlayer insulating film 634, and the electrode layer 642 is electrically connected to the conductive layer 645 via the electrode layer 641a. The conductive layer 645 is electrically connected to the transistor 640 or the gate electrode layer of the transistor 1640, and the photodiode 602 is electrically connected to the transistor 640 or the transistor 1640.

Here, a semiconductor film having a p-type conductivity as the first semiconductor film 606a, a high resistance semiconductor film (I-type semiconductor film) as the second semiconductor film 606b, and an n-type as the third semiconductor film 606c. An example of a pin type photodiode for laminating semiconductor films having a conductive type is given.

The first semiconductor film 606a is a p-type semiconductor film and can be formed of an amorphous silicon film containing an impurity element imparting a p-type. The first semiconductor film 606a is formed by a plasma CVD method using a semiconductor material gas containing a group 13 impurity element (for example, boron (B)). As the semiconductor material gas, silane (SiH ₄ ) may be used. Alternatively, Si ₂ H ₆ , SiH ₂ Cl ₂ , SiHCl ₃ , SiCl ₄ , SiF _4, or the like may be used. After the amorphous silicon film containing no impurity element is formed, the impurity element may be introduced into the amorphous silicon film by the diffusion method or the ion implantation method. The impurity element may be diffused by introducing the impurity element by ion implantation or the like, followed by heating. In this case, the LPCVD method, the vapor phase growth method, the sputtering method, or the like may be used as a method of forming the amorphous silicon film. It is preferable to form the 1st semiconductor film 606a so that film thickness may be 10 nm or more and 50 nm or less.

The second semiconductor film 606b is an I-type semiconductor film (intrinsic semiconductor film), and is formed of an amorphous silicon film. As the second semiconductor film 606b, an amorphous silicon film is formed by a plasma CVD method using a semiconductor material gas. As the semiconductor material gas, silane (SiH ₄ ) may be used. Alternatively, Si ₂ H ₆ , SiH ₂ Cl ₂ , SiHCl ₃ , SiCl ₄ , SiF _4, or the like may be used. The second semiconductor film 606b may be formed by the LPCVD method, the vapor phase growth method, the sputtering method, or the like. It is preferable to form the second semiconductor film 606b so that the film thickness is 200 nm or more and 1000 nm or less.

The third semiconductor film 606c is an n-type semiconductor film and is formed of an amorphous silicon film containing an impurity element imparting n-type. The third semiconductor film 606c is formed by a plasma CVD method using a semiconductor material gas containing a group 15 impurity element (for example, phosphorus (P)). As the semiconductor material gas, silane (SiH ₄ ) may be used. Alternatively, Si ₂ H ₆ , SiH ₂ Cl ₂ , SiHCl ₃ , SiCl ₄ , SiF _4, or the like may be used. After the amorphous silicon film containing no impurity element is formed, the impurity element may be introduced into the amorphous silicon film by the diffusion method or the ion implantation method. The impurity element may be diffused by introducing the impurity element by ion implantation or the like, followed by heating. In this case, the LPCVD method, the vapor phase growth method, the sputtering method, or the like may be used as a method of forming the amorphous silicon film. The film thickness of the third semiconductor film 606c is preferably formed to be 20 nm or more and 200 nm or less.

In addition, the first semiconductor film 606a, the second semiconductor film 606b, and the third semiconductor film 606c may be formed using a polycrystalline semiconductor instead of an amorphous semiconductor, and may be a microcrystalline semiconductor (Semi Amorphous Semiconductor). Semiconductor (SAS)) may be used.

In addition, since the mobility of holes generated by the photoelectric effect is very small compared to the mobility of electrons, the pin-type photodiode exhibits a better characteristic of making the p-type semiconductor film side the light-receiving surface. Here, the example which converts the light which the photodiode 602 receives from the surface of the glass substrate 601 in which the pin type photodiode was formed into an electrical signal is shown. In addition, since light from the semiconductor film side having a conductivity type opposite to the semiconductor film side serving as the light receiving surface becomes external light, a conductive film having light shielding properties may be used as the electrode layer. The n-type semiconductor film side can also be used as the light receiving surface.

The insulating film 631, the interlayer insulating film 633, and the interlayer insulating film 634 can be formed using an insulating material, and depending on the material, the sputtering method, the plasma CVD method, the spin coating method, the dip method, the spray coating method, and the droplets can be formed. It can form using a discharge method (ink-jet method etc.), a printing method (screen printing, offset printing, etc.).

When an inorganic insulating material is used as the insulating film 631, an oxide insulating film such as a silicon oxide layer, a silicon oxynitride layer, an aluminum oxide layer, or an aluminum oxynitride layer, a silicon nitride layer, a silicon nitride oxide layer, an aluminum nitride layer, or A single layer or a lamination of a nitride insulating film such as an aluminum nitride oxide layer can be used.

In this embodiment, an aluminum oxide film is used as the insulating film 631. The insulating film 631 can be formed by sputtering or plasma CVD.

The aluminum oxide film formed as the insulating film 631 on the oxide semiconductor film has a high effect of blocking the film from permeating both the impurities such as hydrogen, moisture, and oxygen to prevent the film from permeating.

Therefore, in the aluminum oxide film, impurities such as hydrogen and water, which are factors of variation in characteristics, are mixed into the oxide semiconductor film and oxygen released from the oxide semiconductor film as a main component material constituting the oxide semiconductor is produced during and after the manufacturing process. It functions as a protective film to prevent.

As the interlayer insulating films 633 and 634, it is preferable to use insulating films that function as planarization insulating films in order to reduce surface irregularities. As the interlayer insulating films 633 and 634, for example, an organic insulating material having heat resistance such as polyimide resin, acrylic resin, benzocyclobutene resin, polyamide resin, epoxy resin or the like can be used. In addition to the above organic insulating material, a single layer or lamination such as low dielectric constant material (low-k material), siloxane resin, PSG (phosphorus glass), BPSG (phosphorus boron glass), or the like can be used.

By detecting the light 622 incident on the photodiode 602, the information of the detected object can be read. In addition, when reading the information to be detected, a light source such as a backlight can be used.

The gate electrode layer of the transistor 640 is covered with the first gate insulating film 636 so that the second gate insulating film and the oxide semiconductor film of the transistor 640 are protected from contamination by the first metal element contained in the glass substrate 601. have. Therefore, at the interface between the first gate insulating film 636 and the second gate insulating film, the concentration of the first metal element contained in the glass substrate 601 is 5 × 10 ¹⁸ atoms / cm ³ or less (preferably 1 × 10 ¹⁸ atoms / cm ³ or less).

The transistor 1640 is provided on the glass substrate 601 covered with the protective insulating film 646, and is protected from contamination due to the second metal element contained in the glass substrate 601. Therefore, at the interface between the gate electrode layer and the gate insulating film of the transistor 1640, the concentration of the second metal element contained in the glass substrate 601 is 5 × 10 ¹⁸ atoms / cm ³ or less (preferably 1 × 10 ^18). atoms / cm ³ or less).

Therefore, a highly reliable semiconductor device including the transistors 640 and 1640 having stable electrical characteristics using the oxide semiconductor film of the present embodiment can be provided. In addition, high productivity can be achieved by manufacturing a highly reliable semiconductor device with high yield.

The structure, method, etc. which were shown in this embodiment can be used suitably in combination with the structure, method, etc. which are shown in another embodiment.

(Embodiment 9)

The semiconductor device described herein can be applied to various electronic devices (including game machines). Examples of the electronic device include a television device (also referred to as a television or a television receiver), a monitor such as a computer, a camera such as a digital camera or a digital video camera, a digital photo frame, a portable telephone, a portable game machine, a portable information terminal, (Pachinko machine, slot machine, etc.), and a housing of a game machine. Specific examples of these electronic devices are shown in Figs. 9A to 9C.

9A shows a table 9000 having a display portion. The table 9000 has a display portion 9003 embedded in the housing 9001 and can display an image on the display portion 9003. In addition, the structure which supported the housing 9001 by the four leg parts 9002 was shown. The housing 9001 also has a power cord 9005 for supplying power.

The semiconductor device described in any one of Embodiments 1 to 8 can be used for the display portion 9003, and can provide high reliability to the table 9000 having the display portion.

The display portion 9003 has a touch input function, and by touching the display button 9004 displayed on the display portion 9003 of the table 9000 with a finger or the like, the screen can be operated or information can be input, and other home appliances By enabling communication with or enabling control, a control device may be used to control other home appliances by screen operation. For example, when the semiconductor device having the image sensor function shown in the eighth embodiment is used, the display portion 9003 can be given a touch input function.

In addition, the screen of the display portion 9003 can be perpendicular to the floor by a hinge formed in the housing 9001, and can also be used as a television device. In a narrow room, the free space becomes narrower when a television device with a large screen is provided. However, if the display unit is built in the table, the space in the room can be effectively used.

9B is a diagram illustrating a television device 9100. The television device 9100 includes a display portion 9103 built into the housing 9101, and may display an image on the display portion 9103. In addition, the structure which supported the housing 9201 by the stand 9905 is shown here.

The television device 9100 can be operated by an operation switch included in the housing 9101 or by a remote controller 9110 provided separately. The operation key 9119 provided by the remote controller 9110 can operate a channel and a volume, and can operate the image displayed on the display portion 9103. It is also possible to provide a configuration in which the display unit 9107 for displaying the information output from the remote controller 9110 is provided to the remote controller 9110.

The television device 9100 illustrated in FIG. 9B includes a receiver, a modem, and the like. The television apparatus 9100 can receive a general television broadcast by a receiver, and can be connected to a communication network by wire or wireless via a modem, and is one-way (from sender to receiver) or two-way (between sender and receiver, or between receivers, etc.). Information communication).

The semiconductor device described in any one of Embodiments 1 to 8 can be used for the display portions 9103 and 9107, and can provide high reliability to televisions and remote controllers.

9C is a computer, and includes a main body 9201, a housing 9202, a display portion 9203, a keyboard 9304, an external connection port 9205, a pointing device 9206, and the like.

The semiconductor device described in any one of Embodiments 1 to 8 can be used for the display portion 9203, and can provide high reliability to a computer.

10A and 10B are foldable tablet terminals. 10A illustrates an expanded state, the tablet terminal includes a housing 9630, a display portion 9631a, a display portion 9631b, a display mode switch 9034, a power switch 9035, and a power saving mode switch 9036. , A hook 9033 and an operation switch 9038.

The semiconductor device described in any one of Embodiments 1 to 8 can be used for the display portions 9631a and 9631b, and can be a highly reliable tablet terminal.

The display portion 9631a can make a part of the touch panel area 9632a and can input data by touching the displayed operation key 9638. In addition, although the figure which showed the structure which only one half of an area | region has a function which only displays in the display part 9331a as an example and the other half of the area | region has a touch panel function is shown, it is not limited to this structure. All regions of the display portion 9631a may have a function of a touch panel. For example, the display portion 9631b can be used as a display screen as a touch panel in which a keyboard button is displayed on the entire surface of the display portion 9631a.

In addition, in the display portion 9631b, a portion of the display portion 9631b may be a region 9432b of the touch panel similarly to the display portion 9631a. Further, a keyboard button can be displayed on the display portion 9631b by touching a position where the keyboard display switching button 9639 of the touch panel is displayed with a finger, a stylus, or the like.

In addition, touch input may be simultaneously performed on the area 9432a of the touch panel and the area 9432b of the touch panel.

In addition, the display mode changeover switch 9034 can switch display directions such as vertical display or horizontal display, and can switch monochrome display or color display. The power saving mode switching switch 9036 can optimize the brightness of the display according to the amount of external light in use detected by the optical sensor built into the tablet terminal. The tablet terminal may include not only an optical sensor but also other detection devices such as a gyro, an acceleration sensor, and a sensor for detecting a tilt.

In addition, although the display area of the display part 9631b and the display part 9631a showed the same example in FIG. 10A, it is not specifically limited to this, It may differ in size, and may differ in display quality. For example, the display panel may be a display panel in which one side is more rigid than the other side.

FIG. 10B shows a closed state, and the tablet terminal has a housing 9630, a solar cell 9633, a charge / discharge control circuit 9634, a battery 9635, and a DCDC converter 9636. 10B is a diagram showing a configuration having a battery 9635 and a DCDC converter 9636 as an example of the charge / discharge control circuit 9634.

In addition, since the tablet terminal can be folded, the housing 9630 can be closed when not in use. Therefore, since the display portion 9631a and the display portion 9631b can be protected, it is possible to provide a tablet terminal having excellent durability and excellent reliability even in view of long-term use.

In addition, the tablet terminal illustrated in FIGS. 10A and 10B further includes a function of displaying various information (still images, moving images, text images, etc.), a function of displaying a calendar, a date, or a time on a display unit, and a display unit. And a touch input function for touch input manipulation or editing of a piece of information, a function for controlling processing by various software (programs), and the like.

Power can be supplied to the touch panel, the display unit, the image signal processing unit, or the like by the solar battery 9633 mounted on the surface of the tablet terminal. In addition, the solar cell 9633 can be provided on one side or both sides of the housing 9630, and the battery 9635 can be efficiently charged. In addition, the use of a lithium ion battery as the battery 9635 has advantages such as miniaturization.

The configuration and operation of the charge / discharge control circuit 9634 illustrated in FIG. 10B will be described with reference to the block diagram of FIG. 10C. FIG. 10C shows a solar cell 9633, a battery 9635, a DCDC converter 9636, a converter 9637, a switch SW1 to a switch SW3, and a display portion 9631, and a battery 9633 and a DCDC. Converter 9636, converter 9637, switches SW1 to SW3 are portions corresponding to the charge / discharge control circuit 9634 shown in FIG. 10B.

First, an operation example in the case of generating power by the solar cell 9633 using external light will be described. The power generated by the solar cell 9633 is stepped up or down by the DCDC converter 9636 so as to be a voltage for charging the battery 9635. When the electric power from the solar cell 9633 is used for the operation of the display portion 9631, the switch SW1 is turned on, and the converter 9637 performs the voltage raising or lowering to the voltage required for the display portion 9631. . When the display portion 9631 does not perform display, the switch SW1 may be turned off and the switch SW2 may be turned on to charge the battery 9635.

Although the solar cell 9633 has been presented as an example of power generation means, the configuration is not particularly limited, and the battery 9635 may be charged by other power generation means such as a piezoelectric element (piezo element) or a thermoelectric conversion element (Peltier element). good. For example, a configuration may be employed in which a non-contact power transmission module that transmits and receives power by radio (noncontact) or other charging means is combined.

The structure, the method, etc. which were shown in this embodiment can be used suitably in combination with the structure, the method, etc. which are shown in another embodiment.

400: glass substrate
401: gate electrode layer
402: gate insulating film
403: oxide semiconductor film
405a: source electrode layer
405b: drain electrode layer
407: insulating film
413: insulation layer
420: transistor
423: insulation layer
425a: opening
425b: opening
430 transistor
436: gate insulating film
440 transistor
450: protective insulating film
452: gate insulating film
500: glass substrate
501: gate insulating film
502: gate insulating film
503: insulation layer
504: interlayer insulating film
505: color filter layer
506: insulating film
507: bulkhead
510: transistor
511a: gate electrode layer
511b: gate electrode layer
512: oxide semiconductor film
513a: conductive layer
513b: conductive layer
520: capacitive element
521a: conductive layer
521b: conductive layer
522: oxide semiconductor film
523: conductive layer
530: wiring layer intersection
533: conductive layer
540: light emitting element
541: electrode layer
542 electroluminescent layer
543: electrode layer
550: protective insulating film
592: gate insulating film
601 glass substrate
602 photodiode
606a: semiconductor film
606b: semiconductor film
606c: semiconductor film
608: adhesive layer
613: substrate
622: light
631: insulating film
633: interlayer insulating film
634: interlayer insulating film
636: gate insulating film
646: protective insulating film
640: transistor
641a: electrode layer
641b: electrode layer
642: electrode layer
643: conductive layer
645: conductive layer
656: transistor
658 photodiode reset signal line
659: gate signal line
671: photo sensor output signal line
672: photo sensor reference signal line
1420: transistor
1430: transistor
1440: transistor
1510: transistor
1520: capacitive element
1530: wiring layer intersection
1640: transistor
1656: transistor
4001: glass substrate
4002: pixel portion
4003: signal line driver circuit
4004: scan line driving circuit
4005: seal material
4006: substrate
4008: liquid crystal composition
4010: transistor
4011: transistor
4013: liquid crystal element
4015: connecting terminal electrode
4016: terminal electrode
4018: FPC
4018a: FPC
4018b: FPC
4019: anisotropic conductive film
4020: Insulating film
4021: insulating film
4023: gate insulating film
4030: electrode layer
4031: electrode layer
4032: insulating film
4033: insulating film
4035: spacer
4040: transistor
4041: transistor
4053: protective insulating film
4510: bulkhead
4511: EL layer
4513: light emitting element
4514: filler
9000: table
9001: housing
9002: leg
9003: display unit
9004: Show button
9005: power cord
9033: Hooks
9034: Switches
9035: Power switch
9036: Switches
9038: Operation switch
9100: television device
9101: housing
9103: display unit
9105: stand
9107 display
9109: operation keys
9110: remote controller
9201: main body
9202: housing
9203: display unit
9204: keyboard
9205: External connection port
9206: pointing device
9630: Housing
9631:
9631a:
9631b:
9632a: area
9632b: area
9633: Solar cell
9634: charge / discharge control circuit
9635: Battery
9636: DCDC Converter
9637: Converter
9638: Operation keys
9639: Button

Claims (12)

In the semiconductor device,
A gate electrode layer on the glass substrate containing at least one metal element;
A first gate insulating film on the gate electrode layer;
A second gate insulating film in contact with the first gate insulating film;
An oxide semiconductor film on the second gate insulating film;
A source electrode layer and a drain electrode layer on the oxide semiconductor film;
The composition of the first gate insulating film is different from that of the second gate insulating film,
The semiconductor device at the interface between the first gate insulating film and the second gate insulating film, wherein the concentration of the at least one metal element is 5 × 10 ¹⁸ atoms / cm ³ or less. The method of claim 1,
Further comprising an insulating layer in contact with the oxide semiconductor film,
And the source electrode layer and the drain electrode layer are formed on the oxide semiconductor film and the insulating layer. The method of claim 1,
And the first gate insulating film is a nitride insulating film. The method of claim 1,
And the first gate insulating film is a silicon nitride film or a silicon nitride oxide film. The method of claim 1,
Wherein said at least one metal element is selected from sodium, aluminum, magnesium, calcium, strontium, and barium. The method of claim 1,
The second gate insulating film may be a silicon oxide film, a gallium oxide film, an aluminum oxide film, a silicon nitride film, a silicon oxynitride film, an aluminum oxynitride film, a silicon nitride oxide film, a hafnium oxide film, a yttrium oxide film, a hafnium silicate film, or nitrogen. A semiconductor device selected from a hafnium silicate film, a hafnium aluminate film, and a lanthanum oxide film. In the semiconductor device,
A protective insulating film on the glass substrate containing at least one metal element;
A gate electrode layer on the protective insulating film;
A gate insulating film on the gate electrode layer;
An oxide semiconductor film on the gate insulating film;
A source electrode layer and a drain electrode layer on the oxide semiconductor film;
The composition of the protective insulating film is different from the composition of the gate insulating film,
At the interface between the gate electrode layer and the gate insulating film, the concentration of the at least one metal element is 5 × 10 ¹⁸ atoms / cm ³ or less. The method of claim 7, wherein
Further comprising an insulating layer in contact with the oxide semiconductor film,
And the source electrode layer and the drain electrode layer are formed on the oxide semiconductor film and the insulating layer. The method of claim 7, wherein
The protective insulating film is a semiconductor insulating film. The method of claim 7, wherein
And the protective insulating film is a silicon nitride film or a silicon nitride oxide film. The method of claim 7, wherein
Wherein said at least one metal element is selected from sodium, aluminum, magnesium, calcium, strontium, and barium. The method of claim 7, wherein
The gate insulating film contains a silicon oxide film, a gallium oxide film, an aluminum oxide film, a silicon nitride film, a silicon oxynitride film, an aluminum oxynitride film, a silicon nitride oxide film, a hafnium oxide film, a yttrium oxide film, a hafnium silicate film, and nitrogen. A semiconductor device selected from one of a hafnium silicate film, a hafnium aluminate film, and a lanthanum oxide film.

Images