JP2011049297A - Method of manufacturing thin film transistor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a field-effect transistor which is highly reliable by providing a gate insulating layer having high adhesion to a substrate. <P>SOLUTION: In a method of manufacturing a thin film transistor, at least a gate electrode, a gate insulating layer, a semiconductor layer containing an oxide, a source electrode, and a drain electrode are provided on an insulating substrate, and the gate insulating layer is formed by laminating a lower gate insulating layer coming into contact with the insulating substrate and one or more upper gate insulating layers formed on the lower gate insulating layer, wherein the lower gate insulating layer is formed by an ion beam sputtering method. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

The present invention relates to a method for manufacturing a thin film transistor.

At present, a general flat panel display (FPD) is driven by an active matrix of a field effect transistor using amorphous silicon or polycrystalline silicon as an active layer.

On the other hand, in recent years, attempts have been made to use a flexible substrate instead of a glass substrate in order to further reduce the thickness, weight, and breakage resistance of an FPD.

However, the manufacture of the above-described transistor using a silicon thin film requires a relatively high temperature thermal process and is generally difficult to form directly on a flexible substrate having low heat resistance.

Thus, development of a thin film transistor using an oxide semiconductor that can be formed at a low temperature as an active layer has been actively performed (Patent Document 1).

As the gate insulating layer of the thin film transistor using the above-described oxide semiconductor as an active layer, for example, a single film of silicon oxide, silicon nitride, aluminum oxide or the like formed by magnetron sputtering or a film in which these films are stacked is used. (Patent Document 2).

However, since the gate insulating layer formed by the magnetron sputtering method has low adhesion to the substrate, there is a problem that the gate insulating film is easily peeled off from the substrate and a highly reliable thin film transistor cannot be obtained.

JP 2006-165532 A Japanese Patent Laid-Open No. 2007-73697

Accordingly, an object of the present invention is to provide a highly reliable field effect transistor by providing a gate insulating layer having high adhesion to a substrate in order to solve the above-described requirements.

The present invention has been made to achieve the above object, and the invention according to claim 1 is provided with at least a gate electrode, a gate insulating layer, a semiconductor layer containing an oxide, a source electrode and a drain electrode on an insulating substrate. The gate insulating layer is a method of manufacturing a thin film transistor comprising a lower gate insulating layer in contact with the insulating substrate and one or more upper gate insulating layers formed on the lower gate insulating layer. A method of manufacturing a thin film transistor, wherein the lower gate insulating layer is formed by ion beam sputtering.

The invention according to claim 2 is characterized in that at least one layer of the lower gate insulating layer contains any one compound of silicon oxide, silicon nitride, silicon oxynitride, and aluminum oxide. It is a manufacturing method of a thin film transistor.

The invention according to claim 3 is the method of manufacturing a thin film transistor according to claim 1 or 2, wherein at least one of the upper gate insulating layers is formed by magnetron sputtering.

According to a fourth aspect of the present invention, in the thin film transistor manufacturing method according to the first or second aspect, at least one of the upper gate insulating layers is formed by a CVD method.

The invention according to claim 5 is the method of manufacturing a thin film transistor according to claim 1 or 2, wherein at least one of the upper gate insulating layers is formed by a coating method.

The invention according to claim 6 is characterized in that at least one of the upper gate insulating layers contains any one compound of silicon oxide, silicon nitride, silicon oxynitride, and aluminum oxide. The manufacturing method of the thin-film transistor in any one.

The invention according to claim 7 is characterized in that at least one layer of the upper gate insulating layer contains any one compound of polyacrylate, polyvinyl alcohol, polystyrene, polyimide, polyester, epoxy, polyvinyl phenol, and polyvinyl alcohol. It is a manufacturing method of the thin-film transistor of Claim 6.

The invention according to claim 8 is the method for manufacturing a thin film transistor according to any one of claims 1 to 7, wherein the film thickness of the lower gate insulating layer is 10 nm or more and 200 nm or less.

The invention according to claim 9 is the method of manufacturing a thin film transistor according to any one of claims 1 to 8, wherein the semiconductor layer containing an oxide contains at least one of In, Ga, and Zn.

The invention according to claim 10 is the method of manufacturing a thin film transistor according to any one of claims 1 to 9, wherein the insulating substrate is a flexible substrate.

According to the method for manufacturing a thin film transistor of the present invention, it is possible to manufacture a highly reliable thin film transistor in which an insulating layer is hardly peeled off from a substrate and exhibits good transistor characteristics. A film formed using the ion beam sputtering method exhibits higher adhesion to an insulating substrate, particularly a flexible substrate, than a film formed using a magnetron sputtering method or the like. Accordingly, at least a gate electrode, a gate insulating layer, a semiconductor layer containing an oxide, a source electrode and a drain electrode are provided over the insulating substrate, the lower gate insulating layer in contact with the insulating substrate, and the lower gate insulating layer A thin film transistor including at least one upper gate insulating layer stacked on the substrate can be obtained by forming the lower gate insulating layer by ion beam sputtering so that the gate insulating layer does not easily peel from the substrate. it can.

When at least one of the lower gate insulating layer or the upper gate insulating layer of the gate insulating layer contains any one compound of silicon oxide, silicon nitride, silicon oxynitride, and aluminum oxide, sufficient insulation is exhibited. Gate leakage current is suppressed.

Since film formation by ion beam sputtering is slow, the lower gate insulating layer of the gate insulating layer is made thin by ion beam sputtering and then made of an inorganic material as shown above by magnetron sputtering or the like. Forming the upper gate insulating layer at a high speed is effective in reducing the manufacturing cost.

When the upper gate insulating layer of the gate insulating layer is in contact with the semiconductor layer, the upper gate insulating layer in contact with the semiconductor is formed using a CVD method, which can form a denser film than the ion beam sputtering method. This is an effective means for improving the transistor characteristics.

Since film formation by ion beam sputtering is slow, the upper gate insulating layer is formed by a coating method that does not require vacuum holding after the lower gate insulating layer of the gate insulating layer is thinly formed by ion beam sputtering. Filming is effective in reducing the manufacturing cost.

Alternatively, at least one layer of the upper gate insulating layer contains a compound of any one of polyacrylate, polyvinyl alcohol, polystyrene, polyimide, polyester, epoxy, polyvinyl phenol, and polyvinyl alcohol, thereby exhibiting sufficient insulation, and the gate. Leakage current is suppressed.

When the thickness of the lower gate insulating layer of the gate insulating layer is 10 nm or more, island-like growth can be suppressed and a film that completely covers the entire substrate can be formed. In addition, when the thickness of the lower gate insulating layer of the gate insulating layer is 200 nm or less, an increase in the stress of the film can be suppressed, and a film that does not easily peel can be formed. Films deposited by ion beam sputtering have higher stress than films deposited by magnetron sputtering or CVD, and it has been confirmed that film peeling occurs due to increased film stress due to increased film thickness. Yes. In addition, when a plastic substrate or the like is used as the substrate, it has been confirmed that the substrate warps due to an increase in film stress due to the increase in film thickness.

Further, excellent transistor characteristics can be obtained by using an oxide containing any one of In, Zn, and Ga for the semiconductor layer.

In addition, by using a flexible substrate as the insulating substrate, a thin, lightweight, and flexible thin film transistor can be provided.

1 is a schematic diagram illustrating a structure of a thin film transistor according to an embodiment of the present invention. 1 is a schematic diagram illustrating a structure of a thin film transistor showing an embodiment of the present invention 1 is a schematic diagram illustrating a structure of a thin film transistor showing an embodiment of the present invention The schematic diagram showing the structure of the thin-film transistor of Examples 1-5 Schematic diagram showing the structure of the thin film transistor of Comparative Example 1

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the embodiments, the same components are denoted by the same reference numerals, and redundant description among the embodiments is omitted.

FIG. 1 shows an example of a thin film transistor of the present invention. This is a bottom gate-top contact type thin film transistor in which a gate electrode 11, a gate insulating layer 12, a semiconductor layer 13, a source electrode 14, and a drain electrode 15 are sequentially formed on an insulating substrate 10. The gate insulating layer 12 includes a lower gate insulating layer 12a and an upper gate insulating layer 12b, and the lower gate insulating layer 12a in contact with the insulating substrate is formed by ion beam sputtering.

FIG. 2 shows another example of the thin film transistor of the present invention. This is a bottom gate-bottom contact type thin film transistor in which a gate electrode 11, a gate insulating layer 1, a semiconductor layer 13, a source electrode 14, and a drain electrode 15 are sequentially formed on an insulating substrate 10. The gate insulating layer 12 includes a lower gate insulating layer 12a and an upper gate insulating layer 12b, and the lower gate insulating layer 12a in contact with the insulating substrate is formed by ion beam sputtering.

FIG. 3 shows another example of the thin film transistor of the present invention. A source electrode 14, a drain electrode 15, a semiconductor layer 13, a gate insulating layer 12, and a gate electrode 11 are sequentially formed on an insulating substrate 10 to form a top gate-bottom contact type thin film transistor. The gate insulating layer 12 includes a lower gate insulating layer 12a and an upper gate insulating layer 12b, and the lower gate insulating layer 12a in contact with the insulating substrate is formed by ion beam sputtering.

The structure of the thin film transistor according to the embodiment of the present invention is not limited to the above, and may be a top gate-top contact type structure.

As the insulating substrate 10, for example, a glass or plastic substrate can be used. Examples of the plastic substrate include polymethyl methacrylate, polyacrylate, polycarbonate, polystyrene, polyethylene sulfide, polyethersulfone (PES), polyolefin, polyethylene terephthalate, polyethylene naphthalate (PEN), cycloolefin polymer, polyethersulfene, triphenyl. Acetyl cellulose, polyvinyl fluoride film, ethylene-tetrafluoroethylene copolymer resin, weather resistant polyethylene terephthalate, weather resistant polypropylene, glass fiber reinforced acrylic resin film, glass fiber reinforced polycarbonate, transparent polyimide, fluorine resin, cyclic polyolefin resin Etc. can be used. These substrates can be used alone, or a composite substrate in which two or more kinds are laminated can be used.

A flexible substrate such as a plastic substrate is preferable because a thin, light, and flexible thin film transistor can be obtained. When the manufacturing process includes a heat treatment such as a drying process, PES or PEN is preferable for a plastic substrate in addition to a glass substrate such as quartz having high thermal stability.

The gate electrode 11, the source electrode 14, and the drain electrode 15 of the present invention include indium oxide (In ₂ O ₃ ), tin oxide (SnO ₂ ), zinc oxide (ZnO), cadmium oxide (CdO), and indium cadmium oxide (CdIn ₂ O ₄ ), cadmium tin oxide (Cd ₂ SnO ₄ ), zinc tin oxide (Zn ₂ SnO ₄ ), indium zinc oxide (In—Zn—O), and other oxide materials are preferably used. It is also preferable to add impurities to this oxide material in order to increase conductivity. For example, indium oxide is doped with tin, molybdenum, or titanium, tin oxide is doped with antimony or fluorine, and zinc oxide is doped with indium, aluminum, or gallium. Among these, indium tin oxide (commonly called ITO) in which tin is doped in indium oxide is particularly preferably used because of its low resistivity. In addition, low resistance metal materials such as Au, Ag, Cu, Cr, Al, Mg, and Li are also preferably used. In addition, a laminate of a plurality of conductive oxide materials and low resistance metal materials can be used. In this case, a three-layer structure in which a conductive oxide thin film / metal thin film / conductive oxide thin film is laminated in order in order to prevent oxidation or deterioration with time of the metal material is particularly preferably used. An organic conductive material such as PEDOT (polyethylenedioxythiophene) can also be suitably used. The gate electrode, the source electrode, and the drain electrode may all be the same material, or may be all different materials. However, in order to reduce the number of steps, it is more desirable that the source electrode and the drain electrode are made of the same material. These electrodes are formed by a vacuum deposition method, an ion plating method, a sputtering method, a laser ablation method, plasma CVD (Chemical Vapor Deposition), a photo CVD method, a hot wire CVD method, or the like. In addition, the conductive material described above in an ink form or a paste form can be applied by screen printing, letterpress printing, an ink jet method or the like, and baked, but is not limited thereto.

The gate insulating layer 12 includes a lower gate insulating layer 12a and an upper gate insulating layer 12b. The thickness of the gate insulating layer 12 is preferably 50 nm to 2 μm. The lower gate insulating layer 12a in contact with the insulating substrate 10 of the present invention is formed by ion beam sputtering. As the material, for example, it is particularly preferable to include any one compound of silicon oxide, silicon nitride, silicon oxynitride, and aluminum oxide. Alternatively, it preferably contains any one compound of tantalum oxide, yttrium oxide, hafnium oxide, hafnium aluminate, zirconia oxide, and titanium oxide. The resistance value of the lower gate insulating layer 12a is preferably 10 ¹⁰ Ω · cm or more, and more preferably 10 ¹² Ω · cm or more. When the resistance value is smaller than 10 ¹⁰ Ω · cm, the gate insulating layer as a whole cannot exhibit sufficient insulation, and the gate leakage current increases, so that good device characteristics cannot be obtained.

The thickness of the lower gate insulating layer 12a is preferably 10 nm or more and 200 nm or less. If the thickness is less than 10 nm, there is a possibility that the substrate is not layered but is island-shaped, or the entire substrate cannot be completely covered by unevenness of the substrate. Further, when the thickness is greater than 200 nm, the stress of the film increases, and film peeling occurs. When a plastic substrate is used, there is a problem that the substrate warps.
Even if the film thickness is 10 nm or less or 200 nm or more, this does not hinder the entire substrate if it does not cause problems such as film peeling and substrate warpage.

The upper gate insulating layer 12b of the thin film transistor used in the present invention can be a single layer or a plurality of layers can be stacked. The material of the upper gate insulating layer 12b is not particularly limited as long as it has sufficient insulating properties for suppressing the gate leakage current, but a material having a resistivity of 10 ¹¹ Ω · cm or more is preferable, and more preferably 10 ^14. It is preferable that it is Ω · cm or more.

Examples of the inorganic material include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, yttrium oxide, hafnium oxide, hafnium aluminate, zirconia oxide, and titanium oxide. These materials are used. Thus, sufficient insulation can be obtained to suppress the gate leakage current.

Examples of organic materials include polyacrylates such as PMMA (polymethyl methacrylate), PVA (polyvinyl alcohol), PS (polystyrene), transparent polyimide, polyester, epoxy, polyvinylphenol, polyvinyl alcohol, and the like. By using it, sufficient insulation can be obtained to suppress the gate leakage current.

The upper gate insulating layer 12b is formed using a method such as vacuum deposition, ion plating, magnetron sputtering, laser ablation, plasma CVD, photo CVD, hot wire CVD, spin coating, dip coating, or screen printing. Is done. As these upper gate insulating layers 12b, those whose composition is inclined toward the growth direction of the film can also be suitably used. Manufacturing costs can be reduced by using vacuum deposition methods that allow relatively high-speed deposition, such as vacuum deposition and magnetron sputtering, and deposition methods that do not require vacuum retention, such as spin coating. Become. Further, when the upper gate insulating layer 12b is in contact with a semiconductor, transistor characteristics can be improved by using a film formation method such as a CVD method that can obtain a dense film.

Examples of the semiconductor layer 13 of the thin film transistor used in the present invention include an oxide containing one or more elements of zinc, indium, tin, tungsten, magnesium, and gallium. Well-known materials such as zinc oxide, indium oxide, indium zinc oxide, tin oxide, tungsten oxide, and zinc gallium indium oxide (In—Ga—Zn—O) may be used, but the material is not limited to these. The structure of these materials may be single crystal, polycrystal, microcrystal, crystal / amorphous mixed crystal, nanocrystal scattered amorphous, or amorphous. The thickness of the semiconductor layer is desirably at least 10 nm. If it is smaller than 10 nm, there may occur a problem that a portion where no semiconductor is formed in the film is generated due to island-like growth.

The semiconductor layer 13 is formed by using a sputtering method, a pulse laser deposition method, a vacuum evaporation method, a CVD method, a sol-gel method, or the like, but preferably a sputtering method, a pulse laser deposition method, a vacuum evaporation method, or a CVD method. . Examples of the sputtering method include RF magnetron sputtering method, DC sputtering method, ion beam sputtering method, vacuum deposition includes heating evaporation, electron beam evaporation, ion plating method, and CVD method includes hot wire CVD method and plasma CVD method. It is not limited.

More preferably, the method of forming the semiconductor layer 13 is the same as the layer in contact with the semiconductor layer of the upper gate insulating layer 12b of the gate insulating layer. By performing continuous film formation in the same chamber, a thin film transistor having excellent device characteristics and high reliability can be obtained.

Hereinafter, although this invention is demonstrated using Examples 1-6 and the comparative example 1, it does not restrict to this.

Example 1
In Example 1, a thin film transistor as shown in FIG. 4 was produced.

A 100 nm ITO film was formed on a PEN substrate (Q65 thickness 125 μm manufactured by Teijin DuPont) as an insulating substrate 10 by using a DC magnetron sputtering apparatus, and a gate electrode 11 was formed by etching using a photolithography method. The input power during the ITO film formation was 100 W, the gas flow rate was Ar = 50 SCCM, O ₂ = 0.1 SCCM, and the film formation pressure was 1.0 Pa. Next, a lower gate insulating layer 12a made of SiN was deposited to a thickness of 50 nm using an ion beam sputtering apparatus (target Si, applied voltage 3 kV, gas flow rate N ₂ = 20 SCCM, deposition pressure 0.01 Pa). Thereafter, the upper gate insulating layer 12b made of SiON is formed to 400 nm using an RF magnetron sputtering apparatus (input power is 500 W, gas flow rate Ar = 50 SCCM, O ₂ = 20 SCCM, film forming pressure 1.0 Pa), In—Ga—Zn—O The semiconductor layer 13 made of a system oxide was continuously formed to a thickness of 40 nm (input power 100 W, gas flow rate Ar = 100 SCCM, O ₂ = ₂ SCCM, film formation pressure 1.0 Pa). The substrate temperature during each film formation is room temperature. After the semiconductor layer 13 is formed by etching using a photolithography method, the source electrode 14 and the drain electrode 15 made of Al are formed to a thickness of 100 nm by EB (Electron Beam) deposition using a metal mask, and the thin film transistor element 1 is formed. Obtained. The length between the source / drain electrodes is 0.2 mm, and the width between the source / drain electrodes is 2 mm. The film thickness was measured with a stylus type film thickness meter (Dektak 6M manufactured by ULVAC).

As a result of evaluating the adhesion between the lower gate insulating layer 12a of the thin film transistor element 1 and the insulating substrate 10 by a cross-cut method, no peeling was observed, and good adhesion was shown. The transistor characteristics of the thin film transistor element 1 measured using a semiconductor parameter analyzer (SCS4200 manufactured by Keithley) are as follows. The mobility is 8 cm ² / Vs, and the ON / OFF ratio when a voltage of 10 V is applied between the source / drain electrodes. The gate leakage current at 6 digits when the gate voltage was 20 V was 4.2 × 10 ⁻¹¹ A, showing good transistor characteristics and sufficiently suppressing the gate leakage current.

(Example 2)
In FIG. 4, an element was produced in the same manner as in Example 1 except that the film thickness of the lower gate insulating layer 12a was 200 nm and the film thickness of the upper gate insulating layer 12b was 250 nm, whereby a thin film transistor element 2 was obtained.

As a result of evaluating the adhesiveness in the same manner as in Example 1, no peeling was observed between the lower gate insulating layer 12a of the manufactured thin film transistor element 2 and the insulating substrate 10, and good adhesiveness was shown. The transistor characteristics of the thin film transistor element 2 measured using a semiconductor parameter analyzer (SCS4200 manufactured by Keithley) are the mobility of 6 cm ² / Vs, and the ON / OFF ratio when the voltage of 10 V is applied between the source / drain electrodes is 6 digits. The gate leakage current at a gate voltage of 20 V was 3.5 × 10 ⁻¹¹ A, indicating good transistor characteristics and sufficiently suppressing the gate leakage current.

(Example 3)
In FIG. 4, an element was fabricated in the same manner as in Example 1 except that the thickness of the lower gate insulating layer 12a was 250 nm and the thickness of the upper gate insulating layer 12b was 200 nm, whereby a thin film transistor element 3 was obtained.

As a result of evaluating the adhesiveness in the same manner as in Example 1, no peeling was observed between the lower gate insulating layer 12a and the insulating substrate 10 of the manufactured thin film transistor element 3, and good adhesiveness was shown. The warpage of the substrate due to the film stress was remarkably observed. The transistor characteristics of the thin film transistor element 3 measured using a semiconductor parameter analyzer (SCS4200 manufactured by Keithley) are as follows: the mobility is 7 cm ² / Vs, and the ON / OFF ratio when a voltage of 10 V is applied between the source / drain electrodes is 6 digits. The gate leakage current at a gate voltage of 20 V was 1.1 × 10 ⁻¹¹ A, showing good transistor characteristics and sufficiently suppressing the gate leakage current.

Example 4
In FIG. 4, an element was produced in the same manner as in Example 1 except that the thickness of the lower gate insulating layer 12a was 10 nm and the thickness of the upper gate insulating layer 12b was 440 nm, whereby a thin film transistor element 4 was obtained.

As a result of evaluating the adhesiveness in the same manner as in Example 1, no peeling was observed between the lower gate insulating layer 12a and the insulating substrate 10 of the manufactured thin film transistor element 4, and good adhesiveness was shown. The transistor characteristics of the thin film transistor element 4 measured using a semiconductor parameter analyzer (SCS4200 manufactured by Keithley) are the mobility of 8 cm ² / Vs, and the ON / OFF ratio when the voltage of 10 V is applied between the source / drain electrodes is 6 digits. The gate leakage current at a gate voltage of 20 V was 4.9 × 10 ⁻¹¹ A, showing good transistor characteristics and sufficiently suppressing the gate leakage current.

(Example 5)
In FIG. 4, an element was produced in the same manner as in Example 1 except that a SiO ₂ film was formed as the upper gate insulating layer 12b using a parallel plate type plasma CVD apparatus, and a thin film transistor element 5 was obtained. SiO ₂ was deposited at a substrate temperature of 120 ° C., hexamethyldisiloxane (50 ° C.) at a gas flow rate of 5 SCCM, O ₂ at a gas flow rate of 50 SCCM, an input power of 100 W, and a deposition pressure of 20 Pa.

As a result of evaluating the adhesiveness in the same manner as in Example 1, no peeling was observed between the lower gate insulating layer 12a of the thin film transistor element 5 and the insulating substrate 10, which showed good adhesiveness. The transistor characteristics of the thin film transistor element 5 measured using a semiconductor parameter analyzer (SCS4200 manufactured by Keithley) are a mobility of 9 cm ² / Vs, and the ON / OFF ratio when a voltage of 10 V is applied between the source / drain electrodes is 7 digits. The gate leakage current at a gate voltage of 20 V was 1.0 × 10 ⁻¹¹ A, indicating good transistor characteristics and sufficiently suppressing the gate leakage current.

(Example 6)
In FIG. 4, a device was fabricated in the same manner as in Example 1 except that polyvinyl phenol was deposited as an upper gate insulating layer 12 b with a thickness of 1000 nm using a spin coater and heat treatment was performed at 180 ° C. for 1 hour in the air. Thus, a thin film transistor element 6 was obtained.

As a result of evaluating the adhesion between the lower gate insulating layer 12a of the manufactured thin film transistor element 6 and the insulating substrate 10 by a cross-cut method, no peeling was observed, and good adhesion was shown. In addition, the transistor characteristics of the thin film transistor element 6 measured using a semiconductor parameter analyzer (SCS 4200 manufactured by Keithley) are as follows. The mobility is 1 cm ² / Vs, and the ON / OFF ratio when a voltage of 10 V is applied between the source / drain electrodes. The gate leakage current at 3 digits when the gate voltage was 20 V was 4.2 × 10 ⁻⁹ A, indicating good transistor characteristics and sufficiently suppressing the gate leakage current.

(Comparative Example 1)
In FIG. 5, a thin film transistor element 7 was obtained in the same manner as in Example 1 except that SiON (film thickness 450 nm) was formed as a single layer using a RF magnetron sputtering apparatus as the gate insulating layer 12. The SiON film formation conditions were an input power of 500 W, a gas flow rate Ar = 50 SCCM, O ₂ = 20 SCCM, and a film formation pressure of 1.0 Pa.

As a result of evaluating the adhesiveness in the same manner as in Example 1, peeling was observed in a part between the gate insulating layer 12 and the insulating substrate 10 of the manufactured thin film transistor element 7, and it was confirmed that the adhesion was poor. For this reason, the transistor characteristics could not be measured.

Table 1 shows the transistor characteristics of the thin film transistors of Examples 1 to 6 and Comparative Example 1.

In a thin film transistor, particularly a flexible thin film transistor, the gate insulating layer has a multilayer structure of two or more layers, and a layer in contact with the substrate is formed by ion beam sputtering. A highly reliable thin film transistor in which an insulating layer is not peeled can be provided.
Such a thin film effect transistor can be used as a switching element for electronic paper, LCD, organic EL display and the like. In particular, the present invention can be widely applied to flexible displays, IC cards, IC tags, etc. using a flexible substrate as a substrate.

DESCRIPTION OF SYMBOLS 10 Insulating substrate 11 Gate electrode 12 Gate insulating layer 12a Lower gate insulating layer 12b Upper gate insulating layer 13 Semiconductor layer 14 Source electrode 15 Drain electrode

Claims (10)

At least a gate electrode, a gate insulating layer, a semiconductor layer containing an oxide, a source electrode and a drain electrode are provided on the insulating substrate, the gate insulating layer being in contact with the insulating substrate, and the lower gate insulating layer A method of manufacturing a thin film transistor in which one or more upper gate insulating layers formed on a substrate are laminated, wherein the lower gate insulating layer is formed by ion beam sputtering. . 2. The method of manufacturing a thin film transistor according to claim 1, wherein at least one layer of the lower gate insulating layer contains any one compound of silicon oxide, silicon nitride, silicon oxynitride, and aluminum oxide. 3. The method of manufacturing a thin film transistor according to claim 1, wherein at least one layer of the upper gate insulating layer is formed by magnetron sputtering. 3. The method of manufacturing a thin film transistor according to claim 1, wherein at least one layer of the upper gate insulating layer is formed by a CVD method. 3. The method of manufacturing a thin film transistor according to claim 1, wherein at least one layer of the upper gate insulating layer is formed by a coating method. 6. The thin film transistor according to claim 1, wherein at least one layer of the upper gate insulating layer contains any one compound of silicon oxide, silicon nitride, silicon oxynitride, and aluminum oxide. Production method. The thin film transistor according to claim 6, wherein at least one layer of the upper gate insulating layer includes any one compound of polyacrylate, polyvinyl alcohol, polystyrene, polyimide, polyester, epoxy, polyvinyl phenol, and polyvinyl alcohol. Manufacturing method. 8. The method of manufacturing a thin film transistor according to claim 1, wherein the thickness of the lower gate insulating layer is not less than 10 nm and not more than 200 nm. The method for manufacturing a thin film transistor according to claim 1, wherein the semiconductor layer containing an oxide contains at least one of In, Ga, and Zn. The method for manufacturing a thin film transistor according to claim 1, wherein the insulating substrate is a flexible substrate.

Images