JP5548500B2 - Method for manufacturing thin film field effect transistor - Google Patents

Description

  The present invention relates to a method for manufacturing a thin film field effect transistor using an amorphous oxide semiconductor, and more particularly to a method for manufacturing a thin film field effect transistor having good TFT characteristics and in-plane uniformity without providing an etching stopper layer. .

Currently, field effect transistors are widely used as semiconductor memory integrated circuits, high-frequency signal amplifiers, and the like.
In addition, as a switching element of a flat thin image display device (FPD) such as a liquid crystal display device (LCD), an electroluminescence display device (EL), a field emission display (FED), etc., a thin film among field effect transistors Field effect transistors (hereinafter also referred to as TFTs) are used. In a TFT used for FPD, an amorphous silicon thin film or a polycrystalline silicon thin film is formed as an active layer on a glass substrate.

A TFT using the above-described amorphous silicon thin film or polycrystalline silicon thin film as an active layer requires a relatively high temperature thermal process. For this reason, although a glass substrate can be used, it is difficult to use a resin substrate having low heat resistance.
Further, the FPD is required to be thinner, lighter, and more resistant to breakage, and the use of a lightweight and flexible resin substrate instead of the glass substrate is also being studied. For this reason, TFTs using amorphous oxides that can be deposited at low temperatures are being actively developed (see, for example, Patent Documents 1 and 2).

Patent Document 1 describes a thin film field effect transistor having an active layer containing an amorphous ZnO-based composite semiconductor as a semiconductor element, and having a source electrode and a drain electrode formed so as to partially overlap the active layer. ing. The amorphous ZnO-based composite semiconductor constituting the active layer is represented by x (Ga2O3) y (In2O3) z (ZnO).
The above x, y, and z satisfy the following relations: 0.75 ≦ x / z ≦ 3.15 and 0.55 ≦ y / z ≦ 1.70.
In Patent Literature 1, an amorphous ZnO-based composite semiconductor is formed by normal sputtering using a composite target of gallium oxide, indium oxide, and zinc oxide. As the target, for example, one having Ga: In: Zn of 2: 2: 1 is used.

  Patent Document 2 describes a driving TFT that supplies current to an organic electroluminescent element. This driving TFT has at least a substrate, a gate electrode, a gate insulating film, an active layer, a source electrode and a drain electrode, and has an electric resistance higher than that of the active layer between the active layer and at least one of the source electrode and the drain electrode. A large resistance layer is formed. Note that the resistance layer and the active layer are formed using an In—Ga—Zn—O-based amorphous oxide semiconductor.

US Patent Application Publication No. 2007/0252147 JP 2009-31742 A JP 2008-166716 A

  In the thin film field effect transistor of Patent Document 1, a source electrode and a drain electrode are directly formed on an active layer, and a layer for protecting the active layer is not formed. For this reason, when etching is performed to form the source electrode and the drain electrode, the active layer is also etched, which causes a problem of defective characteristics and uneven characteristics of the thin film transistor. In addition, depending on the etching conditions of the source electrode and the drain electrode, the active layer is entirely etched, so that the thin film field effect transistor is not obtained and the TFT characteristics may not be exhibited.

  In the driving TFT of Patent Document 2, a resistance layer is provided between the active layer and the source and drain electrodes. However, in the driving TFT of Patent Document 2, the resistance layer has the same composition as the active layer. For this reason, when etching is performed to form a source electrode and a drain electrode directly provided on the resistance layer, there is a problem that the resistance layer is also etched to cause defective characteristics and uneven characteristics of the thin film transistor. Further, depending on the etching conditions of the source electrode and the drain electrode, even the active layer below the resistance layer is etched, so that the thin film field effect transistor may not be formed and the TFT characteristics may not be exhibited.

In order to solve these problems, as described in Patent Document 3, an etching stopper layer made of an insulating film is provided on the active layer of amorphous oxide, and the active layer is etched during etching of the source electrode and the drain electrode. There is known a method for preventing the etching until the etching. However, in the method as described in Patent Document 3, since it is necessary to newly provide an etching stopper layer, there arises a new problem that the number of steps increases and the manufacturing cost increases.
As described above, the TFT manufacturing method using an amorphous oxide semiconductor is an inexpensive manufacturing method capable of obtaining a TFT having good TFT characteristics and good in-plane uniformity without increasing the number of steps. There is no current method.

  An object of the present invention is to provide an inexpensive method for manufacturing a thin film field-effect transistor that eliminates the problems based on the above-described prior art, has good TFT characteristics, and good in-plane uniformity.

In order to achieve the above object, according to an embodiment of the present invention, at least a gate electrode, an insulating film, an active layer, a source electrode, and a drain electrode are formed on a substrate, and the source electrode and the drain electrode are formed on the active layer. A step of forming the source electrode and the drain electrode using a mixed acid aqueous solution containing phosphoric acid, acetic acid, and nitric acid as an etchant, The active layer is composed of an amorphous oxide semiconductor containing In, Ga, and Zn. The active layer has a Zn concentration of less than 20%, an In concentration of 40% or more, and a Ga concentration of The present invention provides a method for manufacturing a thin film field effect transistor characterized by being 37% or more.
Here, in the present invention, the Zn concentration indicates the concentration of Zn atoms contained in the amorphous oxide semiconductor film excluding oxygen atoms. As a method for calculating the Zn concentration, Zn concentration = [Amount of Zn atom contained in the amorphous oxide semiconductor film / (In atom amount contained in the amorphous oxide semiconductor film + Atom amount contained in the amorphous oxide semiconductor film + The amount of Zn atoms contained in the amorphous oxide semiconductor film) can be used. The In concentration and the Ga concentration are also defined in the same manner as the Zn concentration, and the In concentration and the Ga concentration are obtained in the same manner as the Zn concentration.

In this case, the active layer has a Zn concentration of less than 20% on the upper surface of the active layer in contact with the source electrode and the drain electrode, an In concentration of 40% or more, and a Ga concentration of 37% or more. preferable.
The source electrode and the drain electrode are preferably made of molybdenum or a molybdenum alloy, and molybdenum is particularly preferable.
Moreover, it is preferable that the said mixed acid aqueous solution contains 70-75 mass% of phosphoric acid, 5-10 mass% of acetic acid, and 1-5 mass% of nitric acid.

A step of forming the gate electrode on the substrate before the step of forming the source electrode and the drain electrode; and a step of forming the insulating film on the substrate so as to cover the gate electrode; Forming the active layer on the insulating film, and in the step of forming the source electrode and the drain electrode, the source electrode and the drain electrode are covered with the active layer so as to cover a part of the active layer. It is preferable to form on a substrate.
It is preferable that after the step of forming the source electrode and the drain electrode, a step of forming a protective layer on the substrate so as to cover the active layer, the source electrode, and the drain electrode.

In another embodiment, the method includes the step of forming the active layer on the substrate before the step of forming the source electrode and the drain electrode, and the step of forming the source electrode and the drain electrode. The source electrode and the drain electrode are formed on the substrate so as to cover a part of the active layer, and after the step of forming the source electrode and the drain electrode, the active layer, the source electrode, and the drain It is preferable to include a step of forming the insulating film on the substrate so as to cover the electrode and a step of forming the gate electrode on the insulating film.
Further, each step is preferably performed at a temperature of 200 ° C. or lower.

  According to the present invention, the active layer is composed of an amorphous oxide semiconductor containing In, Ga, and Zn, and the Zn concentration of this active layer is less than 20%, the In concentration is 40% or more, and the Ga concentration Is 37% or more, the etching rate ratio between the source electrode and the drain electrode and the active layer is sufficiently increased with respect to the mixed acid aqueous solution containing phosphoric acid, acetic acid and nitric acid for forming the source electrode and the drain electrode. Can be bigger. Therefore, etching of the active layer during formation of the source electrode and the drain electrode is suppressed, and a thin film field effect transistor having good TFT characteristics and good in-plane uniformity can be obtained by an inexpensive manufacturing method. .

It is typical sectional drawing which shows an example of the thin film field effect transistor formed with the manufacturing method of the thin film field effect transistor which concerns on the 1st Embodiment of this invention. It is a graph which shows the etching rate ratio with respect to the molybdenum of the IGZO film by Zn density | concentration when phosphoric acid 73 mass%, acetic acid 7 mass%, and nitric acid 3 mass% are contained in the etching liquid and the temperature is 25 degreeC. . The etching rate ratio of the IGZO film to molybdenum according to the In concentration and Ga concentration when a mixed acid aqueous solution containing 73 mass% phosphoric acid, 7 mass% acetic acid and 3 mass% nitric acid at a temperature of 25 ° C. is used in the etching solution is shown. It is a graph. (A)-(c) is typical sectional drawing which shows the manufacturing method of the thin film field effect transistor which concerns on the 1st Embodiment of this invention in process order. It is typical sectional drawing which shows the other example of the thin film field effect transistor formed with the manufacturing method of the thin film field effect transistor which concerns on the 2nd Embodiment of this invention. (A)-(d) is typical sectional drawing which shows the manufacturing method of the thin film field effect transistor which concerns on the 2nd Embodiment of this invention in process order.

Hereinafter, a thin film field effect transistor of the present invention will be described in detail based on a preferred embodiment shown in the accompanying drawings.
FIG. 1 is a schematic cross-sectional view showing an example of a thin film field effect transistor formed by the method for manufacturing a thin film field effect transistor according to the first embodiment of the present invention.

  A thin film field effect transistor (hereinafter simply referred to as TFT) 10 shown in FIG. 1 includes a substrate 12, a gate electrode 14, a gate insulating film 16, an active layer 18 functioning as a channel layer, a source electrode 20a, A drain electrode 20b and a protective layer 22 are provided. The TFT 10 is an active element having a function of switching a current between the source electrode 20a and the drain electrode 20b by applying a voltage to the gate electrode 14 to control a current flowing through the active layer 18. The TFT 10 shown in FIG. 1 is generally called a top contact type bottom gate structure.

  In the TFT 10, a gate electrode 14 is formed on the surface 12 a of the substrate 12, and a gate insulating film 16 is formed on the surface 12 a of the substrate 12 so as to cover the gate electrode 14. An active layer 18 is formed on the surface 16 a of the gate insulating film 16. A source electrode 20 a is formed on the surface 16 a of the gate insulating film 16 so as to cover a part of the active layer 18. Further, a drain electrode 20b that forms a pair with the source electrode 20a is formed on the surface 16a of the gate insulating film 16 so as to cover a part of the active layer 18 and to face the source electrode 20a. That is, the source electrode 20a and the drain electrode 20b are formed so as to cover a part of the surface 18a of the active layer 18 with the upper surface 18a of the active layer 18 being opened. A protective layer 22 is formed so as to cover the source electrode 20a, the active layer 18 and the drain electrode 20b.

The substrate 12 is not particularly limited. For the substrate 12, for example, an inorganic material such as YSZ (zirconia stabilized yttrium) and glass can be used. Further, the substrate 12 includes polyesters such as polyethylene terephthalate (PET), polybutylene terephthalate (PBT), and polyethylene naphthalate (PEN), polystyrene, polycarbonate, polyethersulfone, polyarylate, allyl diglycol carbonate, polyimide, polycyclo Organic materials such as synthetic resins such as olefin, norbornene resin and poly (chlorotrifluoroethylene) can also be used.
When an organic material is used for the substrate 12, heat resistance, dimensional stability, solvent resistance, electrical insulation, workability, low air permeability, low moisture absorption, and the like are preferable.
In addition, when glass is used for the substrate 12, it is preferable to use alkali-free glass in order to reduce eluted ions from the glass. In addition, when using soda-lime glass for the board | substrate 12, it is preferable to use what gave barrier coats, such as a silica.

The substrate 12 can be a flexible substrate. The flexible substrate preferably has a thickness of 50 μm to 500 μm. This is because if the thickness of the flexible substrate is less than 50 μm, it is difficult for the substrate itself to maintain sufficient flatness. Further, if the thickness of the flexible substrate exceeds 500 μm, the flexibility of the substrate itself becomes poor, and it becomes difficult to bend the substrate itself freely.
As the flexible substrate, an organic plastic film having a high transmittance is preferable. Examples of the organic plastic film include polyesters such as polyethylene terephthalate (PET), polybutylene phthalate (PBT), and polyethylene naphthalate (PEN), polystyrene, polycarbonate, polyethersulfone, polyarylate, polyimide, polycycloolefin, and norbornene. A resin or a plastic film such as poly (chlorotrifluoroethylene) is used.
When a plastic film or the like is used for the substrate 12, an insulating layer is formed and used if the electrical insulation is insufficient.

The substrate 12 can be provided with a moisture permeation preventive layer (gas barrier layer) on the front surface or the back surface in order to prevent permeation of water vapor and oxygen.
As the material for the moisture permeation preventing layer (gas barrier layer), inorganic materials such as silicon nitride and silicon oxide are preferably used. The moisture permeation preventing layer (gas barrier layer) can be formed by, for example, a high frequency sputtering method.
In addition, when using a thermoplastic substrate, you may provide a hard-coat layer, an undercoat layer, etc. further as needed.

  The gate electrode 14 is made of, for example, a metal such as Al, Mo, Cr, Ta, Ti, Au, or Ag, or an alloy thereof, an alloy such as Al—Nd, APC, tin oxide, zinc oxide, indium oxide, or indium tin oxide. It is formed using a metal oxide conductive material such as (ITO) or indium zinc oxide (IZO), an organic conductive compound such as polyaniline, polythiophene, or polypyrrole, or a mixture thereof. As the gate electrode 14, it is preferable to use Mo, Mo alloy or Cr from the viewpoint of reliability of TFT characteristics. The thickness of the gate electrode 14 is, for example, 10 nm to 1000 nm.

  The method for forming the gate electrode 14 is not particularly limited. The gate electrode 14 is formed using, for example, a wet method such as a printing method or a coating method, a physical method such as a vacuum deposition method, a sputtering method, or an ion plating method, or a chemical method such as CVD or plasma CVD method. The Among these, a forming method is appropriately selected in consideration of suitability with the material constituting the gate electrode 14. For example, when the gate electrode 14 is formed using Mo or Mo alloy, a DC sputtering method is used. Further, when an organic conductive compound is used for the gate electrode 14, a wet film forming method is used.

The gate insulating film 16 is made of an insulator such as SiO ₂ , SiNx, SiON, Al ₂ O ₃ , YsO ₃ , Ta ₂ O ₅ , or HfO ₂ , or a mixed crystal compound containing at least two of these compounds. . A polymer insulator such as polyimide can also be used for the gate insulating film 16.
The thickness of the gate insulating film 16 is preferably 10 nm to 10 μm. The gate insulating film 16 needs to be thick to some extent in order to reduce leakage current and increase voltage resistance. However, when the thickness of the gate insulating film 16 is increased, the driving voltage of the TFT 10 is increased. Therefore, the thickness of the gate insulating film 16 is more preferably 50 nm to 1000 nm in the case of an inorganic insulator, and more preferably 0.5 μm to 5 μm in the case of a polymer insulator.
Note that when a high dielectric constant insulator such as HfO ₂ is used for the gate insulating film 16, the transistor can be driven at a low voltage even when the film thickness is increased. It is particularly preferable to use a high dielectric constant insulator.

The source electrode 20a and the drain electrode 20b are made of, for example, a metal such as Al, Mo, Cr, Ta, Ti, Au, or Ag, or an alloy thereof, an alloy such as Al—Nd, APC, tin oxide, zinc oxide, or indium oxide. , Indium tin oxide (ITO), indium zinc oxide (IZO), and other metal oxide conductive materials.
As the source electrode 20a and the drain electrode 20b, Mo or Mo alloy is preferably used from the viewpoint of reliability of TFT characteristics and an etching rate ratio with the active layer 18, and Mo is particularly preferable. In addition, the thickness of the source electrode 20a and the drain electrode 20b is 10 nm-1000 nm, for example.

The source electrode 20a and the drain electrode 20b are formed by forming the above-described film, forming a resist pattern on the film using a photolithography method, and etching the film.
Note that there is no particular limitation on the method of forming the above-described film formed by the source electrode 20a and the drain electrode 20b. The above-described film is formed using, for example, a wet method such as a printing method or a coating method, a physical method such as a vacuum deposition method, a sputtering method, or an ion plating method, or a chemical method such as CVD or plasma CVD method. The

For example, when the source electrode 20a and the drain electrode 20b are formed of Mo or Mo alloy, for example, a Mo film or a Mo alloy film is formed by using a DC sputtering method.
Then, using a photolithography method, a resist pattern is formed on the Mo film or the Mo alloy film, and the Mo film or the Mo alloy film is etched with an etchant to form the source electrode 20a and the drain electrode 20b.
As the etching solution, a mixed acid aqueous solution containing phosphoric acid, acetic acid, and nitric acid is used. This mixed acid aqueous solution contains, for example, 70 to 75% by mass of phosphoric acid, 5 to 10% by mass of acetic acid, 1 to 5% by mass of nitric acid, and the balance is water.

The active layer 18 is composed of an amorphous oxide semiconductor containing In, Ga, and Zn. In the active layer 18, the Zn concentration (Zn / (Zn + In + Ga)) is less than 20% and the In concentration (In / (Zn + In + Ga)) is 40% or more when the total atomic weight excluding oxygen is 100%. The Ga concentration (Ga / (Zn + In + Ga)) is 37% or more.
As described above, the Zn concentration herein refers to the concentration of Zn atoms contained in the amorphous oxide semiconductor film excluding oxygen atoms. As a method for calculating the Zn concentration, Zn concentration = [Amount of Zn atom contained in the amorphous oxide semiconductor film / (In atom amount contained in the amorphous oxide semiconductor film + Atom amount contained in the amorphous oxide semiconductor film + The amount of Zn atoms contained in the amorphous oxide semiconductor film) can be used. The In concentration and the Ga concentration are also defined in the same manner as the Zn concentration, and the In concentration and the Ga concentration are obtained in the same manner as the Zn concentration.
Note that values obtained by XRF (fluorescence X-ray analysis) are used as the Zn atomic weight, In atomic weight, and Ga atomic weight in the amorphous oxide semiconductor film.

The Zn concentration, In concentration, and Ga concentration in the active layer 18 may be the entire active layer 18, or may be concentrations on the surface 18a portion where the active layer 18 is in contact with the source electrode 20a and the drain electrode 20b, or on the upper surface.
The Zn concentration is preferably 5% or more and less than 20%. This is because when the Zn concentration is less than 5%, the amorphous property of the oxide semiconductor film is deteriorated and crystallization is easily caused.
The In concentration is preferably 40% to 58%, and the Ga concentration is preferably 37% to 55%.

  When the source electrode 20a and the drain electrode 20b made of Mo or Mo alloy are formed using the above mixed acid aqueous solution as an etching solution, the active layer 18 also comes into contact with the etching solution. In this case, if the active layer 18 is not resistant to the etching solution, the active layer 18 is also etched. For this reason, in this invention, the etching rate with respect to the mixed acid aqueous solution of the active layer 18 is reduced so that the active layer 18 may not be etched. That is, the active layer 18 has a sufficiently high etching rate ratio (selection ratio) with Mo constituting the source electrode 20a and the drain electrode 20b.

In the present invention, when the Zn concentration of the active layer 18 is less than 20%, the etching rate ratio with molybdenum exceeds 10 with respect to the mixed acid aqueous solution containing phosphoric acid, acetic acid and nitric acid, as shown in FIG. ing. For this reason, the etching of the active layer 18 is suppressed when the source electrode 20a and the drain electrode 20b are formed.
When the Ga concentration of the active layer 18 is 37% or more, the etching rate ratio with molybdenum exceeds 10 with respect to the mixed acid aqueous solution containing phosphoric acid, acetic acid, and nitric acid, as shown in FIG. . For this reason, the etching of the active layer 18 is suppressed when the source electrode 20a and the drain electrode 20b are formed.
Further, even if the In concentration of the active layer 18 is 40% or more, the etching rate ratio with molybdenum exceeds 10 with respect to the mixed acid aqueous solution containing phosphoric acid, acetic acid and nitric acid as shown in FIG. Yes. For this reason, the etching of the active layer 18 is suppressed when the source electrode 20a and the drain electrode 20b are formed.

  Thus, in the present invention, the composition of the active layer 18 is such that the Zn concentration is less than 20%, the In concentration is 40% or more, the Ga concentration is 37% or more, and the source electrode 20a and the drain electrode 20b for the mixed acid aqueous solution. The etching rate ratio is sufficiently high, for example, exceeding 10. Thereby, when forming the source electrode 20a and the drain electrode 20b, the etching of the active layer 18 can be suppressed.

The protective layer 22 is formed for the purpose of protecting the active layer 18, the source electrode 20 a, and the drain electrode 20 b from the deterioration due to the atmosphere, and for the purpose of insulating them from the electronic device manufactured on the transistor.
The protective layer 22 of the present embodiment is formed by, for example, photosensitive acrylic resin being heat-cured in a nitrogen atmosphere.

The protective layer 22 is, for example, MgO, SiO, SiO ₂ , Al ₂ O ₃ , GeO, NiO, CaO, BaO, Fe ₂ O ₃ , Y ₂ O ₃ , Ga ₂ O ₃ other than the above-described photosensitive acrylic resin. Or metal oxides such as TiO ₂ , metal nitrides such as SiNx, SiNxOy, metal fluorides such as MgF ₂ , LiF, AlF ₃ , or CaF ₂ , polyethylene, polypropylene, polymethyl methacrylate, polyimide, polyurea, polytetrafluoro Copolymerization obtained by copolymerizing ethylene, polychlorotrifluoroethylene, polydichlorodifluoroethylene, a copolymer of chlorotrifluoroethylene and dichlorodifluoroethylene, and a monomer mixture containing tetrafluoroethylene and at least one comonomer Combined and copolymerized main chain with cyclic structure Fluorine-containing copolymer to water absorption of 1% by weight of the water absorbing material, it is also possible to use a water absorption of 0.1% or less of the proof substance.

  The method for forming the protective layer 22 is not particularly limited. The protective layer 22 is formed by, for example, vacuum deposition, sputtering, reactive sputtering, MBE (molecular beam epitaxy), cluster ion beam, ion plating, plasma polymerization (high frequency excitation ion plating), plasma. A CVD method, a laser CVD method, a thermal CVD method, a gas source CVD method, a coating method, a printing method, or a transfer method can be applied.

Next, a manufacturing method of the TFT 10 of this embodiment will be described with reference to FIGS.
First, for example, a glass substrate is prepared as the substrate 12.
Next, a molybdenum film (not shown) having a thickness of, for example, 40 nm is formed on the surface 12a of the substrate 12 by using a DC sputtering method.
Next, a resist film (not shown) is formed on the molybdenum film, and a resist pattern is formed using a photolithography method.
Next, for example, the molybdenum film is etched using a mixed acid aqueous solution containing 70 to 75% by mass of phosphoric acid, 5 to 10% by mass of acetic acid, 1 to 5% by mass of nitric acid, and the balance being water. To do. Thereafter, the resist film is peeled off. As a result, a gate electrode 14 made of molybdenum is formed on the surface 12a of the substrate 12 as shown in FIG.

Next, an SiO ₂ film (not shown) to be the gate insulating film 16 is formed on the entire surface 12a of the substrate 12 so as to cover the gate electrode 14 by using an RF sputtering method to a thickness of 200 nm, for example. Form.
Next, an IGZO film (not shown) to be the active layer 18 is formed on the surface of the SiO ₂ film to a thickness of, for example, 50 nm using a DC sputtering method. As described above, the SiO ₂ film and the IGZO film are successively formed on the substrate 12 in this order.

Next, a resist film (not shown) is formed on the IGZO film. Then, a resist pattern is formed using a photolithography method. Then, for example, the IGZO film is etched using 5% oxalic acid water. Thereafter, the resist film is peeled off. Thereby, the active layer 18 is formed.
Again, a resist film (not shown) is formed on the SiO ₂ film / IGZO film. Then, a resist pattern is formed using a photolithography method. Then, for example, the SiO ₂ film is etched using buffered hydrofluoric acid. Thereafter, the resist film is peeled off. Thereby, the gate insulating film 16 is formed. In this way, the active layer 18 and the gate insulating film 16 are patterned as shown in FIG.

The composition of the IGZO film constituting the active layer 18 is such that the Zn concentration is less than 20%, the In concentration is 40% or more, and the Ga concentration is 37% or more.
When the IGZO film is formed by DC sputtering, a target whose composition is adjusted in advance so as to have the composition of the IGZO film is used.

Next, for example, a molybdenum film (not shown) that becomes the source electrode 20a and the drain electrode 20b is applied to the surface 16a of the gate insulating film 16 so as to cover the active layer 18, using a DC sputtering method. The film is formed to a thickness of 100 nm under the condition of 0.37 Pa.
Next, a resist film (not shown) is formed on the molybdenum film, and a resist pattern is formed using a photolithography method in the same manner as the gate electrode 14. Then, for example, the molybdenum film is etched using a mixed acid aqueous solution containing 70 to 75% by mass of phosphoric acid, 5 to 10% by mass of acetic acid, 1 to 5% by mass of nitric acid, and the balance being water. Etching is preferably performed at a liquid temperature of the mixed acid aqueous solution at the time of etching of 35 ° C. or lower, more preferably at a liquid temperature of 15 ° C. to 25 ° C. After the etching, the resist film is peeled off. Thereby, as shown in FIG. 4C, the source electrode 20a and the drain electrode 20b formed so as to cover a part of the surface 18a of the active layer 18 are obtained.

Next, for example, a photosensitive acrylic resin is applied so as to cover the active layer 18, the source electrode 20a, and the drain electrode 20b. Then, an acrylic resin film is patterned by using a photolithography method. In addition, the curing conditions of the acrylic resin at the time of pattern formation are, for example, a temperature of 180 ° C. and 30 minutes.
Next, post-annealing is performed at a temperature of 180 ° C. for 1 hour in a nitrogen atmosphere. As described above, the TFT 10 shown in FIG. 1 can be formed.

In the present embodiment, the etching rate ratio of the active layer 18 in the etching solution with respect to the source electrode 20a and the drain electrode 20b is increased to 10 or more, and the etching resistance of the active layer 18 is increased. Thereby, the etching of the underlying active layer 18 can be reduced during the etching for forming the source electrode 20a and the drain electrode 20b. For this reason, TFT10 which shows a favorable TFT characteristic can be formed uniformly in a surface.
In the present embodiment, since the etching stopper layer for protecting the active layer 18 from being etched is not provided on the active layer 18, the manufacturing process of the TFT 10 can be simplified. Thereby, the production efficiency can be improved and the production cost can be reduced.
Furthermore, by increasing the etching resistance of the active layer 18, for example, a threshold shift is suppressed for the TFT 10, and the reliability of the TFT characteristics is improved.

  In the manufacturing process of the TFT 10, the resist film formation, resist pattern formation, various film formation, and protective layer 22 formation are all performed at a temperature of 200 ° C. or less. Thus, since each process is performed at a temperature of 200 ° C. or lower, for example, PET, PEN or the like having low heat resistance can be used for the substrate 12. Since these PET and PEN are flexible, a flexible transistor can be obtained.

Next, a second embodiment will be described.
FIG. 5 is a schematic cross-sectional view showing another example of a thin film field effect transistor formed by the method of manufacturing a thin film field effect transistor according to the second embodiment of the present invention.
In this embodiment, the same components as those of the TFT 10 of the first embodiment shown in FIG. 1 are denoted by the same reference numerals, and detailed description thereof is omitted.

  The TFT 10a shown in FIG. 5 is generally called a top contact type top gate structure. The TFT 10a is different from the TFT 10 shown in FIG. 1 in that the arrangement position of the gate electrode 14 and the arrangement position of the active layer 18 and the source electrode 20a and the drain electrode 20b are reversed upside down. The configuration is the same as that of the TFT 10 shown in FIG.

In the TFT 10 a shown in FIG. 5, an active layer 18, a source electrode 20 a, and a drain electrode 20 b are formed on the surface 12 a of the substrate 12. An insulating film 24 is formed on the substrate 12 so as to cover the active layer 18, the source electrode 20a, and the drain electrode 20b. A gate electrode 14 is formed on the surface 24 a of the insulating film 24. A protective layer 22 is formed on the surface 24 a of the insulating film 24 so as to cover the gate electrode 14.
The insulating film 24 is for insulating the active layer 18 and the source and drain electrodes 20a and 20b from the gate electrode 14. Since the insulating film 24 has the same configuration as that of the gate insulating layer 16 of the TFT 10 shown in FIG. 1, detailed description thereof is omitted.

Next, a manufacturing method of the TFT 10a of this embodiment will be described.
6A to 6D are schematic cross-sectional views showing a method of manufacturing a thin film field effect transistor according to the second embodiment of the present invention in the order of steps.
In the manufacturing method of the TFT 10a, detailed description of the same steps as those of the manufacturing method of the TFT 10 of the first embodiment shown in FIGS.

In the manufacturing method of the TFT 10a of this embodiment, first, for example, a glass substrate is prepared as the substrate 12.
Next, an IGZO film (not shown) to be the active layer 18 is formed on the surface 12a of the substrate 12 to a thickness of 50 nm by using, for example, a DC sputtering method.
Next, a resist film (not shown) is formed on the IGZO film, and a resist pattern is formed using a photolithography method. Then, for example, the IGZO film is etched using 5% oxalic acid water. Thereafter, the resist film is peeled off. Thereby, as shown in FIG. 6A, the active layer 18 is patterned on the surface 12 a of the substrate 12.

Next, a source film 20a and a drain electrode 20b are formed on the surface 12a of the substrate 12 so as to cover the active layer 18, for example, a molybdenum film (not shown) is formed to a thickness of 100 nm using a DC sputtering method. The film is formed under the condition of 37 Pa.
Next, a resist film (not shown) is formed on the molybdenum film, and a resist pattern is formed using a photolithography method. Then, the molybdenum film is etched using a mixed acid aqueous solution having the same component as that of the first embodiment. After the etching, the resist film is peeled off. As a result, as shown in FIG. 6B, a source electrode 20a and a drain electrode 20b formed so as to cover a part of the surface 18a of the active layer 18 are obtained.

Next, as shown in FIG. 6C, an SiO ₂ film (not shown), for example, having a thickness of 200 nm, becomes an insulating film 24 so as to cover the active layer 18, the source electrode 20a, and the drain electrode 20b. Is formed using an RF sputtering method. A resist film (not shown) is formed on the SiO ₂ film, and a resist pattern is formed using a photolithography method. Then, for example, the insulating film 24 is formed by etching the SiO ₂ film using buffered hydrofluoric acid.
Next, for example, a molybdenum film (not shown) to be the gate electrode 14 having a thickness of 40 nm is formed on the surface 24a of the insulating film 24 by using a DC sputtering method.
Next, a resist film (not shown) is formed on the molybdenum film, and a resist pattern is formed using a photolithography method.
Next, the molybdenum film is etched using a mixed acid aqueous solution having the same components as in the first embodiment. Thereafter, the resist film is peeled off. As a result, the gate electrode 14 made of molybdenum is formed on the surface 24 a of the insulating film 24 as shown in FIG.

Next, for example, a photosensitive acrylic resin is applied to the surface 24 a of the insulating film 24 so as to cover the gate electrode 14. Then, an acrylic resin film is patterned by using a photolithography method. In addition, the curing conditions of the acrylic resin at the time of pattern formation are, for example, a temperature of 180 ° C. and 30 minutes.
Next, post-annealing is performed at a temperature of 180 ° C. for 1 hour in a nitrogen atmosphere. As described above, the TFT 10a shown in FIG. 5 can be formed.

Also in this embodiment, the same effect as that of the manufacturing method of the TFT 10 of the first embodiment can be obtained. For this reason, also in this embodiment, the TFT 10a exhibiting good TFT characteristics can be uniformly formed in the surface. Further, the reliability of TFT characteristics can be improved.
Also in this embodiment, since the etching stopper layer is not provided, the manufacturing process of the TFT 10a can be simplified, so that the production efficiency can be improved and the production cost can be reduced.
Also in the manufacturing process of the TFT 10a, the formation of the resist film, the formation of the resist pattern, the formation of various films, and the formation of the protective layer 22 are all performed at a temperature of 200 ° C. or less. Thus, since each process is performed at a temperature of 200 ° C. or lower, a substrate 12 having low heat resistance such as PET or PEN can be used. Thereby, a flexible TFT can be obtained.

  The present invention is basically as described above. As mentioned above, although the manufacturing method of the thin film field effect transistor of this invention was demonstrated in detail, this invention is not limited to the said embodiment, Even if it is variously improved or changed in the range which does not deviate from the main point of this invention. Of course it is good.

Examples of the method for manufacturing a thin film field effect transistor of the present invention will be specifically described below.
In this example, the TFT 10 having the structure shown in FIG. 1 having the active layers shown in the following Example 1, Example 2, Comparative Example 1 and Comparative Example 2 was produced. The TFTs of Example 1 and Comparative Example 2 were evaluated.

Each TFT of Example 1, Example 2, Comparative Example 1 and Comparative Example 2 was manufactured by the manufacturing method shown in FIGS. 4A to 4C described above except that the composition of the active layer was different.
In each of the TFTs of Example 1, Example 2, Comparative Example 1, and Comparative Example 2, for the gate electrode 14, a molybdenum film having a thickness of 40 nm is formed by DC sputtering, and a photolithography method is used for this molybdenum film. A resist pattern was formed by etching using a mixed acid aqueous solution (liquid temperature 35 ° C.) containing 73% by mass of phosphoric acid, 7% by mass of acetic acid, 3% by mass of nitric acid, and the balance being water.

Next, a 200 nm thick SiO ₂ film to be the gate insulating film 16 is formed by RF sputtering. Next, on the surface of the SiO ₂ film, an IGZO film having a composition to be described later, which will become the active layer 18, is formed to a thickness of 50 nm using the DC sputtering method. A resist pattern was formed on the IGZO film using a photolithography method, and the active layer 18 was formed by etching the IGZO film using 5% oxalic acid water.
The gate insulating film 16 was formed by forming a resist pattern on the SiO ₂ film / IGZO film using a photolithography method and etching the SiO ₂ film using buffered hydrofluoric acid after forming the active layer 18.

For the active layer 18, an IGZO film having each composition described later is formed to a thickness of 50 nm using DC sputtering, a resist pattern is formed on the IGZO film using a photolithography method, and 5% oxalic acid water is used. The IGZO film was etched using this.
For the source electrode 20a and the drain electrode 20b, a molybdenum film is formed to a thickness of 100 nm under a pressure of 0.37 Pa using a DC sputtering method. A resist pattern is formed on the molybdenum film using a photolithography method. Then, a molybdenum film is formed by etching using a mixed acid aqueous solution (liquid temperature 25 ° C.) containing 73% by mass of phosphoric acid, 7% by mass of acetic acid and 3% by mass of nitric acid as an etchant and the balance being water. did.

  As for the protective layer 22, a photosensitive acrylic resin (PC405G (manufactured by JSR Corporation)) is applied so as to cover the active layer 18, the source electrode 20a, and the drain electrode 20b, and an acrylic resin film is used by photolithography. The pattern was formed. The curing conditions for the acrylic resin during pattern formation are a temperature of 180 ° C. and 30 minutes. After that, post-annealing was performed for 1 hour at a temperature of 180 ° C. in a nitrogen atmosphere to form the TFT 10.

In Example 1, the active layer has a Zn concentration (Zn / In + Ga + Zn) of 14.6%, a Ga concentration (Ga / In + Ga + Zn) of 41.6%, and an In concentration (In / In + Ga + Zn) of 43.8%. An IGZO film was used. The concentration analysis of the IGZO film was performed by XRF analysis as described above.
In Example 1, the etching rate with the above-described etching liquid (molybdic acid aqueous solution of 73% by mass of phosphoric acid, 7% by mass of acetic acid and 3% by mass of nitric acid (liquid temperature 25 ° C.)) with molybdenum constituting the source electrode and the drain electrode. The ratio (IGZO: Mo) is 1: 13.8. Example 1 corresponds to the symbol A shown in FIG.

In Example 2, the active layer has a Zn concentration (Zn / In + Ga + Zn) of 19.2%, a Ga concentration (Ga / In + Ga + Zn) of 38.8%, and an In concentration (In / In + Ga + Zn) of 42.0%. An IGZO film was used.
In Example 2, the etching rate with the above-described etching liquid (molybdic acid aqueous solution (liquid temperature 25 ° C.) of 73% by mass of phosphoric acid, 7% by mass of acetic acid and 3% by mass of nitric acid) with molybdenum constituting the source electrode and the drain electrode. The ratio (IGZO: Mo) is 1: 10.6. Example 2 corresponds to the symbol B shown in FIG.

In Comparative Example 1, the active layer has a Zn concentration (Zn / In + Ga + Zn) of 34.7%, a Ga concentration (Ga / In + Ga + Zn) of 30.3%, and an In concentration (In / In + Ga + Zn) of 35.0%. An IGZO film was used.
In Comparative Example 1, the etching rate with the above-described etching liquid (mixed aqueous solution of phosphoric acid 73 mass%, acetic acid 7 mass% and nitric acid 3 mass% (liquid temperature 25 ° C.)) with molybdenum constituting the source electrode and the drain electrode The ratio (IGZO: Mo) is 1: 3.1. Comparative example 1 corresponds to the symbol C shown in FIG.

In Comparative Example 2, the active layer has a Zn concentration (Zn / In + Ga + Zn) of 25.1%, a Ga concentration (Ga / In + Ga + Zn) of 36.5%, and an In concentration (In / In + Ga + Zn) of 38.4 %. An IGZO film was used.
In Comparative Example 2, the etching rate with molybdenum constituting the source electrode and the drain electrode by the above-described etching solution (mixed acid aqueous solution of phosphoric acid 73 mass%, acetic acid 7 mass% and nitric acid 3 mass% (liquid temperature 25 ° C.)). The ratio (IGZO: Mo) is 1: 9.0. Comparative example 2 corresponds to the symbol D shown in FIG.

For the transistors of Example 1, Example 2, Comparative Example 1 and Comparative Example 2, the mobility was measured. As a result, in Examples 1 and 2, the mobility was 10 cm ² / Vs or more, and a TFT with good uniformity in TFT characteristics could be formed.
On the other hand, in Comparative Example 1, when the source electrode and the drain electrode were formed, the active layer disappeared and a TFT could not be formed. In Comparative Example 2, although the TFT operated, the in-plane uniformity of the TFT characteristics was poor.

10, 10a Thin film field effect transistor (TFT)
DESCRIPTION OF SYMBOLS 12 Substrate 14 Gate electrode 16 Gate insulating film 18 Active layer 20a Source electrode 20b Drain electrode 22 Protective layer 24 Insulating film

Claims (8)

A method of manufacturing a thin film field effect transistor in which at least a gate electrode, an insulating film, an active layer, a source electrode, and a drain electrode are formed on a substrate, and the source electrode and the drain electrode are provided on the active layer. And
Using a mixed acid aqueous solution containing phosphoric acid, acetic acid, and nitric acid as an etchant, and forming the source electrode and the drain electrode,
The active layer is composed of an amorphous oxide semiconductor containing In, Ga, and Zn. The active layer has a Zn concentration of less than 20%, an In concentration of 40% or more, and a Ga concentration of A manufacturing method of a thin film field effect transistor, characterized by being 37% or more. The method for producing a thin film field effect transistor according to claim 1, wherein the temperature of the mixed acid aqueous solution is 35 ° C. or lower .   3. The method of manufacturing a thin film field effect transistor according to claim 1, wherein the source electrode and the drain electrode are made of molybdenum or a molybdenum alloy.   4. The thin film field effect transistor according to claim 1, wherein the mixed acid aqueous solution contains 70 to 75 mass% phosphoric acid, 5 to 10 mass% acetic acid, and 1 to 5 mass% nitric acid. 5. Production method. Before the step of forming the source electrode and the drain electrode, the step of forming the gate electrode on the substrate, the step of forming the insulating film on the substrate so as to cover the gate electrode, and the insulation Forming the active layer on the film,
5. The process according to claim 1, wherein in the step of forming the source electrode and the drain electrode, the source electrode and the drain electrode are formed on the substrate so as to cover a part of the active layer. Of manufacturing a thin film field effect transistor.   The thin film field effect according to claim 5, further comprising a step of forming a protective layer on the substrate so as to cover the active layer, the source electrode, and the drain electrode after the step of forming the source electrode and the drain electrode. Type transistor manufacturing method. Before the step of forming the source electrode and the drain electrode, the step of forming the active layer on the substrate,
In the step of forming the source electrode and the drain electrode, the source electrode and the drain electrode are formed on the substrate so as to cover a part of the active layer,
Further, after the step of forming the source electrode and the drain electrode, a step of forming the insulating film on the substrate so as to cover the active layer, the source electrode, and the drain electrode, and the gate on the insulating film The method of manufacturing a thin film field effect transistor according to claim 1, further comprising a step of forming an electrode.   The method of manufacturing a thin film field effect transistor according to claim 1, wherein each of the steps is performed at a temperature of 200 ° C. or less.

Images