JP2006339265A - Field effect transistor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a field effect transistor capable of having superior on-current characteristics without increasing an occupation area. <P>SOLUTION: The field effect transistor comprises a gate electrode 12, a gate insulating film 13, a semiconductor thin film 15 having a channel formation region 16, and a pair of source/drain electrodes 14. When a width in a channel widthwise direction in the projection image of the channel formation region 16, a width in a channel lengthwise direction, a length in the channel widthwise direction following an interface with the gate insulating film 13 of the semiconductor thin film 15 in the channel formation region 16, and a length in the channel lengthwise direction are set to W<SB>1</SB>, L<SB>1</SB>, W<SB>2</SB>, and L<SB>2</SB>, respectively. W<SB>2</SB>is larger than W<SB>1</SB>, and L<SB>2</SB>is equal to L<SB>1</SB>. The width in the channel widthwise direction is expanded effectively in the channel formation region 16, and the so-called on-current characteristics are improved. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a field effect transistor, and more particularly to a field effect transistor including a semiconductor thin film as a channel formation region.

  A field effect transistor formed on a support such as a glass substrate, a quartz substrate, or a plastic substrate is used for a memory element such as a static random access memory (SRAM), an active matrix liquid crystal display device (LCD), or the like. Widely used. In addition, research and development of elements using conductive polymer materials as field effect transistors (FETs) have been eagerly advanced, and a new field of flexible and inexpensive plastic electronics is being developed. A so-called organic field effect transistor in which a channel formation region is composed of an organic semiconductor layer is known from, for example, Japanese Patent Laid-Open Nos. 10-270712 and 2000-269515.

  An outline of an example of a conventional field effect transistor will be described below with reference to FIGS. A projected image for explaining the arrangement of the components in the field effect transistor 100 is shown in FIG. 14A, the broken line indicates the gate electrode 12 with a part cut away, the alternate long and short dash line indicates the source / drain electrode 114 with a part cut away, and the solid line indicates the semiconductor thin film 115. FIG. 14B shows an AA cross section and a BB cross section of the field effect transistor in FIG.

  The conventional field effect transistor 100 includes a gate electrode 12, a pair of source / drain electrodes 114, and a semiconductor thin film 115. The semiconductor thin film 115 includes a channel formation region 116. The channel formation region 116 is provided on the gate insulating film 113 across the source / drain electrodes 114 and is formed so as to be in contact with the source / drain electrodes 114.

  Here, the field effect transistor 100 is a so-called bottom gate / bottom contact field effect transistor. The gate electrode 12 is formed on the support 11. The gate insulating film 113 is provided to ensure electrical insulation from the gate electrode 12 and is provided at least on the gate electrode 12. More specifically, the gate insulating film 113 is formed on the support 11 and the gate electrode 12. The pair of source / drain electrodes 114 is formed on the flat gate insulating film 113. The semiconductor thin film 115 is provided on the gate insulating film 113 across the source / drain electrodes 114 and is formed so as to be in contact with the source / drain electrodes 114. An interlayer insulating layer 120 is provided on the gate insulating film 113, the source / drain electrode 114, and the semiconductor thin film 115. Further, a wiring 121 connected to the source / drain electrode 114 is formed on the interlayer insulating layer 120. In FIG. 14A, the wiring 121 is omitted.

In FIG. 14A, the semiconductor thin film 115 is disposed so as to have a width W ₁ in the channel width direction in the projected image of the channel formation region 116. In the semiconductor thin film 115, a portion provided on the gate insulating film 113 between the source / drain electrodes 114 becomes a channel formation region 116. Further, the width in the channel length direction in the projected image of the channel formation region 116 is the width L ₁ . Since the gate insulating film 113 has a flat surface, the surface of the semiconductor thin film 115 formed thereon (the surface indicated as the interface in FIG. 14B) also has a flat shape. Therefore, the length in the channel width direction following the interface between the semiconductor thin film 115 and the gate insulating film 113 in the channel formation region 116 shown in the BB cross-sectional view of FIG. 14B, that is, W ₂ is the width in the projected image. substantially equal to the W _1. Similarly, A-A sectional view showing the channel width direction to follow the interface between the gate insulating film 113 of the semiconductor thin film 115 in the channel forming region 116 the length of (B) in FIG. 14, i.e., L ₂ is also projected image Is substantially equal to the width L ₁ at.

  A current flow in the conventional field effect transistor 100 will be described with reference to FIG. In the channel formation region 116, a current flows between the source / drain electrodes 114 in the Y-axis direction of FIG. Specifically, when the semiconductor thin film 115 is made of pentacene, which is an organic semiconductor material, a limited region having a thickness of about several nanometers in the Z-axis direction in FIG. 15 from the surface of the semiconductor thin film 115 on the gate insulating film 113 side. That is, a current flows in the channel region indicated by the oblique lines in FIG.

JP-A-10-270712 JP 2000-269515 A

  As described above, in the conventional field effect transistor 100, the current flowing between the source / drain electrodes 114 flows in a limited channel region near the gate insulating film 113 of the semiconductor thin film 115 in the channel formation region 116. . Therefore, the so-called on-current characteristics of the field effect transistor 100 shown in FIG. 15 are limited by the area of the semiconductor thin film 115 (portion indicated as an interface in FIG. 15) in the channel formation region 116. In other words, the channel formation region 116 is almost restricted by the length in the X-axis direction of FIG. That is, the on-current characteristics are improved by increasing the length of the channel formation region 116 in the semiconductor thin film 115 in the X-axis direction. However, if the length of the channel formation region 116 in the X-axis direction is simply increased, the area occupied by the field-effect transistor also increases, making it difficult to achieve both high integration and miniaturization of the field-effect transistor.

  Therefore, an object of the present invention is to provide a field effect transistor that can have excellent on-current characteristics without increasing the area occupied by the field effect transistor.

In order to achieve the above object, a field effect transistor of the present invention is a field effect transistor comprising a gate electrode, a gate insulating film, a semiconductor thin film having a channel formation region, and a pair of source / drain electrodes. And
In the projected image of the channel formation region, the width in the channel width direction is W ₁ , the width in the channel length direction is L _1, and the length in the channel width region following the interface between the semiconductor thin film and the gate insulating film is W _2. When the length in the channel length direction is L ₂ ,
W ₂ is greater than W ₁ and L ₂ is equal to L ₁ . Here, “L ₂ is equal to L ₁ ” includes not only the case where it is strictly equal but also the case where there is a difference due to manufacturing variation or the like.

  In the field effect transistor of the present invention, for example, the cross-sectional shape of the interface in the channel width direction can be a wave shape. Examples of the wave shape include a non-sinusoidal shape, a sine wave shape, or a combination thereof. Furthermore, examples of the non-sinusoidal shape include a substantially arc shape, a triangular shape, a square shape, a rectangular shape, or a combination thereof.

The field effect transistor of the present invention is
The gate electrode is formed on the support,
The gate insulating film is formed on at least the gate electrode,
The semiconductor thin film can be a field effect transistor provided on the gate insulating film between the source / drain electrodes and formed so as to be in contact with the source / drain electrodes. Hereinafter, the field effect transistor having such a structure is referred to as a bottom gate type field effect transistor. In this case, a so-called bottom gate / bottom contact field effect transistor in which the source / drain electrodes are formed on the gate insulating film may be used, or the source / drain electrodes may be formed on the semiconductor thin film. A so-called bottom gate / top contact type field effect transistor may be used.

  In the bottom gate type field effect transistor, the gate insulating film may be made of a resin material, and the wavefront shape may be transferred to the gate insulating film by a transfer mold provided with the wavefront shape. The transfer may be performed mechanically or physically. In the case where the gate insulating film is a film made of an ultraviolet curable resin material, the film may be cured by irradiating ultraviolet rays after the transfer mold is pressed against the film before curing. Alternatively, when the gate insulating film is a film made of a thermosetting resin material, the film may be cured by applying heat after the transfer mold is pressed against the uncured film. Furthermore, the surface of the gate insulating film made of a silicon oxide film or the like may be polished into a wavefront shape by polishing it in a certain direction with abrasive grains or the like. By disposing the semiconductor thin film following the wavefront shape of the gate insulating film, the cross-sectional shape in the channel width direction of the interface of the semiconductor thin film can be a shape having a wave shape.

The field effect transistor of the present invention is
The semiconductor thin film is provided on the support across the source / drain electrodes and is formed in contact with the source / drain electrodes.
The gate insulating film is formed on the semiconductor thin film,
The gate electrode may be a field effect transistor formed on the gate insulating film. Hereinafter, the field effect transistor having such a structure is referred to as a top gate type field effect transistor. In this case, the source / drain electrodes may be so-called top gate / top contact type field effect transistors formed on the semiconductor thin film, or the source / drain electrodes are formed on the support. A so-called top gate / bottom contact type field effect transistor may be used.

  In the top gate type field effect transistor, the surface shape of the support may be a wavefront shape. For example, the support may be a plastic substrate whose surface is processed into a wavefront shape. In addition, a silicon substrate having a silicon oxide film formed on the surface can be used as the support, and the surface of the silicon oxide film may be polished into a wavefront shape by polishing it in a certain direction with abrasive grains or the like. Furthermore, the wavefront shape may be transferred to the surface of the support by a transfer mold provided with the wavefront shape. For example, the wavefront shape may be transferred to the surface of a support made of a plastic material such as a plastic material. Furthermore, a wavefront shape may be formed on the surface of the resin layer using a support having a plastic layer on the surface, for example, a resin layer. In the case where the resin layer is a film made of an ultraviolet curable resin material, the film may be cured by irradiating ultraviolet rays after the transfer mold is pressed against the film before curing. Alternatively, when the resin layer is a film made of a thermosetting resin material, the film may be cured by applying heat after the transfer mold is pressed against the film before curing. By forming a gate electrode, a gate insulating film, a semiconductor thin film, and the like on these supports in a predetermined order, a top gate field effect transistor, and in some cases, the field effect transistor of the present invention Can be obtained. By disposing the semiconductor thin film following the wavefront shape of the support, the cross-sectional shape in the channel width direction of the interface of the semiconductor thin film can be a shape having a wave shape.

In the field effect transistor of the present invention, the unevenness in the channel width direction following the semiconductor thin film in the channel formation region depends on the size of the channel formation region, but the peak height Zp of the contour curve specified in JIS B0601: 2001 is 0. .05 μm to 500 μm, contour curve valley depth Zv is 0.05 μm to 500 μm, contour curve element height Zt is 0.01 μm to 1000 μm, and contour curve element length Xs is appropriately set in the range of 1 nm to 1000 μm. It only has to be. Note that the width in the channel width direction in the projected image of the channel formation region of the field effect transistor is W _1, and the length in the channel width direction following the interface between the semiconductor thin film and the gate insulating film in the channel formation region is W ₂ . It is preferable that W ₂ ≧ 1.5 × W ₁ .

In the field effect transistor of the present invention, the semiconductor thin film is a film having a volume resistivity of the order of 10 ⁻⁴ Ω · m (10 ⁻⁶ Ω · cm) to 10 ¹² Ω · m (10 ¹⁰ Ω · cm). Point to. The semiconductor thin film can be composed of an inorganic semiconductor material or an organic semiconductor material. Specific examples of the inorganic semiconductor material include Si, Ge, and Se. 2,3,6,7-dibenzoanthracene (also called pentacene), C ₉ S ₉ (benzo [1,2-c; 3,4-c ′; 5,6-c ″] tris [1] as organic semiconductor materials , 2] dithiol-1,4,7-trithione), C ₂₄ H ₁₄ S ₆ (alpha-sexithiophene), phthalocyanine represented by copper phthalocyanine, fullerene (C ₆₀ ), tetrathiotetracene (C ₁₈ H ₈ S _4), tetraselenotetracene _{(C 18 H 8 Se 4)} , tetra-tellurium tetracene _{(C 18 H 8 Te 4)} , mention poly (3,4-ethylenedioxythiophene) / polystyrene sulfonic acid [PEDOT / PSS] be able to.

  As a method for forming a semiconductor thin film, depending on the material constituting the semiconductor thin film, a physical vapor deposition method (PVD method) exemplified by a vacuum deposition method or a sputtering method; various chemical vapor deposition methods (CVD methods) ); Spin coating method; printing method such as screen printing method and inkjet printing method; air doctor coater method, blade coater method, rod coater method, knife coater method, squeeze coater method, reverse roll coater method, transfer roll coater method, gravure coater Any of the coating methods such as the stamping method, the lift-off method, the shadow mask method, and the spraying method, such as coating method, kiss coater method, cast coater method, spray coater method, slit orifice coater method, calendar coater method, and dipping method be able to.

Further, in the field effect transistor of the present invention, as a material constituting the gate insulating film, a silicon oxide-based material, silicon nitride (SiN _Y ), Al ₂ O ₃ , an inorganic exemplified by a metal oxide high dielectric insulating film Not only poly-insulating materials but also polymethyl methacrylate (PMMA), polyvinylphenol (PVP), polyethylene terephthalate (PET), polyoxymethylene (POM), polyvinyl chloride, polyvinylidene fluoride, polysulfone, polycarbonate (PC), polyimide Examples thereof include organic insulating materials, and combinations thereof can also be used. As silicon oxide-based materials, silicon dioxide (SiO ₂ ), BPSG, PSG, BSG, AsSG, PbSG, silicon oxynitride (SiON), SOG (spin-on-glass), low dielectric constant SiO _x -based material (for example, polyaryl) And ether, cycloperfluorocarbon polymer and benzocyclobutene, cyclic fluororesin, polytetrafluoroethylene, fluorinated aryl ether, fluorinated polyimide, amorphous carbon, and organic SOG).

  As a method for forming the gate insulating film, mention may be made of any of the above-described various printing methods; the above-described various coating methods; the dipping method; the casting method; the spin coating method; the spray method; the various CVD methods; Can do. Here, as the PVD method, (a) various vacuum vapor deposition methods such as electron beam heating method, resistance heating method, flash vapor deposition, (b) plasma vapor deposition method, (c) bipolar sputtering method, direct current sputtering method, direct current magnetron sputtering Various sputtering methods such as sputtering, high-frequency sputtering, magnetron sputtering, ion beam sputtering, bias sputtering, (d) DC (direct current) method, RF method, multi-cathode method, activation reaction method, electric field evaporation method, Various ion plating methods such as a high-frequency ion plating method and a reactive ion plating method can be given.

Alternatively, the gate insulating film can be formed by oxidizing or nitriding the surface of the gate electrode, or can be obtained by forming an oxide film or a nitride film on the surface of the gate electrode. Examples of a method for oxidizing the surface of the gate electrode include a thermal oxidation method, an oxidation method using O ₂ plasma, and an anodic oxidation method, although depending on the material constituting the gate electrode. Further, as a method of nitriding the surface of the gate electrode, although it depends on the material constituting the gate electrode, a nitriding method using N ₂ plasma can be exemplified. Alternatively, for example, when a gate electrode is made of gold (Au), an insulating material having a functional group capable of forming a chemical bond with the gate electrode, such as a linear hydrocarbon modified at one end with a mercapto group. The gate insulating film can also be formed on the surface of the gate electrode by covering the surface of the gate electrode with a sex molecule by a method such as an immersion method.

  Furthermore, in the field effect transistor of the present invention, platinum (Pt), gold (Au), palladium (Pd), chromium (Cr), nickel as materials constituting the gate electrode, the source / drain electrode, and various wirings. (Ni), molybdenum (Mo), niobium (Nb), neodymium (Nd), aluminum (Al), silver (Ag), tantalum (Ta), tungsten (W), copper (Cu), rubidium (Rb), rhodium (Rh), titanium (Ti), indium (In), tin (Sn), etc., or alloys containing these metal elements, conductive particles made of these metals, and conductivity of alloys containing these metals Particle, polysilicon, amorphous silicon, tin oxide, indium oxide, indium-tin oxide (ITO) and include these elements It may be a laminated structure. Furthermore, an organic material such as poly (3,4-ethylenedioxythiophene) / polystyrene sulfonic acid [PEDOT / PSS] can also be used as a material constituting the gate electrode and the source / drain electrode.

  Depending on the material constituting the source / drain electrode and gate electrode, the spin coating method; the various printing methods using various conductive pastes and various conductive polymer solutions; the various coatings described above Lift-off method; shadow mask method; plating method such as electrolytic plating method, electroless plating method or a combination thereof; spray method; various PVD methods described above; and any of various CVD methods including MOCVD method Or, further, a combination with a patterning technique can be mentioned if necessary.

  In the field effect transistor of the present invention, as a support, various glass substrates, various glass substrates with an insulating layer formed on the surface, a quartz substrate, a quartz substrate with an insulating layer formed on the surface, and an insulating layer on the surface A silicon substrate formed can be mentioned. Furthermore, as a support, polyethersulfone (PES), polyimide, polycarbonate (PC), polyethylene terephthalate (PET), polymethyl methacrylate (polymethyl methacrylate, PMMA), polyvinyl alcohol (PVA), polyvinylphenol (PVP) And a plastic film, a plastic sheet, and a plastic substrate made of a polymer material exemplified in the above. If a support made of such a flexible polymer material is used, for example, A field effect transistor can be incorporated or integrated into a display device or electronic device having a curved surface. Other examples of the support include a conductive substrate (a substrate made of a metal such as gold or highly oriented graphite). In the field effect transistor of the present invention, the field effect transistor may be provided on the support member depending on the configuration and structure of the field effect transistor. The support member in such a case is also described above. It can consist of materials.

  When the field effect transistor of the present invention is applied to and used in a display device or various electronic devices, it may be a monolithic integrated circuit in which a number of field effect transistors are integrated on a support, or each field effect transistor may be cut. It may be individualized and used as a discrete part. Further, the field effect transistor may be sealed with resin.

  In the present invention, the area of the interface of the semiconductor thin film in the channel formation region can be increased without increasing the area occupied by the field effect transistor. This makes it possible to improve the on-current characteristics of the field-effect transistor and achieve both high integration and miniaturization.

  Hereinafter, the present invention will be described based on examples with reference to the drawings.

  Example 1 relates to a field effect transistor of the present invention. A projected image showing the arrangement of the components in the field effect transistor 1 of Example 1 is shown in FIG. The same applies to other embodiments described later. In FIG. 1A, the broken line indicates the gate electrode 12 with a part cut away, the alternate long and short dash line indicates the source / drain electrode 14 with a part cut away, and the solid line indicates the semiconductor thin film 15. The AA cross section and BB cross section of the field effect transistor in FIG. 1A are shown in FIG.

The field effect transistor 1 of Example 1 is a field effect transistor including a gate electrode 12, a gate insulating film 13, a semiconductor thin film 15 including a channel formation region 16, and a pair of source / drain electrodes 14. In the projected image of the channel formation region 16, the width in the channel width direction is W ₁ , the width in the channel length direction is L _1, and the channel width direction follows the interface between the semiconductor thin film 15 and the gate insulating film 13 in the channel formation region 16. length of W _2, when the length in the channel length direction is L _2, W ₂ is greater than W _1, L ₂ is equal to L _1. Furthermore, in the field effect transistor 1 of Example 1, the gate electrode 12 is formed on the support 11. The gate insulating film 13 is formed on at least the gate electrode 12. Further, the semiconductor thin film 15 is provided on the gate insulating film 13 across the source / drain electrodes 14 and is formed so as to be in contact with the source / drain electrodes 14. The source / drain electrode 14 is formed on the gate insulating film 13. That is, the field effect transistor 1 is a so-called bottom gate / bottom contact field effect transistor.

In Example 1, the support 11 is made of a glass substrate having a SiO ₂ layer (not shown) formed on the surface. Furthermore, the gate electrode 12 and the source / drain electrode 14 are composed of a gold (Au) layer, and the gate insulating film 13 is composed of polyvinylphenol (PVP). The semiconductor thin film 15 was made of pentacene. The semiconductor thin film 15 also extends on the source / drain electrode 14.

  As shown in FIG. 1B, in the field effect transistor 1 of Example 1, the surface of the gate insulating film 13 has a wavefront shape. The wavefront cross-sectional shape of the gate insulating film 13 is a substantially sinusoidal curve in the channel width direction (X-axis direction in FIG. 1A) as shown in the BB cross-sectional view in FIG. As shown in the AA cross-sectional view in FIG. 1B, the shape does not change in the channel length direction (Y-axis direction in FIG. 1A), that is, a linear shape.

The semiconductor thin film 15 is formed following the wavefront shape of the gate insulating film 13. For this reason, the cross-sectional shape in the channel width direction of the interface between the semiconductor thin film 15 and the gate insulating film 13 in the channel formation region 16 (the portion indicated as the interface in FIG. 1B) is also shown in FIG. As shown in the -B cross-sectional view, it has a substantially sinusoidal shape in the channel width direction. On the other hand, the cross-sectional shape in the channel length direction of the interface of the semiconductor thin film 15 in the channel forming region 16 is linear as shown in the AA cross-sectional view in FIG. Therefore, the semiconductor thin film in the channel formation region 16 shown in the BB cross-sectional view in FIG. 1B is compared with the width W ₁ in the channel width direction in the projection image of the channel formation region 16 shown in FIG. The length in the channel width direction, that is, W ₂ , which follows the interface with 15 gate insulating films 13, is large. Therefore, W ₂ > W ₁ , and the width of the channel forming region 16 in the channel width direction is effectively expanded. Thereby, so-called on-current characteristics are improved. On the other hand, the width L ₁ in the channel length direction in the projected image of the channel formation region 16 shown in FIG. 1A and the semiconductor thin film 15 in the channel formation region 16 shown in the AA sectional view of FIG. The length in the channel length direction following the interface with the gate insulating film 13, that is, L ₂ is equal. Therefore, since the length in the channel length direction following the interface between the semiconductor thin film 15 and the gate insulating film 13 in the channel formation region 16 is maintained in the same manner as in the conventional structure, carrier transmission is not hindered.

  Hereinafter, FIGS. 2A and 2B, FIGS. 3A and 3B, FIGS. 4A and 4B, and FIGS. (A) and (B), FIG. 6 (A) and (B), FIG. 7 (A) and (B), and FIG. 8, an outline of the method of manufacturing the field effect transistor 1 Will be explained. In the drawings showing the respective steps, “AA” is a partial cross-sectional view similar to that along AA in FIG. 1A, and “BB” indicates (A in FIG. 1. It is a partial sectional view similar to that along BB.

[Step-100]
First, the gate electrode 12 is formed on the support 11. Specifically, a pattern for forming a gate electrode made of a resist layer 31 is formed on a support 11 made of a glass substrate having a SiO ₂ layer (not shown) formed on the surface (FIG. 2A). reference).

  Next, a Ti layer as an adhesion layer and an Au layer as an ohmic electrode are sequentially formed on the support 11 and the resist layer 31 by vacuum deposition (see FIG. 2B). In the drawings, the adhesion layer is not shown. When performing vapor deposition, the support 11 is placed on a support holder (not shown) whose temperature can be adjusted, and can suppress an increase in the temperature of the support during vapor deposition. 11 can be formed while minimizing the deformation of 11.

  Thereafter, the resist layer 31 is removed by a lift-off method, whereby the gate electrode 12 made of an Au layer can be obtained (see FIG. 3A).

[Step-110]
Next, a gate insulating film 13 is formed so as to cover at least the gate electrode 12. In Example 1, a gate insulating film 13 made of a resin material is formed on the support 11 including the gate electrode 12. As the resin material, polyvinylphenol (PVP) to which a crosslinking agent and an acid generator were added was used. A gate insulating film 13 is formed on the gate electrode 12 and the support 11 based on a spin coating method (see FIG. 3B). Polyvinylphenol (PVP) to which a crosslinking agent and an acid generator are added exhibits ultraviolet curability. As an example of the crosslinking agent, Nikalac NW-100LM manufactured by Sanwa Chemical Co., Ltd. can be mentioned. An example of the acid generator is TFE-triazine manufactured by the same company.

[Step-120]
Next, the transfer mold 32 having a wavefront shape provided on the gate insulating film 13 is pressed. The end face of the transfer mold 32 on the side of the gate insulating film 13 is provided with a wavefront shape having a sine wave cross section, for example. Therefore, the gate insulating film 13 has a shape that follows the wavefront shape of the transfer mold 32. That is, the wavefront shape is transferred to the gate insulating film 13 made of a resin material by the transfer mold 32 provided with the wavefront shape (see FIG. 4A).

  Next, the gate insulating film 13 is irradiated with ultraviolet rays to cure the gate insulating film 13 (see FIG. 4B). Thereby, the wavefront shape transferred to the gate insulating film 13 is fixed. The ultraviolet irradiation can be performed after the transfer mold 32 is separated from the gate insulating film 13, or can be performed in a state where the transfer mold 32 is in pressure contact with the gate insulating film 13. In the latter case, the transfer mold 32 is preferably made of a material that transmits ultraviolet rays.

[Step-130]
Thereafter, source / drain electrodes 14 are formed on the gate insulating film 13. In the first embodiment, the source / drain electrode 14 is formed on the wavefront shape transferred to the gate insulating film 13. Specifically, a pattern for forming source / drain electrodes made of a resist layer 33 is formed on the entire surface (see FIG. 5A).

  Next, a Ti layer as an adhesion layer and an Au layer as an ohmic electrode are sequentially formed on the gate insulating film 13 and the resist layer 33 by a vacuum deposition method (see FIG. 5B). In the drawings, the adhesion layer is not shown. When performing vapor deposition, the support 11 is placed on a support holder (not shown) whose temperature can be adjusted, and can suppress an increase in the temperature of the support during vapor deposition. 11 can be formed while minimizing the deformation of 11.

  Thereafter, the resist layer 33 is removed by a lift-off method, whereby the source / drain electrode 14 made of an Au layer can be obtained (see FIG. 6A).

[Step-140]
Next, the semiconductor thin film 15 is formed (see FIG. 6B). A mask (not shown) is disposed above the gate insulating film 13 and the source / drain electrode 14, and the semiconductor thin film 15 is formed in a predetermined region. Specifically, based on the vacuum deposition method illustrated in Table 1 below, the semiconductor thin film 15 made of pentacene is placed on the source / drain electrodes 14 and the gate insulating film 13 (more specifically, the gate insulating film) through a mask. It is formed on the wavefront shape transferred to the film 13. The interface of the semiconductor thin film 15 on the gate insulating film 13 side is formed following the wavefront shape transferred to the gate insulating film 13 and exhibits a wavefront shape.

[Table 1]
Support temperature: 60 ° C
Deposition rate: 3 nm / min Pressure: 5 × 10 ⁻⁴ Pa

  The semiconductor thin film 15 is provided on the gate insulating film 13 across the source / drain electrodes 14 and is formed in contact with the source / drain electrodes 14. As a result, a channel forming region 16 made of the semiconductor thin film 15 can be obtained. The cross-sectional shape in the channel width direction of the interface between the semiconductor thin film 15 and the gate insulating film 13 in the channel formation region 16 has a wave shape (see FIG. 6B).

[Step-150]
Next, after forming an interlayer insulating layer 20 made of SiO _{2 on} the entire surface (see FIG. 7A), an opening is formed in the portion of the interlayer insulating layer 20 above the gate electrode 12 and the source / drain electrode 14. (Refer to FIG. 7B.) A wiring material layer is formed on the interlayer insulating layer 20 including the inside of these openings, and the wiring material layer is patterned to thereby connect the wiring connected to the gate electrode 12 (not shown). And the wiring 21 connected to the source / drain electrode 14 can be formed (see FIG. 8). Thus, the field effect transistor 1 of Example 1 can be obtained.

  The second embodiment is a modification of the first embodiment, and the order of forming the semiconductor thin film and the source / drain electrodes is mainly different from the first embodiment. The projected image for explaining the arrangement of the components in the field effect transistor 2 of the second embodiment is the same as that described with reference to FIG. FIG. 10 shows a partial cross-sectional view of the field effect transistor 2 of the second embodiment. In the drawings, “AA” is a partial cross-sectional view similar to that along AA in FIG. 1A, and “BB” indicates B-B in FIG. 4 is a partial cross-sectional view similar to FIG.

Similarly to the first embodiment, the field effect transistor 2 of the second embodiment also includes a gate electrode 12, a gate insulating film 13, a semiconductor thin film 15 including a channel formation region 16, and a pair of source / drain electrodes 14. It is a field effect transistor. In the projected image of the channel formation region 16, the width in the channel width direction is W ₁ , the width in the channel length direction is L _1, and the channel width direction follows the interface between the semiconductor thin film 15 and the gate insulating film 13 in the channel formation region 16. length of W _2, when the length in the channel length direction is L _2, W ₂ is greater than W _1, L ₂ is equal to L _1. Furthermore, in the field effect transistor 2 of Example 2, the gate electrode 12 is formed on the support 11. The gate insulating film 13 is formed on at least the gate electrode 12. Further, the semiconductor thin film 15 is provided on the gate insulating film 13 across the source / drain electrodes 14 and is formed so as to be in contact with the source / drain electrodes 14. The source / drain electrodes are formed on the semiconductor thin film 15. That is, the field effect transistor 2 is a so-called bottom gate / top contact field effect transistor.

  In the field effect transistor 2 of the second embodiment, the vertical arrangement state of the source / drain electrodes 14 and the semiconductor thin film 15 is thus opposite to that of the field effect transistor 1 of the first embodiment. The point is the same as in the first embodiment. Therefore, a detailed description of the field effect transistor 2 of Example 2 is omitted.

  Hereinafter, an outline of a method for manufacturing the field-effect transistor 2 of Example 2 will be described with reference to FIGS. 9A and 9B and FIG. 10 which are schematic partial sectional views of a support and the like. . In the drawings showing the respective steps, “AA” is a partial cross-sectional view similar to that along AA in FIG. 1A, and “BB” indicates (A in FIG. 1. It is a partial sectional view similar to that along BB.

[Step-200]
First, the gate electrode 12 is formed on the support 11 in the same manner as in [Step-100] of the first embodiment.

[Step-210]
Next, in the same manner as in [Step-110] in Example 1, the gate insulating film 13 is formed on the support 11 including the gate electrode 12.

[Step-220]
Next, a wavefront shape is formed in the gate insulating film 13 in the same manner as in [Step-120] in the first embodiment.

[Step-230]
Thereafter, the semiconductor thin film 15 is formed in the same manner as in [Step-140] in Example 1. A mask (not shown) is disposed above the gate insulating film 13, and the semiconductor thin film 15 is formed in a predetermined region. The surface of the semiconductor thin film 15 on the gate insulating film 13 side is formed following the wavefront shape transferred to the gate insulating film 13 and exhibits a wavefront shape.

  Thereby, a channel forming region 16 made of the semiconductor thin film 15 can be obtained. In the channel formation region 16, the cross-sectional shape in the channel width direction of the interface between the semiconductor thin film 15 and the gate insulating film 13 has a wave shape (see FIG. 9A).

[Step-240]
Thereafter, the source / drain electrodes 14 made of an Au layer are formed on the semiconductor thin film 15 in the same manner as in [Step-130] of Example 1. Specifically, with a part of the semiconductor thin film 15 and the gate insulating film 13 covered with a hard mask, a Ti layer as an adhesion layer and an Au layer as an ohmic electrode are sequentially vacuumed on the semiconductor thin film 15. It is formed by vapor deposition. In the drawings, the adhesion layer is not shown. Thus, the source / drain electrode 14 made of the Au layer can be formed without a photolithography process.

[Step-250]
Next, in the same manner as in [Step-150] in Example 1, an interlayer insulating layer 20 made of SiO ₂ is formed on the entire surface, and then on the portion of the interlayer insulating layer 20 above the gate electrode 12 and the source / drain electrode 14. Forming an opening, forming a wiring material layer on the interlayer insulating layer 20 including the inside of the opening, and patterning the wiring material layer; thereby, wiring (not shown) connected to the gate electrode 12, and The wiring 21 connected to the source / drain electrode 14 can be formed (see FIG. 10). Thus, the field effect transistor 2 of Example 2 can be obtained.

  The third embodiment is also a modification of the first embodiment, and is mainly different from the first embodiment in the wavefront shape of the gate insulating film. The projection image for explaining the arrangement of the components in the field effect transistor of the third embodiment is the same as that described with reference to FIG. A partial cross-sectional view of the field effect transistor 3 of Example 3 is shown in FIG. In the drawings, “AA” is a partial cross-sectional view similar to that along AA in FIG. 1A, and “BB” indicates B-B in FIG. 4 is a partial cross-sectional view similar to FIG.

  The field-effect transistor 3 of Example 3 also includes the [Step-100], [Step-110], [Step-120], [Step-130], [Step-140], and [Step-150] of Example 1. ] Is formed through the same process as described above. In the third embodiment, the surface of the gate insulating film 13 is processed so that the cross-sectional shape in the channel width direction is a non-sinusoidal wave shape, more specifically, a square wave shape (see FIG. 11 (A) BB cross-sectional view).

  Note that the wavefront shape of the gate insulating film 13 of Example 3 can also be applied to Example 2. The drawings are omitted.

    The fourth embodiment is also a modification of the first embodiment, and the processing of the wavefront shape of the gate insulating film is different from the first embodiment. The projected image for explaining the arrangement of the components in the field effect transistor 4 of the fourth embodiment is the same as that described with reference to FIG. A partial cross-sectional view of the field effect transistor 4 of Example 4 is shown in FIG. In the drawings, “AA” is a partial cross-sectional view similar to that along AA in FIG. 1A, and “BB” indicates B-B in FIG. 4 is a partial cross-sectional view similar to FIG.

  The field-effect transistor 4 of Example 4 also includes [Step-100], [Step-110], [Step-120], [Step-130], [Step-140], and [Step-150] of Example 1. ] Is formed through the same process as described above. In the fourth embodiment, the cross-sectional shape in the channel width direction on the surface of the gate insulating film 13 is processed so as to be a non-sinusoidal wave shape, more specifically, a triangular wave shape ( (Refer to BB cross-sectional view in FIG. 11B).

  The wavefront shape of the gate insulating film 13 of Example 4 can also be applied to Example 2. The drawings are omitted.

  Example 5 also relates to the field effect transistor of the present invention. The projected image for explaining the arrangement of the components in the field effect transistor 5 of the fifth embodiment is the same as that described with reference to FIG. A partial cross-sectional view of the field effect transistor 5 of Example 5 is shown in FIG. In the drawings, “AA” is a partial cross-sectional view similar to that along AA in FIG. 1A, and “BB” indicates B-B in FIG. 4 is a partial cross-sectional view similar to FIG.

The field effect transistor 5 of Example 5 is also a field effect transistor including a gate electrode 12, a gate insulating film 13, a semiconductor thin film 15 including a channel formation region 16, and a pair of source / drain electrodes 14. In the projected image of the channel formation region 16, the width in the channel width direction is W ₁ , the width in the channel length direction is L _1, and the channel width direction follows the interface between the semiconductor thin film 15 and the gate insulating film 13 in the channel formation region 16. length of W _2, when the length in the channel length direction is L _2, W ₂ is greater than W _1, L ₂ is equal to L _1. Furthermore, in the field effect transistor 5 of Example 5, the semiconductor thin film 15 is provided on the support 11 between the source / drain electrodes 14 and is formed so as to be in contact with the source / drain electrodes 14. ing. The gate insulating film 13 is formed on the semiconductor thin film 15. Furthermore, the gate electrode 12 is formed on the gate insulating film 13. The source / drain electrode 14 is formed on the semiconductor thin film 15. That is, the field effect transistor 5 is a so-called top gate / top contact type field effect transistor.

  In Example 5, the support 11 is made of a glass substrate on the surface of which an insulating layer 17 made of a resin material or the like is formed. The cross-sectional shape of the surface shape of the support 11 (more specifically, the surface shape of the insulating layer 17) is as shown in the cross-sectional view along the line BB in FIG. In (A) the X-axis direction) changes in a substantially sinusoidal curve, and in the channel length direction (Y-axis direction in FIG. 1 (A)) as shown in the AA sectional view in FIG. 12 (B). The shape which is not, that is, a linear shape.

The semiconductor thin film 15 is formed following the wavefront shape of the support 11 (more specifically, the wavefront shape of the insulating layer 17). For this reason, the cross-sectional shape in the channel width direction of the interface between the semiconductor thin film 15 and the gate insulating film 13 in the channel formation region 16 (the portion indicated as the interface in FIG. 12B) is also the same as B in FIG. As shown in the -B cross-sectional view, it has a substantially sinusoidal shape in the channel width direction. On the other hand, the cross-sectional shape in the channel length direction of the interface of the semiconductor thin film 15 in the channel formation region 16 is a straight line as shown in the AA cross-sectional view in FIG. Therefore, the semiconductor thin film in the channel formation region 16 shown in the BB cross-sectional view in FIG. 12B is compared with the width W ₁ in the channel width direction in the projection image of the channel formation region 16 shown in FIG. The length in the channel width direction following the interface with the 15 gate insulating film 13, that is, W ₂ is large. Therefore, W ₂ > W ₁ , and the width of the channel forming region 16 in the channel width direction is effectively expanded. Thereby, so-called on-current characteristics are improved. On the other hand, the width L ₁ in the channel length direction in the projected image of the channel formation region 16 shown in FIG. 1A and the semiconductor thin film 15 in the channel formation region 16 shown in the AA sectional view of FIG. The length in the channel length direction following the interface with the gate insulating film 13, that is, L ₂ is equal. Therefore, since the length in the channel length direction following the interface between the semiconductor thin film 15 and the gate insulating film 13 in the channel formation region 16 is maintained in the same manner as the conventional structure, carrier transmission is not hindered. .

  Hereinafter, an outline of a method for manufacturing the field effect transistor 5 of Example 5 will be described with reference to FIGS. 12A and 12B which are schematic partial cross-sectional views of a support and the like. In the drawings showing the respective steps, “AA” is a partial cross-sectional view similar to that along AA in FIG. 1A, and “BB” indicates (A in FIG. 1. It is a partial sectional view similar to that along BB.

[Step-500]
First, the surface shape of the support 11 made of a glass substrate on which an insulating layer 17 made of a resin material or the like is formed is processed. Specifically, in the same manner as in [Step-110] in Example 1, an insulating layer 17 made of polyvinylphenol (PVP) to which a crosslinking agent and an acid generator are added is applied on a glass substrate by spin coating. On the glass substrate.

  Next, in the same manner as in [Step-120] of Example 1, a wavefront shape is formed in the insulating layer 17. In Example 1, the transfer mold 32 was pressed against the gate insulating film 13. On the other hand, in Example 5, the transfer mold is pressed against the insulating layer 17. Thereafter, the insulating layer 17 is irradiated with ultraviolet rays to cure the insulating layer 17. As a result, the wavefront shape transferred to the insulating layer 17 is fixed. The ultraviolet irradiation can be performed after the transfer mold 32 is separated from the insulating layer 17 or can be performed in a state where the transfer mold 32 is in pressure contact with the insulating layer 17. In the latter case, the transfer mold 32 is preferably made of a material that transmits ultraviolet rays.

[Step-510]
Thereafter, the semiconductor thin film 15 is formed in the same manner as in [Step-140] in Example 1. A mask (not shown) is disposed above the insulating layer 17, and the semiconductor thin film 15 is formed in a predetermined region. The semiconductor thin film 15 is formed following the wavefront shape transferred to the insulating layer 17. (See FIG. 12A). As will be described later, the interface of the semiconductor thin film 15 on the gate insulating film 13 side is formed following the wavefront shape transferred to the insulating layer 17 and exhibits a wavefront shape.

[Step-520]
Next, in the same manner as in [Step-130] of Example 1, the source / drain electrodes 14 are formed on the semiconductor thin film 15 and the insulating layer 17 so as to sandwich the channel formation region 16 therebetween. A pattern for forming a source / drain electrode composed of a resist layer provided on the semiconductor thin film 15 and the insulating layer 17 is formed, and then a Ti layer as an adhesion layer and an Au layer as an ohmic electrode are sequentially formed in the semiconductor. It forms on the thin film 15, the insulating layer 17, and a resist layer by a vacuum evaporation method. In the drawings, the adhesion layer is not shown. When performing vapor deposition, the support 11 is placed on a support holder (not shown) whose temperature can be adjusted, and can suppress an increase in the temperature of the support during vapor deposition. 11 can be formed while minimizing the deformation of 11. Thereafter, the resist layer is removed by a lift-off method, whereby the source / drain electrode 14 made of an Au layer formed on the semiconductor thin film 15 and the insulating layer 17 can be obtained.

[Step-530]
Thereafter, a gate insulating film 13 is formed on the source / drain electrodes 14 and the channel formation region 16. Specifically, a pattern for forming a gate insulating film made of a resist layer is formed, and PVA is formed on the entire surface by spin coating. Then, the gate insulating film 13 can be obtained by removing the resist layer by a lift-off method.

[Step-540]
Next, the gate electrode 12 is formed on the gate insulating film 13 in the same manner as in [Step-100] in Example 1. Specifically, a gate electrode forming pattern made of a resist layer is formed on the gate insulating film 13. Next, a Ti layer as an adhesion layer and an Au layer as an ohmic electrode are sequentially formed on the gate insulating film 13 and the resist layer by vacuum deposition. In the drawings, the adhesion layer is not shown. When performing vapor deposition, the support 11 is placed on a support holder (not shown) whose temperature can be adjusted, and can suppress an increase in the temperature of the support during vapor deposition. 11 can be formed while minimizing the deformation of 11. Thereafter, the resist layer is removed by a lift-off method, whereby the gate electrode 12 made of an Au layer can be obtained.

[Step-550]
Next, in the same manner as in [Step-150] in Example 1, an interlayer insulating layer 20 made of SiO ₂ is formed on the entire surface, and then on the portion of the interlayer insulating layer 20 above the gate electrode 12 and the source / drain electrode 14. Forming an opening, forming a wiring material layer on the interlayer insulating layer 20 including the inside of the opening, and patterning the wiring material layer; thereby, wiring (not shown) connected to the gate electrode 12, and The wiring 21 connected to the source / drain electrode 14 can be formed. The interface of the semiconductor thin film 15 on the gate insulating film 13 side is formed following the wavefront shape transferred to the insulating layer 17 and exhibits a wavefront shape. (See FIG. 12B). Thus, the field effect transistor 5 of Example 5 can be obtained.

  The sixth embodiment is a modification of the fifth embodiment, and the order of forming the semiconductor thin film and the source / drain electrodes is mainly different from the fifth embodiment. The projected image for explaining the arrangement of the components in the field effect transistor 6 of the sixth embodiment is the same as that described with reference to FIG. A partial cross-sectional view of the field effect transistor 6 of Example 6 is shown in FIG.

Similarly to the fifth embodiment, the field effect transistor 6 of the sixth embodiment also includes a gate electrode 12, a gate insulating film 13, a semiconductor thin film 15 including a channel formation region 16, and a pair of source / drain electrodes 14. It is a field effect transistor. In the projected image of the channel formation region 16, the width in the channel width direction is W ₁ , the width in the channel length direction is L _1, and the channel width direction follows the interface between the semiconductor thin film 15 and the gate insulating film 13 in the channel formation region 16. length of W _2, when the length in the channel length direction is L _2, W ₂ is greater than W _1, L ₂ is equal to L _1. Furthermore, in the field effect transistor 6 of Example 6, the semiconductor thin film 15 is provided on the support 11 between the source / drain electrodes 14 and is formed so as to be in contact with the source / drain electrodes 14. ing. The gate insulating film 13 is formed on the semiconductor thin film 15. Furthermore, the gate electrode 12 is formed on the gate insulating film 13. The source / drain electrode 14 is formed on the support 11. That is, the field effect transistor 6 is a so-called top gate / bottom contact field effect transistor.

  In the field effect transistor 6 of the sixth embodiment, the vertical arrangement state of the source / drain electrodes 14 and the semiconductor thin film 15 is thus opposite to that of the field effect transistor 5 of the fifth embodiment. This is the same as in the fifth embodiment. Therefore, detailed description of the field effect transistor 6 of Example 6 is omitted.

  Hereinafter, an outline of a method for manufacturing the field effect transistor 6 of Example 6 will be described with reference to FIGS. 13A and 13B which are schematic partial cross-sectional views of a support and the like. In the drawings, “AA” is a partial cross-sectional view similar to that along AA in FIG. 1A, and “BB” indicates B-B in FIG. 4 is a partial cross-sectional view similar to FIG.

[Step-600]
First, in the same manner as in [Step-500] of Example 5, the surface shape of the support 11 made of a glass substrate on which the insulating layer 17 made of a resin material or the like is formed is processed.

[Step-610]
Next, the source / drain electrode 14 is formed on the support 11 in the same manner as in [Step-130] of Example 1.

[Step-620]
Thereafter, the semiconductor thin film 15 is formed in the same manner as in [Step-140] in Example 1. A mask (not shown) is disposed above the gate insulating film 13 and the source / drain electrode 14, and the semiconductor thin film 15 is formed in a predetermined region. The channel forming region 16 of the semiconductor thin film 15 is formed following the wavefront shape transferred to the support 11 (see FIG. 13A).

[Step-630]
Next, the gate insulating film 13 is formed on the source / drain electrodes 14 and the channel formation region 16 in the same manner as in [Step-530] of the fifth embodiment.

[Step-640]
Thereafter, the gate electrode 12 is formed on the gate insulating film 13 in the same manner as in [Step-540] of the fifth embodiment.

[Step-650]
Next, in the same manner as in [Step-150] in Example 1, an interlayer insulating layer 20 made of SiO ₂ is formed on the entire surface, and then on the portion of the interlayer insulating layer 20 above the gate electrode 12 and the source / drain electrode 14. Forming an opening, forming a wiring material layer on the interlayer insulating layer 20 including the inside of the opening, and patterning the wiring material layer; thereby, wiring (not shown) connected to the gate electrode 12, and The wiring 21 connected to the source / drain electrode 14 can be formed. The interface of the semiconductor thin film 15 on the gate insulating film 13 side is formed following the wavefront shape transferred to the insulating layer 17 and exhibits a wavefront shape. (See FIG. 13B). Thus, the field effect transistor 6 of Example 6 can be obtained.

  As mentioned above, although this invention was demonstrated based on the preferable Example, this invention is not limited to these Examples. The specific configuration and structure of the constituent elements of the field effect transistor in the embodiment are examples and can be changed as appropriate.

  In Example 5 or Example 4, in the same way as in Example 5 or Example 6 in which the cross-sectional shape in the channel width direction of the surface of the gate insulating film 13 is non-sinusoidal, The cross-sectional shape of the surface of the body 11 in the channel width direction may be a non-sinusoidal shape.

FIG. 1A is a projected image showing the arrangement of components in the field effect transistor 1 of the first to sixth embodiments. FIG. 1B is a schematic partial cross-sectional view of a support and the like for explaining the AA cross section and the BB cross section of the field effect transistor 1 in FIG. 2A and 2B are schematic partial cross-sectional views of a support and the like for explaining the method for manufacturing the field effect transistor 1 of Example 1. FIG. FIGS. 3A and 3B are schematic partial cross-sectional views of a support and the like for explaining the method for manufacturing the field effect transistor 1 of Example 1 following FIG. 2B. is there. 4A and 4B are schematic partial cross-sectional views of a support and the like for explaining the method for manufacturing the field-effect transistor 1 of Example 1 following FIG. 3B. is there. 5A and 5B are schematic partial cross-sectional views of a support and the like for explaining the manufacturing method of the field effect transistor 1 of Example 1 following FIG. 4B. is there. 6A and 6B are schematic partial cross-sectional views of a support and the like for explaining the manufacturing method of the field effect transistor 1 of Example 1 following FIG. 5B. is there. 7A and 7B are schematic partial cross-sectional views of a support and the like for explaining the manufacturing method of the field effect transistor 1 of Example 1 following FIG. 6B. is there. FIG. 8 is a schematic partial cross-sectional view of a support and the like for explaining the method for manufacturing the field effect transistor 1 of Example 1 following FIG. FIGS. 9A and 9B are schematic partial cross-sectional views of a support and the like for explaining the method for manufacturing the field-effect transistor 2 of Example 2. FIGS. FIG. 10 is a schematic partial cross-sectional view of a support and the like for explaining the method for manufacturing the field-effect transistor 2 of Example 2 following FIG. 9B. FIG. 11A is a schematic partial cross-sectional view of a support and the like for explaining the AA cross section and the BB cross section of the field effect transistor 3 of the third embodiment. FIG. 11B is a schematic partial cross-sectional view of a support and the like for explaining the AA cross section and the BB cross section of the field effect transistor 3 of the fourth embodiment. 12A and 12B are schematic partial cross-sectional views of a support and the like for explaining a method for manufacturing the field effect transistor 5 of Example 5. FIG. 13A and 13B are schematic partial cross-sectional views of a support and the like for explaining the method for manufacturing the field effect transistor 6 of Example 6. FIG. FIG. 14A is a projected image showing the arrangement of the components in the conventional field effect transistor 100. FIG. 14B is a schematic partial cross-sectional view of a support and the like for explaining the AA cross section and the BB cross section of the field effect transistor 100 in FIG. FIG. 15 is a schematic perspective view for explaining a channel formation region and a region of current flowing therethrough in the conventional field effect transistor 100. FIG.

Explanation of symbols

1, 2, 3, 4, 5, 6, 100 ... field effect transistor, 11 ... support, 12 ... gate electrode, 13, 113 ... gate insulating film, 14, 114 ... Source / drain electrodes, 15, 115 ... semiconductor thin film, 16, 116 ... channel forming region, 17 ... insulating layer, 20, 120 ... interlayer insulating layer, 21, 121 ... wiring, 31, 33 ... resist layer, 32 ... transfer mold

Claims (13)

A field effect transistor comprising a gate electrode, a gate insulating film, a semiconductor thin film having a channel formation region, and a pair of source / drain electrodes,
In the projected image of the channel formation region, the width in the channel width direction is W ₁ , the width in the channel length direction is L _1, and the length in the channel width region following the interface between the semiconductor thin film and the gate insulating film is W _2. When the length in the channel length direction is L ₂ ,
A field effect transistor, wherein W ₂ is greater than W ₁ and L ₂ is equal to L ₁ .   2. The field effect transistor according to claim 1, wherein the cross-sectional shape of the interface in the channel width direction is a wave shape.   3. The field effect transistor according to claim 2, wherein the wave shape is a non-sinusoidal shape, a sine wave shape, or a combination thereof.   4. The field effect transistor according to claim 3, wherein the non-sinusoidal shape is a substantially arc shape, a triangular shape, a square shape, a rectangular shape, or a combination thereof. The gate electrode is formed on the support,
The gate insulating film is formed on at least the gate electrode,
2. The field effect transistor according to claim 1, wherein the semiconductor thin film is provided on the gate insulating film between the source / drain electrodes and is in contact with the source / drain electrodes.   6. The field effect transistor according to claim 5, wherein the source / drain electrodes are formed on a gate insulating film.   6. The field effect transistor according to claim 5, wherein the source / drain electrodes are formed on a semiconductor thin film.   6. The field effect transistor according to claim 5, wherein the gate insulating film is made of a resin material, and the wavefront shape is transferred to the gate insulating film by a transfer mold provided with the wavefront shape. The semiconductor thin film is provided on the support across the source / drain electrodes and is formed in contact with the source / drain electrodes.
The gate insulating film is formed on the semiconductor thin film,
2. The field effect transistor according to claim 1, wherein the gate electrode is formed on the gate insulating film.   The field effect transistor according to claim 9, wherein the source / drain electrodes are formed on a semiconductor thin film.   The field effect transistor according to claim 9, wherein the source / drain electrodes are formed on a support.   10. The field effect transistor according to claim 9, wherein the surface shape of the support is a wavefront shape.   13. The field effect transistor according to claim 12, wherein the wavefront shape is transferred to the surface of the support by a transfer mold provided with the wavefront shape.

Images