JPH02140980A - Thin film transistor - Google Patents

Abstract

PURPOSE:To highly integrate by forming a plurality of grooves along a source to drain direction on an insulating board, and laminating and disposing a semiconductor layer, source and drain electrodes, an insulating layer and a gate electrode on the board. CONSTITUTION:Since a plurality of recesses 10 along a source to drain direction alphaare formed on an insulating board 1, its surface area perpendicular to the direction alpha is increased. Further, since a semiconductor layer 4, source and drain electrodes 6, 7, an insulating layer 3 and a gate electrode 2 are laminated and disposed on the board 1, the length of a direction of the layer 4 perpendicular to the source to drain direction alpha is increased. Accordingly, since the channel width of the layer 4 can be substantially increased, the size in the direction perpendicular to the direction alpha of a thin film transistor can be shortened that much. Thus, high integration can be provided.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to thin film transistors used for driving image sensors, electroluminescent displays, liquid crystal displays, etc., and particularly relates to improvements in thin film transistors that can achieve high integration. It is related to.

[Prior Art] As shown in FIGS. 7 and 8, this type of thin film transistor includes a glass substrate (a);
The gate electrode (b) formed on this gate electrode (
a first amorphous semiconductor layer (d) deposited on this gate insulating film (C);
), and if necessary, this first amorphous semiconductor layer (d
) a protective film (e) provided on a portion corresponding to the gate electrode (b) to protect the first amorphous semiconductor 1it (d), and the first amorphous semiconductor layer (d)
A second amorphous semiconductor layer (f) for ohmic contact which is provided above and mixed with trivalent or pentavalent atoms, and 1 il (m) of gold for interconnection which is provided on this second amorphous semiconductor layer <f>. First amorphous semiconductor layer (d)
The so-called ``reverse stagger type'' type, in which the main part is formed by the source/drain electrodes (g) and (h) formed by the diffusion prevention WJ (j), which prevents diffusion to ~As shown in FIG. 10, a glass substrate (a), a metal layer (j) provided on this glass substrate (1), and this metal!
(j) Source/drain electrodes (1
(h) and a first amorphous semiconductor layer (G) deposited on the source/drain electrode (G) (h) and on the glass substrate (a) between the source electrode i) and the drain electrode (h).
d), an insulation WA(e) depositing this first amorphous semiconductor layer ed), and this insulation l! A so-called "stagger type J" in which the main part thereof is composed of a gate electrode (b) formed on the J(e) is known.

In these thin film transistors, the voltage (V, ) is applied between the source and drain electrodes (q) and (h), and the gate voltage (V, ) is applied to the gate electrode (b). A channel is formed in the first amorphous semiconductor layer (d), the transistor is turned on, and a drain current (Io) flows, while the gate voltage (V
As g') is lowered, the first amorphous semiconductor layer (d)
A channel is not formed in (then the transistor is OFF)
This state causes the drain current (1,) to stop flowing, and is used for driving image sensors, liquid crystal displays, etc. as described above.

By the way, these conventional IL film transistors are shown in FIGS. 11(A) to (C) or FIGS. 12(A) to (
It was manufactured through the steps shown in C).

That is, in the former type, as shown in FIG. 11(A), the insulating film 1! serves as the gate electrode (b) and the gate insulating film (C). (C'), first amorphous semiconductor layer (
d), a protective film (e), a second amorphous semiconductor layer forming film (f), a diffusion prevention layer forming film (j'), a photoresist film (k), etc. are formed. The exposed substrate (a) is irradiated with light through a photomask (M), and the photoresist film (k) in the exposed area is removed by a development process to form a resist III (kl) (kl
) (see FIG. 11B), and a diffusion prevention layer forming film (jo) exposed from this resist DII (kl) (kl) and a second amorphous semiconductor layer forming film ("
°) are removed by an etching process to form source/drain electrodes (o) (
In the latter type, source/drain electrodes (g) are formed as shown in Figure 12 (A).
(h), first amorphous semiconductor layer (d), insulation R (e
), gate electrode forming film (b'), and photoresist 1! (k) etc. are formed on the substrate (a) through a photomask (M), and the exposed portion of the photoresist It! (k) is removed by development processing to form a resist film (k゛) (see FIG. 12B), and a gate electrode forming film (b) exposed from this resist 1m (k') is removed.
The gate electrode (b) as shown in FIG. 12(C) was formed by removing the gate electrode (b) as shown in FIG. 12(C).

Therefore, in thin film transistors manufactured by conventional methods, as shown in FIG. 11(C) and FIG. 12(C), techniques that take into account alignment errors between the substrate (a) and the photomask (M) during manufacturing are required. While an overlap part (OL) (01) was formed between the gate electrode (b) and the source/drain electrodes (g) and (h) based on the requirements of the Due to limitations in the etching accuracy of the prevention layer formation j1 (j'), the second amorphous semiconductor layer formation film (r'), the gate electrode formation film (bo), etc., there is a gap between the source and drain electrodes (g) 1). Part (G) was formed.

When using normal manufacturing equipment that transfers the pattern of the photomask (M) at a ratio of 1:1, the amount of overlap between the gate electrode (b) and the source/drain electrodes (Q) (h) is The gap between one source/drain electrode 1) (h> is approximately 5 μm.
The minimum channel length (Sh) of the first amorphous semiconductor 1(d) determined based on the amount of overlap and the amount of gap was about 18 μm.

[Problems to be Solved by the Invention] By the way, in this type of WIII1 transistor, when a constant voltage is applied to the gate electrode (b), a drain current (Io ), the first amorphous semiconductor Jl
The smaller the resistance of (d), that is, the shorter the minimum channel length (L) of the first amorphous semiconductor layer (d), the shorter the channel width (L) of the first amorphous semiconductor layer (d).
The wider the W), the larger the drain current (Io) could be obtained.

However, even if the minimum channel length (L) of the first amorphous semiconductor layer (d) is set short, there is a limit as described above at the conventional level, so when seeking a large drain current (I,), In this case, the channel width (W) of the first amorphous semiconductor WJ(d) had to be set large.

For this reason, the ratio of the channel width (W) dimension to the minimum channel length (L) dimension of the first amorphous semiconductor Jll(d), that is, (W/L), is usually set to 4 to 10, and the thin film transistor source - There was a problem in that the dimension in the direction perpendicular to the drain direction, that is, the width dimension became large, which was a major hindrance to achieving high integration.

In addition, when using a reduction stepper that reduces and transfers the pattern of the photomask (M), the maximum channel length (L) can be set shorter because the overlap amount and gear gap are reduced by the amount of reduction. Based on this, the channel I (W) of the first amorphous semiconductor (d)
Although it is possible to reduce the dimensions, the overlap part (O
L) (0shi) still cannot be eliminated, and there is a limit to its high integration.

[Means for Solving the Problems] The present invention has been made by focusing on the above-mentioned problems, and its object is to provide a thin film transistor whose width can be reduced based on the premise of the conventional Kanji level. It's about doing.

That is, the present invention includes an insulating substrate, a semiconductor layer provided on this substrate, a source/drain electrode connected to this semiconductor layer, and a gate electrode disposed opposite to the semiconductor layer with an insulating layer interposed therebetween. A plurality of grooves are formed along the source/drain direction in the insulating substrate, and the semiconductor layer, source/drain electrodes, insulating layer, and gate electrode are laminated on the insulating substrate. It is characterized by its placement.

In such technical means, the insulating substrate is
Glass, quartz, etc. can be used, and the semiconductor layer formed on this substrate includes amorphous silicon, polycrystalline silicon, etc.

In addition, regarding the source/drain electrodes arranged to be connected to the semiconductor layer and the gate electrode arranged facing the semiconductor layer through the insulating layer, for example, aluminum (
AI), chromium (Cr), titanium (T i >, tungsten (W), molybdenum (MO), nickel (N
i), optically opaque conductive materials such as copper (CU), titanium nitride (TiN), titanium tungsten (TiW), tantalum (Ta), or indium tin oxide (
ITO), tin oxide (SnO□), indium oxide (In
2O2), zinc oxide (ZnO), or other light-transmissive conductive material.

In order to make ohmic contact with the semiconductor layer for the source/drain electrodes, an ohmic contact semiconductor layer such as amorphous silicon containing trivalent or pentavalent atoms is interposed between the semiconductor layer and the conductive material. However, a structure may be adopted in which source/drain electrodes are formed of the above conductive material and a semiconductor layer for ohmic contact. In this case, as trivalent or pentavalent atoms to be mixed,
Gallium (Ga), boron (B), indium (In)
, trivalent atoms such as aluminum (AI), and phosphorus (P)
, antimony (Sb), arsenic (AS), and other pentavalent atoms can be used.

On the other hand, the grooves to be formed on the insulating substrate are either formed directly on the surface of the substrate, or formed on the surface of the substrate using Si.
Optionally, an insulating layer of O, Si, N, etc. may be formed in a shape and a groove may be formed on this surface.

Regarding the formation method, dry etching incorporating photolithography, wet etching, laser cutting, etc. can be used to form grooves directly on the substrate surface, while in the latter case grooves are formed on the insulating layer. As a method for this, a dry etching method incorporating a photolithography method, a wet etching method, etc. can be used.

Further, the above-mentioned grooves may be formed uniformly over the entire substrate, or may be formed selectively only in the semiconductor layer forming region of the 'Rm transistor. or 7 characters, or U
It is optional, such as making it into a letter shape. Further, the groove dimensions of the groove can be appropriately set depending on the required degree of integration of the wI film transistor.

In addition, this technical means has a gate electrode on the substrate side.
The present invention can be applied to both "inverted stagger type" thin film transistors and "stagger type" thin film transistors having source and drain electrodes on the substrate side.

[Function] According to the above-mentioned technical means, since a plurality of grooves are formed along the source/drain direction in the insulating substrate, the surface area in the direction orthogonal to the source/drain direction increases, and Since a semiconductor layer, a source/drain electrode, an insulating layer, and a gate electrode are stacked on this insulating substrate, the length of the semiconductor layer in the direction orthogonal to the source/drain direction increases.

Therefore, since the channel width of the semiconductor layer can be substantially increased, the dimension of the thin film transistor in the direction perpendicular to the source/drain direction can be reduced accordingly.

[Example] Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

In this embodiment, the present invention is applied to an "inverted stagger type" thin film transistor.1 As shown in FIGS. 1 to 3, this thin film transistor has a source-drain direction (α) Rectangular concave grooves (10) to (10
) and a glass substrate in a direction that crosses the grooves (10) to (10) at the portions of the substrate (1) where the grooves (10) to (10) are formed. (
1) A band-shaped gate electrode made of chromium (2) provided along the surface, and a gate electrode (5) covering this gate electrode (2).
txN, a first amorphous semiconductor layer (4) made of intrinsic amorphous silicon layered on this gate insulating film (3), and this first amorphous semiconductor layer (4). The above gate electrode (2
) to protect the first amorphous semiconductor layer (4), s+xN, protection M! <5> and a source formed of a second near-morphous semiconductor ff (60) made of n-type amorphous silicon for ohmic contact provided on the first amorphous semiconductor layer (4) and a metal layer (61) made of chromium; Drain electrode (6) (7
) and wiring gold [!t(8)(8)] connected to the source/drain electrodes (7).

In this thin film transistor, source/drain electrodes (6) (7) are used as in conventional thin film transistors.
), apply a voltage (Vo) between the gate N pole (2〉
By applying a gate voltage (Vg) to the first amorphous semiconductor layer (4), a channel is formed and a drain current (1o) flows through the first amorphous semiconductor layer (4).On the other hand, when the gate voltage (V) is lowered, the first amorphous semiconductor layer (4) A channel is no longer formed in the layer (4), and the drain current (Io) no longer flows.

At this time, in this R-film transistor, since rectangular grooves (1o) to (1o) are provided on the surface of the glass substrate (1) toward the source/drain direction (α),
The surface area of the glass substrate (1) in the direction perpendicular to the source/drain direction (α) increases partially, and this Along the surface of the glass substrate (1) in the direction crossing the grooves (10) to (10), a gate electrode (2), a gate insulation 11m (3), a first semiconductor H (4), and , source/drain electrode <6) (7
) etc. are arranged in a stacked manner, the length of the first amorphous semiconductor layer (4) in the direction perpendicular to the source/drain direction (α) increases.

Therefore, the channel width (W) of the first amorphous semiconductor layer (4) can be substantially increased, and the dimension in the direction perpendicular to the source/drain direction (α) of the thin film transistor can be reduced. This has the advantage that thin film transistors can be integrated.

In addition, if the degree of integration is the same as before,
Channel width (W) of first amorphous semiconductor layer (4)
is significantly wider than that of the conventional one, so that the resistance value of the first amorphous semiconductor layer (4) is correspondingly lowered and a large drain current (■, ) can be obtained.

"Manufacturing Process J of Thin Film Transistor This R film transistor is manufactured through the following steps.

First, a photoresist film (positive resist material manufactured by Bequist Co., Ltd., product name AZ1350J) is deposited on a glass substrate (product name: Corning 7059) (1) using a spinner device.
The photoresist film at the exposed area is irradiated with light through a photomask to transform it into a property that can be dissolved in an alkaline aqueous solution. The resist l was removed by reactive ion etching (RIE).
! The glass substrate (1) exposed from the J (20) is melted and removed, and a groove (10) with a depth of 2 μm is formed on the glass substrate (1) as shown in FIG. 4 (A>).

Next, a chromium (Cr) film of 500 to 1000 angstroms is uniformly formed on the glass substrate (1) on which the groove portion (10) is formed by sputtering, and then photolithography is performed on the surface. After forming a patterned resist film by the method, a wet etching process was performed using an etching agent composed of a mixture of ceric ammonium nitrate, hydrogen peroxide, and water, as shown in Figure 4 (B). A gate electrode (2) is formed.

Next, the photoresist film was removed, and a gate insulating film with a thickness of 3000 mm was formed by plasma CVD (Chemical Vapor Deposition) using S + H4/N H3 under vacuum conditions.
Angstrom amorphous silicon nitride (Six
An insulating film (3°) made of N.
i-8i) If the semiconductor film (4°) is also
Amorphous silicon nitride (S + xN, >1 protective film forming film) with a thickness of 1000 to 2000 angstroms was deposited on a glass substrate (
1) A patterned resist IIQ (2
1), and then the resist film (21) is etched by a wet etching method using an etching agent of buffered hydrofluoric acid (a mixture of hydrofluoric acid and ammonium fluoride in a volume ratio of 1:10). The exposed protective film forming film is removed to form a protective film (5) (see FIG. 4C).

Next, the resist II (21) is removed, and the surface of the glass substrate (1) on which the protective film (5) is formed is degreased and cleaned, and then the Si A second semiconductor film (62) made of n-type amorphous silicon having a thickness of 1000 to 1500 Å is deposited by plasma CVD using H/PH3,
Furthermore, a layer of 1000 to 20
A chromium metal film (63) having a thickness of 0.00 angstroms is deposited.

Furthermore, a photoresist film is applied and formed on this surface, and after forming a resist film (22) (22) as shown in FIG. 4(E) by the above-mentioned photolithography method,
The exposed chromium metal film (63) was removed by wet etching using an etching agent composed of a mixture of ceric ammonium nitrate, hydrogen peroxide, and water, and then etched with hydrofluoric acid, nitric acid, and phosphoric acid. Volume ratio 1:10:5
A second semiconductor skin made of n-type amorphous silicon exposed by a wet etching method using an etching agent mixed at a ratio of 0 g! (62) is dissolved and removed to form source/train electrodes (6) and (7) composed of the second amorphous semiconductor layer (60) and the gold R layer (61).

Then, a 1 μm thick aluminum (AI) gold a film is uniformly deposited on this surface, and unnecessary etching is performed using the above-mentioned photolithography method and wet etching method using a mixed etching agent of phosphoric acid, nitric acid, and acetic acid. By removing the metal film and forming gold R layers (8) (8), a 1WIG1 transistor as shown in FIG. 4(F) is obtained.

This embodiment applies the present invention to a "stagger type" thin film transistor, and as shown in FIGS. 5 and 6, a rectangular concave groove (1
A glass substrate (1) on which 0) to (10) are formed, and a near-amorphous semiconductor layer (6) made of n-type amorphous silicon provided on this substrate (1) for ohmic contact.
Source/drain electrodes (6) (7) formed of 0) and a chromium metal layer (61) to which the metal layers (8) (8) are connected, and the source/drain electrodes (6). (7
), as well as the source electrode (6) and drain electrode 8i (7)
The grooves (10) to (1) on the surface of the glass substrate (1) between
10), a first amorphous semiconductor layer (4) made of intrinsic amorphous silicon formed along the direction transverse to the first amorphous semiconductor layer (4), and an insulating film (30) made of 5ixN covering this first amorphous semiconductor layer (4); This insulation 11!
! (30) Chromium gate electrode formed on (2)
Its main parts are comprised of:

Also in the thin film transistor according to this embodiment, the surface of the glass substrate (1) is provided with a direction (α) in the source/drain direction.
Since the rectangular grooves (10) to (1o) are provided, the surface area of the glass substrate (1) in the direction orthogonal to the source/drain direction (α) is partially increased, and Source/drain electrodes (6) ( 7), first amorphous semiconductor layer (4)
, the insulation Ill (30), and the gate electrode (2) are arranged in a stacked manner, so that the source/drain direction (α) in the first amorphous semiconductor layer (4)
The length dimension in the direction orthogonal to this will increase.

Therefore, the channel width (W) of the first amorphous semiconductor layer (4) can be substantially increased, and the dimension in the direction perpendicular to the source/drain direction (α) of the thin film transistor can be reduced. This has the advantage that thin film transistors can be integrated.

In addition, if the degree of integration is the same as before,
As in the first embodiment, the channel width (W) of the first amorphous semiconductor layer (4) is significantly wider than that of the conventional one, so that the resistance value of the amorphous semiconductor layer (4) decreases and a large drain current is generated. (I,) has the advantage of being obtained.

[Effects of the Invention] As described above, in the present invention, since a plurality of grooves are formed along the source/drain direction in an insulating substrate, the surface area in the direction perpendicular to the source/drain direction is increased, and Since a semiconductor layer, a source/drain electrode, an insulating layer, and a gate electrode are stacked on this insulating substrate, the length of the semiconductor layer in the direction orthogonal to the source/drain direction increases.

Therefore, it is possible to substantially increase the channel width of the semiconductor layer, and the dimension in the direction perpendicular to the source/drain direction of the thin film transistor can be reduced accordingly, which has the effect of achieving higher integration of the thin film transistor. ing.

[Brief explanation of the drawing]

1 to 4 show a first embodiment of the present invention, FIG. 1 is a perspective view of the structure of a thin film transistor according to this embodiment, and FIG. 3 shows the plan view of FIG. 1, and FIGS. 4(A) to 4(F) show the manufacturing process of the H film transistor according to the first embodiment. ) to (F) (a) in Figure 1 (
a)-(a) plane sectional view, (b) of Fig. 4(A)-(F)
1A and 1B are cross-sectional views taken along line (b)-(b) in FIG. 1, and FIGS. 5 and 6 show a second embodiment of the present invention, and FIG. A perspective view of the structure of a single-film transistor, FIG. 6 shows a Vl-VI IN sectional view of FIG. 5, and FIGS. 7 and 9 show a conventional 'fa
A perspective view of the structure of a membrane transistor, Fig. 8 is the same as ■-■ in Fig. 7.
A plane sectional view, Figure 10 is a XX plane sectional view of Figure 9, and Figure 11.
Figures (A) to (C) and Figures 12 (A) to (C) are explanatory diagrams showing a part of the manufacturing process of these thin film transistors. [Explanation of symbols] (1)...Substrate (2)...Gate electrode (3)...Gate insulating film (4)...First amorphous semiconductor layer (6)...Source electrode (7) ...Drain electrode patent Applicant Fuji Xerox Co., Ltd. Representative Patent attorney Tomohiro Nakamura (3 others) Figure 4 Figure 4 (E) (a) Figure 4 (a) Figure 11 12 Figure

Claims (1)

[Scope of Claims] An insulating substrate, a semiconductor layer provided on this substrate, source/drain electrodes connected to this semiconductor layer, and a gate electrode placed opposite to the semiconductor layer with an insulating layer interposed therebetween. In the thin film transistor, a plurality of grooves are formed in the insulating substrate along the source/drain direction, and the semiconductor layer, the source/drain electrode, the insulating layer, and the gate electrode are stacked on the insulating substrate. A thin film transistor characterized by: