WO2016162978A1 - Thin film transistor, tft substrate, display device, and tft substrate manufacturing method - Google Patents

Thin film transistor, tft substrate, display device, and tft substrate manufacturing method Download PDF

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Publication number
WO2016162978A1
WO2016162978A1 PCT/JP2015/060998 JP2015060998W WO2016162978A1 WO 2016162978 A1 WO2016162978 A1 WO 2016162978A1 JP 2015060998 W JP2015060998 W JP 2015060998W WO 2016162978 A1 WO2016162978 A1 WO 2016162978A1
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Prior art keywords
gate
source
tft substrate
thin film
drain
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PCT/JP2015/060998
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French (fr)
Japanese (ja)
Inventor
覚 宇津木
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堺ディスプレイプロダクト株式会社
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Priority to PCT/JP2015/060998 priority Critical patent/WO2016162978A1/en
Publication of WO2016162978A1 publication Critical patent/WO2016162978A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film

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  • the present invention relates to a thin film transistor, a TFT substrate, a display device including a display panel having a TFT substrate, and a method for manufacturing the TFT substrate.
  • a liquid crystal display device includes a TFT substrate in which transparent pixel electrodes connected to a thin film transistor (TFT, Thin Film Transistor) and a thin film transistor are formed in a matrix, and a color filter (CF) substrate facing the TFT substrate. Is provided. A liquid crystal material is sealed between the TFT substrate and the CF substrate. The liquid crystal display device further includes a backlight for irradiating the display panel with light.
  • TFT Thin Film Transistor
  • CF color filter
  • the TFT controls on / off switching of voltage application to the pixel electrode.
  • the direction of the liquid crystal molecules in the display panel changes in units of each pixel or sub-pixel by the voltage applied to the pixel electrode connected to the turned-on TFT, and the light transmittance is controlled.
  • An image is displayed on the display panel by irradiating light from the backlight onto the display panel whose light transmittance is controlled in units of pixels or sub-pixels.
  • Liquid crystal display devices are required to have high definition in order to improve image quality.
  • the area per pixel or sub-pixel becomes smaller.
  • the area of the TFT through which light is not transmitted needs to be similarly reduced.
  • Patent Document 1 discloses a TFT having a channel width longer than that in the case where the channel is formed in a plane because the channel is formed in three dimensions. Therefore, in the TFT of Patent Document 1, a decrease in on-current is suppressed even when the projected area on the TFT substrate is reduced.
  • the TFT disclosed in Patent Document 1 is a top gate type TFT.
  • a TFT substrate using a top gate type TFT is disadvantageous for manufacturing a large-sized TFT substrate because the number of steps in manufacturing is relatively large.
  • the present invention has been made in view of such circumstances, and an object thereof is to manufacture a large-sized TFT substrate that can suppress a decrease in on-current even when the projected area on the TFT substrate is reduced.
  • a thin film transistor according to the present invention is formed on a gate, an insulating film covering the gate, a semiconductor layer having a channel, and a semiconductor layer having a channel, facing the semiconductor layer with a space therebetween.
  • a thin film transistor including a source and a drain, wherein the channel is located between the source and the drain, the channel extending in a direction in which the source and the drain face each other, and the gate side or the side opposite to the gate It is characterized by having a bent portion that is bent.
  • the channel since the channel has a three-dimensional bent portion, the length in the direction perpendicular to the direction in which the source and the drain face each other on the channel as compared with the planar channel, that is, the channel Long width and therefore high on-current.
  • the gate extends in a direction in which the source and the drain face each other, protrudes toward the channel side, or extends in a direction in which the source and the drain face each other. It has a concave portion which is recessed on the opposite side, and the bent portion is formed along the shape of the convex portion or the concave portion.
  • the bent portion is formed by the channel along the convex portion or concave portion of the gate. Therefore, it is not necessary to form a pattern in the insulating film in order to form the bent portion, and the cleanliness of the boundary surface between the insulating film and the other layer is maintained.
  • the thin film transistor according to the present invention includes a convex or concave base portion formed in a lower layer of the gate so as to extend in a direction in which the source and the drain face each other, and the bent portion follows the shape of the base portion. It is formed.
  • the bent portion is formed when the channel follows the shape of the base portion. Therefore, it is not necessary to form a pattern in the insulating film in order to form the bent portion, and the cleanliness of the boundary surface between the insulating film and the other layer is maintained.
  • a TFT substrate includes a substrate, a gate formed on one main surface of the substrate, an insulating film covering the gate, a semiconductor layer formed on the insulating film and having a channel, A TFT substrate having a source and a drain formed on the semiconductor layer so as to face each other with a space therebetween, wherein the channel is located between the source and the drain; Has a bent portion that extends in the opposite direction and is bent on the gate side or the opposite side of the gate.
  • the channel since the channel has a three-dimensional bent portion, the length in the direction perpendicular to the direction in which the source and the drain face each other on the channel as compared with the planar channel, that is, the channel Long width and therefore high on-current.
  • the gate extends in a direction in which the source and the drain face each other, protrudes toward the channel, or extends in a direction in which the source and the drain face each other, Has a concave portion recessed on the opposite side, and the bent portion is formed along the shape of the convex portion or the concave portion.
  • the bent portion is formed when the channel follows the shape of the convex portion or the concave portion. Therefore, it is not necessary to form a pattern in the insulating film in order to form the bent portion, and the cleanliness of the boundary surface between the insulating film and the other layer is maintained.
  • the TFT substrate according to the present invention includes a convex or concave base formed in a lower layer of the gate on the one main surface so as to extend in a direction in which the source and the drain face each other, and the bent portion includes And formed along the shape of the base.
  • the bent portion is formed when the channel of the thin film transistor follows the shape of the base. Therefore, it is not necessary to form a pattern in the insulating film in order to form the bent portion, and the cleanliness of the boundary surface between the insulating film and the other layer is maintained.
  • the TFT substrate according to the present invention is characterized in that the base is a part of the substrate.
  • the base is a part of the substrate, it is not necessary to use other materials to form the base.
  • the TFT substrate according to the present invention is characterized in that the substrate is a glass substrate and the base is formed of spin-on glass.
  • the base is made of spin-on glass, it has a high affinity for the glass substrate. Therefore, it is easy to form the base.
  • a display device includes a display panel having any one of the TFT substrates described above.
  • the display device since the display device includes the above-described TFT substrate, even if the projected area of the thin film transistor on the TFT substrate is reduced, a decrease in on-current is suppressed.
  • the TFT substrate manufacturing method includes forming a metal thin film on the substrate, applying a resist on the metal thin film, exposing the resist using a photomask having a semi-transmissive portion, and developing the resist. Then, the metal thin film is etched to form a gate, the gate is partially etched to form a convex portion or a concave portion extending in one direction on the gate, and is insulated on the substrate on which the gate is formed. A film and a semiconductor layer are sequentially formed, a metal thin film is formed on the semiconductor layer, the metal thin film is etched, and the one direction is sandwiched between portions of the semiconductor layer formed on the convex portion or the concave portion. And a source and a drain opposite to each other.
  • a convex portion or a concave portion is formed on the metal wiring by performing one-time exposure and two-time etching using a photomask having a semi-transmissive portion on the metal thin film coated with the resist. Form. Therefore, the exposure for forming the convex portion or the concave portion may be performed once, and the manufacturing process is simplified.
  • the TFT substrate manufacturing method includes etching a substrate to form a convex or concave pattern extending in one direction, forming a metal thin film on the substrate on which the pattern is formed, and forming the metal thin film on the substrate. Etching to form a gate on the pattern, sequentially forming an insulating film and a semiconductor layer on the substrate on which the gate is formed, forming a metal thin film on the semiconductor layer, etching the metal thin film, A source and a drain that are opposed to each other in one direction across a portion of the semiconductor layer formed on the pattern are formed.
  • a convex or concave pattern is formed on the glass substrate. Therefore, it is not necessary to form another thin film below the metal thin film in order to form a three-dimensional pattern on the metal wiring, and the manufacturing process is simplified.
  • a spin-on glass layer is formed on a glass substrate, the spin-on glass layer is etched to form a convex or concave pattern extending in one direction, and the pattern is formed.
  • a metal thin film is formed on the substrate, and the metal thin film is etched to form a source and a drain opposed to each other in one direction across a portion of the semiconductor layer formed on the pattern.
  • a spin-on glass layer is formed on a glass substrate, and photolithography is performed on the spin-on glass layer to form a convex or concave pattern. Since the spin-on glass layer has material characteristics similar to those of the glass substrate, the internal stress is small when formed on the glass substrate. Therefore, defects such as cracks are unlikely to occur. Therefore, pattern formation is easy even on a large TFT substrate.
  • the method for manufacturing a TFT substrate according to the present invention is characterized in that the spin-on glass layer has photosensitivity.
  • the present invention even when the projected area on the TFT substrate is reduced, it is possible to suppress a decrease in on-current, which is particularly advantageous for manufacturing a large TFT substrate.
  • FIG. 1 is a schematic perspective view of a display device according to Embodiment 1.
  • FIG. 3 is a schematic cross-sectional view of the display panel according to Embodiment 1.
  • FIG. 3 is a schematic enlarged view showing wiring on the TFT substrate according to Embodiment 1.
  • FIG. 3 is an enlarged top view of a TFT formed on the TFT substrate according to Embodiment 1.
  • FIG. 5 is a cross-sectional view of the TFT substrate according to the first embodiment taken along line VV in FIG.
  • FIG. 5 is a cross-sectional view of the TFT substrate according to the first embodiment taken along line VI-VI in FIG.
  • FIG. 5 is a cross-sectional view sequentially illustrating a manufacturing process of the TFT substrate according to the first embodiment.
  • FIG. 5 is a cross-sectional view sequentially illustrating a manufacturing process of the TFT substrate according to the first embodiment.
  • FIG. 5 is a cross-sectional view sequentially illustrating a manufacturing process of the TFT substrate according to the first embodiment.
  • FIG. 5 is a cross-sectional view sequentially illustrating a manufacturing process of the TFT substrate according to the first embodiment.
  • FIG. 5 is a cross-sectional view sequentially illustrating a manufacturing process of the TFT substrate according to the first embodiment.
  • FIG. 5 is a cross-sectional view sequentially illustrating a manufacturing process of the TFT substrate according to the first embodiment.
  • FIG. 5 is a cross-sectional view sequentially illustrating a manufacturing process of the TFT substrate according to the first embodiment.
  • FIG. 5 is a cross-sectional view sequentially illustrating a manufacturing process of the TFT substrate according to the first embodiment.
  • FIG. 5 is a cross-sectional view sequentially illustrating a manufacturing process of the TFT substrate according to the first embodiment.
  • FIG. 5 is a cross-sectional view sequentially illustrating a manufacturing process of the TFT substrate according to the first embodiment.
  • FIG. 5 is a cross-sectional view sequentially illustrating a manufacturing process of the TFT substrate according to the first embodiment.
  • FIG. 5 is a cross-sectional view sequentially illustrating a manufacturing process of the TFT substrate according to the first embodiment.
  • 6 is a cross-sectional view of a TFT substrate according to a modification of the first embodiment.
  • FIG. 6 is a cross-sectional view of a TFT substrate according to Embodiment 2.
  • FIG. FIG. 5 is a cross-sectional view sequentially illustrating a manufacturing process of a TFT substrate according to a second embodiment.
  • FIG. 5 is a cross-sectional view sequentially illustrating a manufacturing process of a TFT substrate according to a second embodiment.
  • FIG. 5 is a cross-sectional view sequentially illustrating a manufacturing process of a TFT substrate according to a second embodiment.
  • 6 is a cross-sectional view of a TFT substrate according to Embodiment 3.
  • FIG. FIG. 6 is a cross-sectional view sequentially illustrating a manufacturing process of a TFT substrate according to a third embodiment.
  • FIG. 6 is a cross-sectional view sequentially illustrating a manufacturing process of a TFT substrate according to a third embodiment.
  • FIG. 6 is a cross-sectional view sequentially illustrating a manufacturing process of a TFT substrate according to a third embodiment.
  • FIG. 6 is a cross-sectional view sequentially illustrating a manufacturing process of a TFT substrate according to a third embodiment.
  • FIG. 1 is a schematic perspective view of a display device 1 according to the first embodiment.
  • FIG. 2 is a schematic cross-sectional view of the display panel 2 according to the first embodiment.
  • FIG. 3 is a schematic enlarged view showing wiring on the TFT substrate 20 according to the first embodiment.
  • FIG. 4 is an enlarged top view of the TFT 14 formed on the TFT substrate 20 according to the first embodiment.
  • the display device 1 is, for example, an active matrix liquid crystal display device.
  • the display device 1 employs, for example, a VA (Vertical Alignment) method, which is a kind of vertical electric field driving method, as a liquid crystal molecule alignment control method.
  • VA Vertical Alignment
  • the display device 1 may adopt an IPS (In-Plane-Switching) method that is a lateral electric field driving method.
  • the display device 1 includes a rectangular display panel 2 on which an image is displayed, and a backlight (not shown) that irradiates the display panel 2 with light.
  • the display device 1 further includes a television tuner 3 that receives a television broadcast wave from an antenna (not shown), and a decoder 4 that decodes the encoded television broadcast wave into an image signal.
  • a television broadcast wave received by the television tuner 3 is decoded into an image signal by the decoder 4.
  • An image is displayed on the display panel 2 based on the decoded image signal.
  • the display device 1 may further include an image signal input terminal (not shown) and display an image based on an image signal input to the image signal input terminal.
  • the display panel 2 includes a glass-made rectangular TFT substrate 20 and a glass-made rectangular color filter (CF) substrate 21 facing the TFT substrate 20 and slightly smaller than the TFT substrate 20.
  • a liquid crystal layer 22 is provided between the TFT substrate 20 and the CF substrate 21.
  • the TFT substrate 20 and the CF substrate 21 are bonded together by a frame-shaped sealing material 23 bonded to the peripheral portions of the TFT substrate 20 and the CF substrate 21.
  • the liquid crystal layer 22 is formed by sealing a liquid crystal material with a sealing material 23 between the TFT substrate 20 and the CF substrate 21.
  • a plurality of gate lines 11a and source lines 12a are arranged on the TFT substrate 20 in a matrix.
  • the horizontal direction is the longitudinal direction of the TFT substrate
  • the vertical direction is the short direction of the TFT substrate.
  • the gate lines 11a are arranged at equal intervals in the lateral direction of the TFT substrate 20 and extend in the longitudinal direction.
  • the source lines 12a are arranged at equal intervals in the longitudinal direction of the TFT substrate 20 and extend in the short direction.
  • the gate line 11a and the source line 12a are formed in different layers on the TFT substrate.
  • an auxiliary capacitance line 11c is arranged between the gate lines 11a in parallel with the gate line 11a.
  • the gate line 11 a and the auxiliary capacitance line 11 c are formed in the same layer on the TFT substrate 20.
  • the gate line 11a and the auxiliary capacitance line 11c are covered with a gate insulating film 16 (see FIGS. 5 and 6) formed over substantially the entire surface excluding the end portion of the TFT substrate 20, for example, with silicon oxide (SiOx).
  • the source line 12 a is formed on the gate insulating film 16. That is, the gate 11a line, the source line 12a, and the storage capacitor line 11c are electrically independent from each other.
  • a rectangular pixel electrode 13 with one corner notched is formed as a transparent conductive film such as ITO (Indium Tin Oxide). It is formed by.
  • a TFT 14 is formed in the notch portion of the pixel electrode 13.
  • each TFT 14 includes a gate 11b, a gate insulating film 16 (see FIGS. 5 and 6), a semiconductor layer 15 having a channel 15a, a source 12b, and a drain 12c.
  • the gate 11 b protrudes from the gate line 11 a to the notch of the pixel electrode 13.
  • a semiconductor layer 15 is formed over substantially the entire area of the gate 11b with a gate insulating film 16 therebetween.
  • a U-shaped source 12b protrudes from the source line 12a on the semiconductor layer 15 so that the U-shaped opening is directed to the opposite side of the source line 12a.
  • a drain 12c electrically connected to the pixel electrode 13 is formed in the U-shaped opening of the source 12b with a substantially constant distance from the source 12b.
  • a portion of the semiconductor layer 15 between the source 12b and the drain 12c is bent in a U shape.
  • Such a U-shaped portion constitutes a channel 15a.
  • the TFT 14 is a bottom gate type TFT in which a channel 15a is formed on the gate 11b.
  • the bottom gate type TFT has an advantage in the production of a large TFT substrate because the number of steps in production is smaller than that of the top gate type.
  • the area to be included is the sub-pixel 30.
  • the TFT 14 the gate line 11a, the source line 12a, and the auxiliary capacitance line 11c arranged under the pixel electrode 13 do not transmit light.
  • One of three color filters (not shown) of R (Red), G (Green), and B (Blue) is provided on the CF substrate 21 at a position facing each sub pixel 30 of the TFT substrate 20. ing.
  • the R, G, and B color filters are arranged so as to be alternately repeated in the same order.
  • a black matrix (not shown) that blocks light is formed between the color filters.
  • a single common electrode (not shown) made of a transparent conductive film such as ITO is formed on each color filter and black matrix.
  • the common electrode is formed on the TFT substrate 20 in the same manner as the pixel electrode 13.
  • One pixel is composed of three sub-pixels 30 facing the adjacent three R, G, and B color filters.
  • FIG. 5 is a cross-sectional view of the TFT substrate 20 according to the first embodiment taken along line VV in FIG.
  • FIG. 6 is a cross-sectional view of the TFT substrate 20 according to the first embodiment taken along line VI-VI in FIG.
  • the TFT substrate 20 has a gate line 11a including a gate 11b and an auxiliary capacitance line 11c (not shown in FIGS. 5 and 6), a gate insulating film 16, a semiconductor layer 15, and a source on one main surface of the glass substrate 10.
  • the source line 12a and the drain 12c including 12b, the passivation film 17, the interlayer insulating film 18, and the pixel electrode 13 are stacked in this order.
  • the gate line 11 a is formed from the gate layer 11.
  • the gate layer 11 includes, for example, a base metal layer 110 containing titanium, chromium, tantalum, or the like, a first gate Cu layer 111, an etch stopper layer 112 containing titanium, nickel, tungsten, or the like, and a second gate Cu.
  • a layer 113 is laminated on the glass substrate 10 in this order. The thickness of each of the first gate Cu layer 111 and the second gate Cu layer 113 is larger than the thickness of the base metal layer 110 or the etch stopper layer 112.
  • the base metal layer 110 is provided to improve the adhesion between Cu and the glass substrate 10.
  • the etch stopper layer 112 is provided to control two-stage etching when forming the gate line 11a, which is performed in the manufacturing process of the TFT substrate 20 described later.
  • an auxiliary capacitance line 11c is similarly formed from the gate layer 11.
  • Other metals such as Al may be used instead of Cu.
  • the second gate Cu layer 113 is patterned by dry etching as will be described later, and a hook-shaped protrusion 113a protruding from the gate insulating film 16 and the channel 15a is formed on the gate 11b shown in FIG. is doing.
  • the convex portion 113a traverses the first portion 15a1 and the second portion 15a2 formed in the longitudinal direction of the TFT substrate 20 in the channel 15a formed in a U shape in plan view, so that the TFT It extends in the short direction of the substrate 20.
  • the protrusion 113a extends in the direction in which the source 12b and the drain 12c face each other in the first portion 15a1 and the second portion 15a2 of the channel 15a.
  • the convex part 113a is formed so that both sides
  • the gate insulating film 16 is formed over substantially the entire portion excluding the end portion of the TFT substrate 20.
  • the semiconductor layer 15 is formed in an island shape on the gate insulating film 16 at a position where each gate 11b is formed.
  • the semiconductor layer 15 includes, for example, an a-Si layer 150 containing amorphous silicon (a-Si) as a component, and an n + layer containing a component of n + semiconductor in which a donor such as phosphorus is doped at high concentration in a-Si. 151 are stacked in this order.
  • the carrier density of n + layer 151 is higher than that of a-Si layer 150, and therefore n + layer 151 has higher conductivity than a-Si layer 150.
  • the n + layer 151 is provided to reduce the resistivity between the source 12b and drain 12c and the a-Si layer 150.
  • an oxide semiconductor such as polycrystalline silicon (p-Si) or InGaZnO may be used as the semiconductor layer 15.
  • the semiconductor layer 15 including the channel 15a is provided on the opposite side of the gate 11b along the convex shape of the convex portion 113a with the gate insulating film 16 interposed therebetween.
  • a bent portion 15b that is bent is formed.
  • the bent portion 15b is formed in a bowl shape so as to extend in a direction in which the source 12b and the drain 12c face each other as a part of the first portion 15a1 and the second portion 15a2 of the U-shaped channel 15a.
  • the length in the longitudinal direction along the shape of the semiconductor layer 15 in the first portion 15a1 and the second portion 15a2 of the channel 15a is longer than that in the case where the bent portion 15b is not formed.
  • the length in the longitudinal direction is a length perpendicular to the direction in which the source 12b and the drain 12c face each other in the first portion 15a1 and the second portion 15a2 of the channel 15a, and is generally called a channel width.
  • the source line 12a including the source 12b and the drain 12c are formed by etching the source / drain layer 12 formed on the semiconductor layer 15 as described later.
  • the source / drain layer 12 is made of Cu, for example.
  • the source / drain layer 12 may be formed of another metal such as Al instead of Cu.
  • a passivation film 17 that covers and protects the source line 12a including the source 12b, the drain 12c, the channel 15a of the semiconductor layer 15, and the gate insulating film 16 is formed. Further, an interlayer insulating film 18 is formed so as to cover the passivation film 17. The upper surface of the interlayer insulating film 18 is formed in parallel with the main surface of the glass substrate 10 and has a function of flattening the unevenness of the layer below the interlayer insulating film 18.
  • the pixel electrode 13 is formed on the interlayer insulating film 18.
  • the pixel electrode 13 is electrically connected to the drain 12 c through a contact hole (not shown) opened in the interlayer insulating film 18.
  • an image signal decoded by the decoder 4 or an image signal input from an external device is input to an image processing circuit (not shown).
  • the image processing circuit outputs a source driver control signal and a gate driver control signal to a gate driver and a source driver (both not shown) based on the image signal.
  • the gate driver sequentially outputs the gate signal to the gate line 11a in synchronization with the horizontal synchronization signal, and the gate signal is input to the gate 11b included in the gate line 11a.
  • Each TFT 14 to which the gate signal is input to the gate 11b is turned on, and the source 12b and the drain 12c are conducted through the channel 15a.
  • a source signal is input from the source driver to the source 12b of the TFT 14 that is turned on via the source line 12a.
  • the source signal input to the source 12b changes the potential of each pixel electrode 13 through the drain 12c.
  • the potential of the common electrode facing each pixel electrode 13 is kept at a constant ground potential, and therefore the voltage between each pixel electrode 13 and the common electrode changes due to the change in potential of each pixel electrode 13. Therefore, since the direction of the liquid crystal molecules sandwiched between each pixel electrode 13 and the common electrode changes, the light transmittance of each sub-pixel 30 changes. In this way, the display panel 2 whose light transmittance is controlled in each sub-pixel 30 is irradiated with light from the backlight, whereby an image is displayed on the display panel 2.
  • the gate 11b has the convex 113a, and the channel 15a of the semiconductor layer 15 is opposite to the gate 11b along the convex shape on the convex 113a. It has the bending part 15b bent to the side. For this reason, the channel width of the three-dimensionally formed channel 15a is longer than the channel width of the planar channel. Since the on-current flowing through the TFT 14 is proportional to the channel width, the TFT 14 having the bent portion 15b in the channel 15a can flow a larger on-current. Therefore, the projected area of the TFT 14 can be reduced and the aperture ratio of each sub-pixel 30 can be increased without reducing the on-current.
  • 7A to 7L are cross-sectional views sequentially showing manufacturing steps of the TFT substrate 20 according to the first embodiment.
  • the main surface on the side where the circuit of the glass substrate 10 is formed is cleaned and dried.
  • the base metal layer 110, the first gate Cu layer 111, the etch stopper layer 112, and the second gate Cu layer 113 are sequentially stacked on the entire cleaned main surface by sputtering.
  • a gate layer 11 made of a metal thin film is formed.
  • a positive photoresist 40 is applied to the entire upper surface of the formed gate layer 11. After the photoresist 40 is applied, the photoresist 40 is pre-baked in a baking furnace.
  • the exposure apparatus exposes the photoresist 40 through the multi-tone photomask 50, and the pattern formed on the multi-tone photomask 50 is transferred with light.
  • the multi-tone photomask 50 is a gray-tone mask or a halftone mask in which a transmissive part 50a, a light-shielding part 50b, and a semi-transmissive part 50c are patterned.
  • the intermediate exposure portion 40a where the light reduced by the semi-transmissive portion 50c is exposed to the photoresist 40 and the unexposed portion 40b where light is blocked by the light shielding portion 50b. Then, a pattern including the exposed portion 40c where the light is exposed by the transmission portion 50a is formed.
  • the photoresist 40 is developed using a developer, and the exposed portion 40c is removed. At this time, as shown in FIG. 7D, a part of the photoresist 40 is removed from the intermediate exposure portion 40a, and the thickness of the photoresist 40 is reduced. The photoresist 40 in the unexposed portion 40 b remains on the second gate Cu layer 113. After the development, the glass substrate 10 is washed and dried, and the photoresist 40 is post-baked in a baking furnace.
  • a portion of the gate layer 11 where the photoresist 40 is removed is removed by an etchant in a wet etching process, and the gate line 11a including the gate 11b and the auxiliary capacitance wiring are formed on the glass substrate 10.
  • a pattern 11c (both see FIG. 3) is formed. After the wet etching, the glass substrate 10 is similarly cleaned and dried.
  • the intermediate exposure portion 40a of the photoresist 40 is removed in the ashing process.
  • FIG. 7G in the dry etching process, a portion of the second gate Cu layer 113 where the intermediate exposure portion 40a is peeled is removed, and a convex portion 113a is formed.
  • the etch stopper layer 112 protects the first gate Cu layer 111 from dry etching, the first gate Cu layer 111 is not removed.
  • the dry etching step as shown in FIG. 7H, in the resist stripping step, the remaining unexposed portion 40b is stripped, and further washed and dried.
  • a gate insulating film is formed on the gate layer 11 including the gate line 11a including the gate 11b on which the convex portion 113a is formed by the above process and the auxiliary capacitance wiring 11c by the CVD (Chemical Vapor Deposition) method.
  • the semiconductor layer 15 composed of the a-Si layer 150 and the n + layer 151 are continuously laminated.
  • the gate insulating film 16, the a-Si layer 150, and the n + layer 151 are continuously formed in the CVD chamber in order to keep the interface between the layers clean.
  • the formed a-Si layer 150 and n + layer 151 are formed into a pattern on the gate 11b as shown in FIG. 7J through photolithography including resist coating, exposure, development, etching, and resist stripping.
  • the source / drain layer 12 is formed on the semiconductor layer 15 including the a-Si layer 150 and the n + layer 151 by sputtering.
  • the formed source / drain layer 12 is subjected to photolithography including resist coating, exposure, development, etching, and resist stripping to form a source 12b.
  • the source 12 line a (see FIG. 3) and the drain 12c (see FIGS. 4 and 5) are also formed.
  • the portion formed in the channel 15 a of the n + layer 151 is removed when the source / drain layer 12 is etched.
  • a passivation film 17, an interlayer insulating film 18, and a pixel electrode 13 are sequentially formed.
  • the convex portion 113a for providing the bent portion 15b in the channel 15a is formed on the gate 11b by etching twice on the gate layer 11. Therefore, since it is not necessary to perform the etching twice on the gate insulating film 16 or the a-Si layer 150, the boundary surface between the gate insulating film 16 and the a-Si layer 150 or the a-Si layer 150 and the n + The cleanliness of the interface with the layer 151 is maintained.
  • the multi-tone photomask 50 since the multi-tone photomask 50 is used, the number of exposures and the number of masks used are reduced, and thus the manufacturing cost is reduced. However, a method using a photomask other than the multi-tone photomask may be used.
  • FIG. 8 is a cross-sectional view of a TFT substrate 20 according to a modification of the first embodiment.
  • FIG. 8 corresponds to FIG. 6 of the first embodiment.
  • the gate 11b is recessed on the opposite side to the gate insulating film 16 and the channel 15a, and a groove-like recess extending in a direction in which the source 12b and the drain 12c face each other.
  • the channel 15a is formed along the concave shape on the concave 113b via the gate insulating film 16. For this reason, the channel 15a has a bent portion 15b that extends in a direction in which the source 12b and the drain 12c face each other and is bent toward the gate 11b.
  • the channel width is formed longer than that of the planar channel 15a, as in the first embodiment. Since the on-current flowing through the TFT 14 is proportional to the channel width, the TFT 14 having the bent portion 15b in the channel 15a can flow a larger on-current. Therefore, the projected area of the TFT 14 can be reduced and the aperture ratio of each sub-pixel 30 can be increased without reducing the on-current.
  • FIG. 9 is a cross-sectional view of the TFT substrate 20 according to the second embodiment.
  • FIG. 9 corresponds to FIG. 6 of the first embodiment.
  • the glass substrate 10 is formed with a bowl-shaped base portion 10a that protrudes from one main surface.
  • the base 10a is integrated with the glass substrate 10 and extends in a direction in which the source 12b and the drain 12c face each other.
  • the channel 15 a is formed along the convex shape on the base portion 10 a via the gate insulating film 16. For this reason, the channel 15a has a bent portion 15b that extends in a direction in which the source 12b and the drain 12c face each other and is bent on the opposite side to the gate 11b.
  • the channel width is formed longer than that of the planar channel as in the first embodiment. Since the on-current flowing through the TFT 14 is proportional to the channel width, the TFT 14 having the bent portion 15b in the channel 15a can flow a larger on-current. Therefore, since the area of the TFT 14 can be reduced without reducing the on-current, the aperture ratio of each subpixel 30 can be increased.
  • the base 10 a may be formed in a groove shape that is recessed with respect to the main surface of the glass substrate 10.
  • the channel 15a formed on the base portion 10a has a bent portion 15b extending in a direction in which the source 12b and the drain 12c face each other and bent toward the gate 11b, and the same effect can be obtained.
  • TFT substrate 20 Other configurations of the TFT substrate 20 according to the present embodiment are the same as those of the first embodiment.
  • 10A to 10C are cross-sectional views sequentially showing manufacturing steps of the TFT substrate 20 according to the second embodiment.
  • a photoresist is applied to the entire main surface of the glass substrate 10, and exposure, development, etching, and resist removal are sequentially performed to form a trench pattern including a base 10a on the glass substrate 10 as shown in FIG. 10A. .
  • trench etching is performed on the glass substrate 10.
  • the region of the glass substrate 10 where the TFT 14 is formed is partially removed in a basin shape, and the base 10a. Is preferably formed.
  • it is desirable that both side surfaces of the base portion 10a are formed in a tapered shape having an angle of about 45 ° to 60 ° with respect to one main surface of the glass substrate 10.
  • the base metal layer 110 and the first gate Cu layer 111 are continuously formed by sputtering on the entire surface of the glass substrate 10 on which the base portion 10a is formed.
  • the formed gate layer 11 is subjected to resist coating, exposure, development, etching, photolithography including resist stripping, and the gate line 11a including the gate 11b and the auxiliary capacitance wiring 11c. A pattern is formed.
  • the gate insulating film 16, the semiconductor layer 15, the source line 12a and the drain 12c including the source 12b, the passivation film 17, the interlayer insulating film 18, and the pixel electrode 13 are sequentially formed.
  • the convex or concave base portion 10a is formed on the glass substrate 10, it is not necessary to form a convex portion on the gate 11b, and therefore the process of forming the gate 11b is simplified.
  • FIG. 11 is a cross-sectional view of the TFT substrate 20 according to the third embodiment.
  • a bowl-shaped base portion 19 a protruding from one main surface is formed on the glass substrate 10.
  • the base 19a extends in a direction in which the source 12b and the drain 12c face each other.
  • the base portion 19a is formed by a spin-on glass layer 19 coated on the glass substrate 10.
  • the channel 15a is formed along the convex shape on the base 19a via the gate insulating film 16. For this reason, the channel 15a has a bent portion 15b that extends in a direction in which the source 12b and the drain 12c face each other and is bent on the opposite side to the gate 11b. Therefore, in the TFT 14 according to the present embodiment, the channel width is formed longer than that of the planar channel, as in the other embodiments.
  • the base portion 19a may be formed in a groove shape that is recessed with respect to the main surface of the glass substrate 10. Even in this case, the channel 15a has a bent portion 15b that extends in a direction in which the source 12b and the drain 12c face each other and is bent toward the gate 11b.
  • FIG. 12A to 12D are cross-sectional views sequentially showing manufacturing steps of the TFT substrate 20 according to the third embodiment.
  • the spin-on glass layer 19 is formed on the entire main surface of the glass substrate 10. Specifically, a liquid glass material is dropped onto the glass substrate 10 and formed as a thin film having a uniform thickness by spin coating. Thereafter, the spin-on glass layer 19 is pre-baked in a baking furnace. Subsequently, a photolithography process including resist coating, exposure, development, etching, and resist stripping is performed on the formed spin-on glass layer 19, thereby forming a base 19a as shown in FIG. 12B.
  • the region where the TFT 14 is formed in the spin-on glass layer 19 is partially removed in a basin shape, and the base portion Preferably 19a is formed. Moreover, it is desirable that both side surfaces of the base portion 19a are formed in a tapered shape that forms an angle of about 45 ° to 60 ° with respect to one main surface of the glass substrate 10.
  • the spin-on glass may be colored in order to facilitate alignment in the subsequent steps. However, when coloring the spin-on glass, it is necessary to remove the spin-on glass layer 19 in the region to be the opening so as not to affect the displayed image.
  • the base metal layer 110 and the first gate Cu layer 111 are continuously formed by sputtering on the entire surface of the glass substrate 10 on which the base portion 19a is formed.
  • a pattern of the gate 11b is formed by photolithography.
  • a pattern of the gate line 11a including the gate 11b and the auxiliary capacitance line 11c is also formed.
  • the gate insulating film 16, the semiconductor layer 15, the source line 12a and drain 12c including the source 12b, the passivation film 17, the interlayer insulating film 18, and the pixel electrode 13 are sequentially formed. 11 is manufactured.
  • the spin-on glass used for forming the base portion 19a is a glass material, and therefore has similar material characteristics to the glass substrate 10, and therefore has a low internal stress when formed on the glass substrate 10. Therefore, defects such as cracks are unlikely to occur. Therefore, there is an advantage that the patterning of the base portion 19a is easy even in manufacturing a large TFT substrate.
  • the spin-on glass since the spin-on glass has substantially the same refractive index as that of the glass substrate 10 and has a high light transmittance, the influence on the optical quality of the display panel 2 by forming the spin-on glass layer 19 on the glass substrate 10. There are few.
  • a bowl-shaped base portion 19 a protruding from one main surface is formed on the glass substrate 10. ing.
  • the base portion 19a is formed of spin-on glass having photosensitivity.
  • Other configurations are the same as those in the third embodiment.
  • the spin-on glass layer 19 having photosensitivity is formed on the entire main surface of the glass substrate 10 by spin coating. Subsequently, exposure and development are performed on the formed spin-on glass layer 19 having photosensitivity, and a pattern of the base portion 19a is formed as in the case shown in FIG. 12B. After pattern formation, the spin-on glass layer 19 is post-baked.
  • the base metal layer 110 and the first gate Cu layer 111 are continuously formed by sputtering on the entire surface of the glass substrate 10 on which the base portion 19a is formed, and the gate is further formed by photolithography.
  • a pattern of the gate line 11a including 11b and the auxiliary capacitance line 11c is formed.
  • the gate insulating film 16, the semiconductor layer 15, the source line 12a and drain 12c including the source 12b, the passivation film 17, the interlayer insulating film 18, and the pixel electrode 13 are sequentially formed, and the TFT The substrate 20 is manufactured.
  • the spin-on glass since the spin-on glass has photosensitivity, when the pattern of the base portion 19a is formed from the spin-on glass layer 19, a step of applying a photoresist to the spin-on glass layer 19, an etching step, and a coating step are performed. Any step of stripping the photoresist is unnecessary. Therefore, the TFT substrate according to the present embodiment has an advantage that the number of manufacturing steps is small because a photoresist is unnecessary in addition to the advantage of the third embodiment.
  • the display device may not include a television tuner and a decoder.
  • the display device is not limited to an active matrix liquid crystal display device.
  • the display device may be an active matrix organic electroluminescence (EL) display device.
  • EL active matrix organic electroluminescence

Abstract

Provided is a thin film transistor 14 that is equipped with: a gate 11b; an insulating film covering the gate 11b; a semiconductor layer 15 formed on the insulating film; and a source 12b and a drain 12c formed on the semiconductor layer 15, said source and drain being separated from each other. A space between the source 12b and the drain 12c of the semiconductor layer 15 is a channel 15a. The thin film transistor 14 is characterized in that the channel 15a is extending in the direction in which the source 12b and the drain 12c face each other, and the channel has a bent portion bent to the gate 11b side or to the side opposite to the gate 11b. Also provided are a TFT substrate equipped with the thin film transistor 14, and a method for manufacturing the TFT substrate. In the present invention, the width of the channel 15a is increased, and on-current reduction can be suppressed even in the cases where the thin film transistor 14 projection area on the TFT substrate is reduced, and specifically, the present invention is advantageous to large TFT substrates.

Description

薄膜トランジスタ、ＴＦＴ基板、表示装置及びＴＦＴ基板の製造方法Thin film transistor, TFT substrate, display device, and method for manufacturing TFT substrate
　本発明は、薄膜トランジスタ、ＴＦＴ基板、ＴＦＴ基板を有する表示パネルを備える表示装置、及びＴＦＴ基板の製造方法に関する。 The present invention relates to a thin film transistor, a TFT substrate, a display device including a display panel having a TFT substrate, and a method for manufacturing the TFT substrate.
　液晶表示装置が近年広く普及している。液晶表示装置は、薄膜トランジスタ（ＴＦＴ, Thin Film Transistor）及び薄膜トランジスタに接続された透明な画素電極がマトリクス状に形成されたＴＦＴ基板と、ＴＦＴ基板と対向するカラーフィルタ（ＣＦ）基板とを有する表示パネルを備える。ＴＦＴ基板とＣＦ基板との間には液晶材料が封入されている。液晶表示装置は更に、表示パネルに光を照射するバックライトを備える。 Liquid crystal display devices have become widespread in recent years. A liquid crystal display device includes a TFT substrate in which transparent pixel electrodes connected to a thin film transistor (TFT, Thin Film Transistor) and a thin film transistor are formed in a matrix, and a color filter (CF) substrate facing the TFT substrate. Is provided. A liquid crystal material is sealed between the TFT substrate and the CF substrate. The liquid crystal display device further includes a backlight for irradiating the display panel with light.
　液晶表示装置においては、ＴＦＴが画素電極への電圧印加のオン又はオフのスイッチングを制御する。オンにされたＴＦＴに接続された画素電極に印加された電圧により表示パネル内の液晶分子の向きが各画素又はサブ画素単位で変化し、光透過率が制御される。光透過率が画素又はサブ画素単位で制御された表示パネルにバックライトから光が照射されることにより、表示パネルに画像が表示される。 In the liquid crystal display device, the TFT controls on / off switching of voltage application to the pixel electrode. The direction of the liquid crystal molecules in the display panel changes in units of each pixel or sub-pixel by the voltage applied to the pixel electrode connected to the turned-on TFT, and the light transmittance is controlled. An image is displayed on the display panel by irradiating light from the backlight onto the display panel whose light transmittance is controlled in units of pixels or sub-pixels.
　液晶表示装置は、画質の向上のために高精細化が求められている。液晶表示装置が高精細化された場合、１つの画素又はサブ画素あたりの面積は小さくなる。１つの画素又はサブ画素あたりの面積のうち光が透過する面積の割合を示す開口率を高精細化により減少させないためには、光が透過しないＴＦＴの面積が同様に小さくなる必要がある。 Liquid crystal display devices are required to have high definition in order to improve image quality. When the liquid crystal display device has a higher definition, the area per pixel or sub-pixel becomes smaller. In order to prevent the aperture ratio indicating the ratio of the area through which light is transmitted out of the area per pixel or sub-pixel from being reduced by high definition, the area of the TFT through which light is not transmitted needs to be similarly reduced.
　ＴＦＴの面積が小さくなると、ＴＦＴのチャネル幅が短くなるため、ＴＦＴのオン電流が小さくなる。ＴＦＴのオン電流が小さくなると、画素電極が十分に駆動できなくなり、表示パネルに画像を表示できなくなる。斯かる問題に対して、特許文献１には、チャネルが立体的に形成されているために、平面的にチャネルが形成された場合と比較してチャネル幅が長いＴＦＴが開示されている。したがって、特許文献１のＴＦＴにおいては、ＴＦＴ基板上の投影面積が小さくなってもオン電流の減少が抑制される。 When the area of the TFT is reduced, the channel width of the TFT is shortened, so that the on-current of the TFT is reduced. If the on-current of the TFT is reduced, the pixel electrode cannot be driven sufficiently and an image cannot be displayed on the display panel. In order to solve such a problem, Patent Document 1 discloses a TFT having a channel width longer than that in the case where the channel is formed in a plane because the channel is formed in three dimensions. Therefore, in the TFT of Patent Document 1, a decrease in on-current is suppressed even when the projected area on the TFT substrate is reduced.
特開２０１０－１０３１４１号公報JP 2010-103141 A
　しかしながら、特許文献１に開示されているＴＦＴはトップゲート型ＴＦＴである。トップゲート型ＴＦＴを用いたＴＦＴ基板は、製造時における工程数が比較的多いため、大型のＴＦＴ基板の製造に対して不利である。 However, the TFT disclosed in Patent Document 1 is a top gate type TFT. A TFT substrate using a top gate type TFT is disadvantageous for manufacturing a large-sized TFT substrate because the number of steps in manufacturing is relatively large.
　本発明は斯かる事情に鑑みてなされたものであり、その目的は、ＴＦＴ基板上の投影面積が小さくなった場合でもオン電流の減少を抑制することが可能であって大型のＴＦＴ基板の製造に有利な薄膜トランジスタ、該薄膜トランジスタが形成されたＴＦＴ基板、及び該ＴＦＴ基板を備える表示装置、並びにＴＦＴ基板の製造方法を提供することにある。 The present invention has been made in view of such circumstances, and an object thereof is to manufacture a large-sized TFT substrate that can suppress a decrease in on-current even when the projected area on the TFT substrate is reduced. An advantageous thin film transistor, a TFT substrate on which the thin film transistor is formed, a display device including the TFT substrate, and a method for manufacturing the TFT substrate.
　本発明に係る薄膜トランジスタは、ゲートと、該ゲートを覆う絶縁膜と、該絶縁膜の上に形成され、チャネルを有する半導体層と、該半導体層の上に間隔を空けて対向するように形成されたソース及びドレインとを備え、前記ソースとドレインとの間に前記チャネルが位置する薄膜トランジスタにおいて、前記チャネルは、前記ソースとドレインとが対向する方向に延び、前記ゲート側又は前記ゲートとは反対側に屈曲している屈曲部を有することを特徴とする。 A thin film transistor according to the present invention is formed on a gate, an insulating film covering the gate, a semiconductor layer having a channel, and a semiconductor layer having a channel, facing the semiconductor layer with a space therebetween. A thin film transistor including a source and a drain, wherein the channel is located between the source and the drain, the channel extending in a direction in which the source and the drain face each other, and the gate side or the side opposite to the gate It is characterized by having a bent portion that is bent.
　本発明にあっては、チャネルが立体的な屈曲部を有するため、平面的なチャネルと比較して、チャネル上であってソースとドレインとが相対する方向に垂直な方向の長さ、すなわちチャネル幅が長く、したがってオン電流が大きい。 In the present invention, since the channel has a three-dimensional bent portion, the length in the direction perpendicular to the direction in which the source and the drain face each other on the channel as compared with the planar channel, that is, the channel Long width and therefore high on-current.
　本発明に係る薄膜トランジスタは、前記ゲートは、前記ソースとドレインとが対向する方向に延び、前記チャネル側に突出した凸部、又は、前記ソースとドレインとが対向する方向に延び、前記チャネルとは反対側に窪んだ凹部を有し、前記屈曲部は、前記凸部又は前記凹部の形状に沿って形成されていることを特徴とする。 In the thin film transistor according to the present invention, the gate extends in a direction in which the source and the drain face each other, protrudes toward the channel side, or extends in a direction in which the source and the drain face each other. It has a concave portion which is recessed on the opposite side, and the bent portion is formed along the shape of the convex portion or the concave portion.
　本発明にあっては、チャネルがゲートの凸部又は凹部に沿うことによって屈曲部が形成される。したがって、屈曲部を形成するために絶縁膜にパターンを形成する必要がなく、絶縁膜と他層との境界面の清浄性が保たれる。 In the present invention, the bent portion is formed by the channel along the convex portion or concave portion of the gate. Therefore, it is not necessary to form a pattern in the insulating film in order to form the bent portion, and the cleanliness of the boundary surface between the insulating film and the other layer is maintained.
　本発明に係る薄膜トランジスタは、前記ゲートの下層に、前記ソースとドレインとが対向する方向に延びるように形成された凸状又は凹状の基部を備え、前記屈曲部は、前記基部の形状に沿って形成されていることを特徴とする。 The thin film transistor according to the present invention includes a convex or concave base portion formed in a lower layer of the gate so as to extend in a direction in which the source and the drain face each other, and the bent portion follows the shape of the base portion. It is formed.
　本発明にあっては、チャネルが基部の形状に沿うことによって屈曲部が形成される。したがって、屈曲部を形成するために絶縁膜にパターンを形成する必要がなく、絶縁膜と他層との境界面の清浄性が保たれる。 In the present invention, the bent portion is formed when the channel follows the shape of the base portion. Therefore, it is not necessary to form a pattern in the insulating film in order to form the bent portion, and the cleanliness of the boundary surface between the insulating film and the other layer is maintained.
　本発明に係るＴＦＴ基板は、基板と、該基板の一の主面上に形成されたゲートと、該ゲートを覆う絶縁膜と、該絶縁膜の上に形成され、チャネルを有する半導体層と、該半導体層の上に間隔を空けて対向するように形成されたソース及びドレインとを備え、前記ソースとドレインとの間に前記チャネルが位置するＴＦＴ基板において、前記チャネルは、前記ソースとドレインとが対向する方向に延び、前記ゲート側又は前記ゲートとは反対側に屈曲している屈曲部を有することを特徴とする。 A TFT substrate according to the present invention includes a substrate, a gate formed on one main surface of the substrate, an insulating film covering the gate, a semiconductor layer formed on the insulating film and having a channel, A TFT substrate having a source and a drain formed on the semiconductor layer so as to face each other with a space therebetween, wherein the channel is located between the source and the drain; Has a bent portion that extends in the opposite direction and is bent on the gate side or the opposite side of the gate.
　本発明にあっては、チャネルが立体的な屈曲部を有するため、平面的なチャネルと比較して、チャネル上であってソースとドレインとが相対する方向に垂直な方向の長さ、すなわちチャネル幅が長く、したがってオン電流が大きい。 In the present invention, since the channel has a three-dimensional bent portion, the length in the direction perpendicular to the direction in which the source and the drain face each other on the channel as compared with the planar channel, that is, the channel Long width and therefore high on-current.
　本発明に係るＴＦＴ基板は、前記ゲートは、前記ソースとドレインとが対向する方向に延び、前記チャネル側に突出した凸部、又は、前記ソースとドレインとが対向する方向に延び、前記チャネルとは反対側に窪んだ凹部を有し、前記屈曲部は、前記凸部又は前記凹部の形状に沿って形成されていることを特徴とする。 In the TFT substrate according to the present invention, the gate extends in a direction in which the source and the drain face each other, protrudes toward the channel, or extends in a direction in which the source and the drain face each other, Has a concave portion recessed on the opposite side, and the bent portion is formed along the shape of the convex portion or the concave portion.
　本発明にあっては、チャネルが凸部又は凹部の形状に沿うことによって屈曲部が形成される。したがって、屈曲部を形成するために絶縁膜にパターンを形成する必要がなく、絶縁膜と他層との境界面の清浄性が保たれる。 In the present invention, the bent portion is formed when the channel follows the shape of the convex portion or the concave portion. Therefore, it is not necessary to form a pattern in the insulating film in order to form the bent portion, and the cleanliness of the boundary surface between the insulating film and the other layer is maintained.
　本発明に係るＴＦＴ基板は、前記一の主面上の前記ゲートの下層に、前記ソースとドレインとが対向する方向に延びるように形成された凸状又は凹状の基部を備え、前記屈曲部は、前記基部の形状に沿って形成されていることを特徴とする。 The TFT substrate according to the present invention includes a convex or concave base formed in a lower layer of the gate on the one main surface so as to extend in a direction in which the source and the drain face each other, and the bent portion includes And formed along the shape of the base.
　本発明にあっては、薄膜トランジスタのチャネルが基部の形状に沿うことによって屈曲部が形成される。したがって、屈曲部を形成するために絶縁膜にパターンを形成する必要がなく、絶縁膜と他層との境界面の清浄性が保たれる。 In the present invention, the bent portion is formed when the channel of the thin film transistor follows the shape of the base. Therefore, it is not necessary to form a pattern in the insulating film in order to form the bent portion, and the cleanliness of the boundary surface between the insulating film and the other layer is maintained.
　本発明に係るＴＦＴ基板は、前記基部は、前記基板の一部であることを特徴とする。 The TFT substrate according to the present invention is characterized in that the base is a part of the substrate.
　本発明にあっては、基部は基板の一部であるため、基部を形成するために他の材料を用いる必要がない。 In the present invention, since the base is a part of the substrate, it is not necessary to use other materials to form the base.
　本発明に係るＴＦＴ基板は、前記基板はガラス基板であり、前記基部はスピンオンガラスにより形成されていることを特徴とする。 The TFT substrate according to the present invention is characterized in that the substrate is a glass substrate and the base is formed of spin-on glass.
　本発明にあっては、前記基部はスピンオンガラスで形成されているため、ガラス基板に対する親和性が高い。したがって、基部の形成が容易である。 In the present invention, since the base is made of spin-on glass, it has a high affinity for the glass substrate. Therefore, it is easy to form the base.
　本発明に係る表示装置は、上述のいずれか一つのＴＦＴ基板を有する表示パネルを備えることを特徴とする。 A display device according to the present invention includes a display panel having any one of the TFT substrates described above.
　本発明にあっては、表示装置は上述のＴＦＴ基板を備えるため、薄膜トランジスタのＴＦＴ基板上の投影面積が減少してもオン電流の減少が抑制される。 In the present invention, since the display device includes the above-described TFT substrate, even if the projected area of the thin film transistor on the TFT substrate is reduced, a decrease in on-current is suppressed.
　本発明に係るＴＦＴ基板の製造方法は、基板上に金属薄膜を形成し、該金属薄膜上にレジストを塗布し、半透過部を有するフォトマスクを用いて前記レジストに露光し、前記レジストを現像した後、前記金属薄膜をエッチングしてゲートを形成し、該ゲートを部分的にエッチングして、一方向に延びる凸部又は凹部を前記ゲートに形成し、該ゲートが形成された基板上に絶縁膜及び半導体層を順に形成し、該半導体層上に金属薄膜を形成し、該金属薄膜をエッチングして、前記半導体層のうち前記凸部又は凹部上に形成された部分を挟んで前記一方向に対向するソース及びドレインを形成することを特徴とする。 The TFT substrate manufacturing method according to the present invention includes forming a metal thin film on the substrate, applying a resist on the metal thin film, exposing the resist using a photomask having a semi-transmissive portion, and developing the resist. Then, the metal thin film is etched to form a gate, the gate is partially etched to form a convex portion or a concave portion extending in one direction on the gate, and is insulated on the substrate on which the gate is formed. A film and a semiconductor layer are sequentially formed, a metal thin film is formed on the semiconductor layer, the metal thin film is etched, and the one direction is sandwiched between portions of the semiconductor layer formed on the convex portion or the concave portion. And a source and a drain opposite to each other.
　本発明にあっては、レジストが塗布された金属薄膜に対して半透過部を有するフォトマスクを用いた１回の露光と２回のエッチングとを行うことにより、金属配線上に凸部又は凹部を形成する。したがって、凸部又は凹部形成のための露光が１回でよく、製造工程が簡略化される。 In the present invention, a convex portion or a concave portion is formed on the metal wiring by performing one-time exposure and two-time etching using a photomask having a semi-transmissive portion on the metal thin film coated with the resist. Form. Therefore, the exposure for forming the convex portion or the concave portion may be performed once, and the manufacturing process is simplified.
　本発明に係るＴＦＴ基板の製造方法は、基板をエッチングして一方向に延びる凸状又は凹状のパターンを形成し、該パターンが形成された前記基板上に金属薄膜を形成し、該金属薄膜をエッチングして前記パターンの上にゲートを形成し、該ゲートが形成された基板上に絶縁膜及び半導体層を順に形成し、該半導体層上に金属薄膜を形成し、該金属薄膜をエッチングして、前記半導体層のうち前記パターン上に形成された部分を挟んで前記一方向に対向するソース及びドレインを形成することを特徴とする。 The TFT substrate manufacturing method according to the present invention includes etching a substrate to form a convex or concave pattern extending in one direction, forming a metal thin film on the substrate on which the pattern is formed, and forming the metal thin film on the substrate. Etching to form a gate on the pattern, sequentially forming an insulating film and a semiconductor layer on the substrate on which the gate is formed, forming a metal thin film on the semiconductor layer, etching the metal thin film, A source and a drain that are opposed to each other in one direction across a portion of the semiconductor layer formed on the pattern are formed.
　本発明にあっては、ガラス基板に凸状又は凹状のパターンを形成する。したがって、金属配線に立体的なパターンを形成するために金属薄膜より下層に別の薄膜を形成する必要がなく、製造工程が簡略化される。 In the present invention, a convex or concave pattern is formed on the glass substrate. Therefore, it is not necessary to form another thin film below the metal thin film in order to form a three-dimensional pattern on the metal wiring, and the manufacturing process is simplified.
　本発明に係るＴＦＴ基板の製造方法は、ガラス基板上にスピンオンガラス層を形成し、該スピンオンガラス層をエッチングして一方向に延びる凸状又は凹状のパターンを形成し、該パターンが形成された前記基板上に金属薄膜を形成し、該金属薄膜をエッチングして前記パターンの上にゲートを形成し、前記ゲートが形成された基板上に絶縁膜及び半導体層を順に形成し、該半導体層上に金属薄膜を形成し、該金属薄膜をエッチングして、前記半導体層のうち前記パターン上に形成された部分を挟んで前記一方向に対向するソース及びドレインを形成することを特徴とする。 In the TFT substrate manufacturing method according to the present invention, a spin-on glass layer is formed on a glass substrate, the spin-on glass layer is etched to form a convex or concave pattern extending in one direction, and the pattern is formed. Forming a metal thin film on the substrate; etching the metal thin film to form a gate on the pattern; and sequentially forming an insulating film and a semiconductor layer on the substrate on which the gate is formed; A metal thin film is formed on the substrate, and the metal thin film is etched to form a source and a drain opposed to each other in one direction across a portion of the semiconductor layer formed on the pattern.
　本発明にあっては、ガラス基板上にスピンオンガラス層を形成し、スピンオンガラス層に対してフォトリソグラフィを行い凸状又は凹状のパターンを形成する。スピンオンガラス層はガラス基板と材料特性が似ているため、ガラス基板上に形成された場合に内部応力が少ない。そのため、クラック等の不具合が発生しにくい。したがって、大型のＴＦＴ基板においてもパターン形成が容易である。 In the present invention, a spin-on glass layer is formed on a glass substrate, and photolithography is performed on the spin-on glass layer to form a convex or concave pattern. Since the spin-on glass layer has material characteristics similar to those of the glass substrate, the internal stress is small when formed on the glass substrate. Therefore, defects such as cracks are unlikely to occur. Therefore, pattern formation is easy even on a large TFT substrate.
　本発明に係るＴＦＴ基板の製造方法は、前記スピンオンガラス層は感光性を有することを特徴とする。 The method for manufacturing a TFT substrate according to the present invention is characterized in that the spin-on glass layer has photosensitivity.
　本発明にあっては、感光性を有するスピンオンガラス層が形成されるため、スピンオンガラス層にパターンを形成する際にフォトレジストを使用する必要がない。したがって、製造工程が簡略化される。 In the present invention, since a spin-on glass layer having photosensitivity is formed, it is not necessary to use a photoresist when forming a pattern on the spin-on glass layer. Therefore, the manufacturing process is simplified.
　本発明によれば、ＴＦＴ基板上の投影面積が小さくなった場合でもオン電流の減少を抑制することが可能であり、特に大型のＴＦＴ基板の製造に対して有利である。 According to the present invention, even when the projected area on the TFT substrate is reduced, it is possible to suppress a decrease in on-current, which is particularly advantageous for manufacturing a large TFT substrate.
実施の形態１に係る表示装置の模式的斜視図である。1 is a schematic perspective view of a display device according to Embodiment 1. FIG. 実施の形態１に係る表示パネルの模式的断面図である。3 is a schematic cross-sectional view of the display panel according to Embodiment 1. FIG. 実施の形態１に係るＴＦＴ基板上の配線を示す模式的拡大図である。3 is a schematic enlarged view showing wiring on the TFT substrate according to Embodiment 1. FIG. 実施の形態１に係るＴＦＴ基板上に形成されたＴＦＴの上面拡大図である。3 is an enlarged top view of a TFT formed on the TFT substrate according to Embodiment 1. FIG. 実施の形態１に係るＴＦＴ基板を図４のＶ－Ｖ線で切断した断面図である。FIG. 5 is a cross-sectional view of the TFT substrate according to the first embodiment taken along line VV in FIG. 実施の形態１に係るＴＦＴ基板を図４のＶＩ－ＶＩ線で切断した断面図である。FIG. 5 is a cross-sectional view of the TFT substrate according to the first embodiment taken along line VI-VI in FIG. 実施の形態１に係るＴＦＴ基板の製造工程を順に示す断面図である。FIG. 5 is a cross-sectional view sequentially illustrating a manufacturing process of the TFT substrate according to the first embodiment. 実施の形態１に係るＴＦＴ基板の製造工程を順に示す断面図である。FIG. 5 is a cross-sectional view sequentially illustrating a manufacturing process of the TFT substrate according to the first embodiment. 実施の形態１に係るＴＦＴ基板の製造工程を順に示す断面図である。FIG. 5 is a cross-sectional view sequentially illustrating a manufacturing process of the TFT substrate according to the first embodiment. 実施の形態１に係るＴＦＴ基板の製造工程を順に示す断面図である。FIG. 5 is a cross-sectional view sequentially illustrating a manufacturing process of the TFT substrate according to the first embodiment. 実施の形態１に係るＴＦＴ基板の製造工程を順に示す断面図である。FIG. 5 is a cross-sectional view sequentially illustrating a manufacturing process of the TFT substrate according to the first embodiment. 実施の形態１に係るＴＦＴ基板の製造工程を順に示す断面図である。FIG. 5 is a cross-sectional view sequentially illustrating a manufacturing process of the TFT substrate according to the first embodiment. 実施の形態１に係るＴＦＴ基板の製造工程を順に示す断面図である。FIG. 5 is a cross-sectional view sequentially illustrating a manufacturing process of the TFT substrate according to the first embodiment. 実施の形態１に係るＴＦＴ基板の製造工程を順に示す断面図である。FIG. 5 is a cross-sectional view sequentially illustrating a manufacturing process of the TFT substrate according to the first embodiment. 実施の形態１に係るＴＦＴ基板の製造工程を順に示す断面図である。FIG. 5 is a cross-sectional view sequentially illustrating a manufacturing process of the TFT substrate according to the first embodiment. 実施の形態１に係るＴＦＴ基板の製造工程を順に示す断面図である。FIG. 5 is a cross-sectional view sequentially illustrating a manufacturing process of the TFT substrate according to the first embodiment. 実施の形態１に係るＴＦＴ基板の製造工程を順に示す断面図である。FIG. 5 is a cross-sectional view sequentially illustrating a manufacturing process of the TFT substrate according to the first embodiment. 実施の形態１に係るＴＦＴ基板の製造工程を順に示す断面図である。FIG. 5 is a cross-sectional view sequentially illustrating a manufacturing process of the TFT substrate according to the first embodiment. 実施の形態１の変形例に係るＴＦＴ基板の断面図である。6 is a cross-sectional view of a TFT substrate according to a modification of the first embodiment. FIG. 実施の形態２に係るＴＦＴ基板の断面図である。6 is a cross-sectional view of a TFT substrate according to Embodiment 2. FIG. 実施の形態２に係るＴＦＴ基板の製造工程を順に示す断面図である。FIG. 5 is a cross-sectional view sequentially illustrating a manufacturing process of a TFT substrate according to a second embodiment. 実施の形態２に係るＴＦＴ基板の製造工程を順に示す断面図である。FIG. 5 is a cross-sectional view sequentially illustrating a manufacturing process of a TFT substrate according to a second embodiment. 実施の形態２に係るＴＦＴ基板の製造工程を順に示す断面図である。FIG. 5 is a cross-sectional view sequentially illustrating a manufacturing process of a TFT substrate according to a second embodiment. 実施の形態３に係るＴＦＴ基板の断面図である。6 is a cross-sectional view of a TFT substrate according to Embodiment 3. FIG. 実施の形態３に係るＴＦＴ基板の製造工程を順に示す断面図である。FIG. 6 is a cross-sectional view sequentially illustrating a manufacturing process of a TFT substrate according to a third embodiment. 実施の形態３に係るＴＦＴ基板の製造工程を順に示す断面図である。FIG. 6 is a cross-sectional view sequentially illustrating a manufacturing process of a TFT substrate according to a third embodiment. 実施の形態３に係るＴＦＴ基板の製造工程を順に示す断面図である。FIG. 6 is a cross-sectional view sequentially illustrating a manufacturing process of a TFT substrate according to a third embodiment. 実施の形態３に係るＴＦＴ基板の製造工程を順に示す断面図である。FIG. 6 is a cross-sectional view sequentially illustrating a manufacturing process of a TFT substrate according to a third embodiment.
　以下、本発明をその実施の形態を示す図面に基づいて詳述する。 Hereinafter, the present invention will be described in detail with reference to the drawings showing embodiments thereof.
（実施の形態１）
　図１は、実施の形態１に係る表示装置１の模式的斜視図である。図２は、実施の形態１に係る表示パネル２の模式的断面図である。図３は、実施の形態１に係るＴＦＴ基板２０上の配線を示す模式的拡大図である。図４は、実施の形態１に係るＴＦＴ基板２０上に形成されたＴＦＴ１４の上面拡大図である。 (Embodiment 1)
FIG. 1 is a schematic perspective view of a display device 1 according to the first embodiment. FIG. 2 is a schematic cross-sectional view of the display panel 2 according to the first embodiment. FIG. 3 is a schematic enlarged view showing wiring on the TFT substrate 20 according to the first embodiment. FIG. 4 is an enlarged top view of the TFT 14 formed on the TFT substrate 20 according to the first embodiment.
　表示装置１は例えば、アクティブマトリクス型の液晶表示装置である。また、表示装置１は液晶分子の配向制御方法として、例えば縦電界駆動方式の一種であるＶＡ（Vertical Alignment）方式を採用する。ただし、表示装置１は横電界駆動方式であるＩＰＳ（In-Plane-Switching）方式を採用するものであってもよい。 The display device 1 is, for example, an active matrix liquid crystal display device. In addition, the display device 1 employs, for example, a VA (Vertical Alignment) method, which is a kind of vertical electric field driving method, as a liquid crystal molecule alignment control method. However, the display device 1 may adopt an IPS (In-Plane-Switching) method that is a lateral electric field driving method.
　表示装置１は、画像が表示される矩形状の表示パネル２と、該表示パネル２に光を照射するバックライト（不図示）とを備える。表示装置１は更に、アンテナ（不図示）からテレビジョン放送波を受信するテレビジョンチューナ３と、符号化されたテレビジョン放送波を画像信号に復号するデコーダ４とを備える。 The display device 1 includes a rectangular display panel 2 on which an image is displayed, and a backlight (not shown) that irradiates the display panel 2 with light. The display device 1 further includes a television tuner 3 that receives a television broadcast wave from an antenna (not shown), and a decoder 4 that decodes the encoded television broadcast wave into an image signal.
　表示装置１においては、例えばテレビジョンチューナ３により受信されたテレビジョン放送波がデコーダ４により画像信号に復号される。復号された画像信号に基づいて表示パネル２に画像が表示される。表示装置１は、他に図示しない画像信号入力端子を備え、該画像信号入力端子に入力される画像信号に基づいて画像を表示してもよい。 In the display device 1, for example, a television broadcast wave received by the television tuner 3 is decoded into an image signal by the decoder 4. An image is displayed on the display panel 2 based on the decoded image signal. The display device 1 may further include an image signal input terminal (not shown) and display an image based on an image signal input to the image signal input terminal.
　図２に示すように、表示パネル２は、ガラス製で矩形状のＴＦＴ基板２０と、ＴＦＴ基板２０に対向し、ＴＦＴ基板２０より僅かに小さいガラス製で矩形状のカラーフィルタ（ＣＦ）基板２１とを備える。ＴＦＴ基板２０とＣＦ基板２１との間には液晶層２２が設けられている。ＴＦＴ基板２０とＣＦ基板２１とは、ＴＦＴ基板２０及びＣＦ基板２１の周縁部に接着された枠状のシール材２３により貼り合わされている。液晶層２２は、ＴＦＴ基板２０とＣＦ基板２１との間にシール材２３により液晶材料が封入されて形成されている。 As shown in FIG. 2, the display panel 2 includes a glass-made rectangular TFT substrate 20 and a glass-made rectangular color filter (CF) substrate 21 facing the TFT substrate 20 and slightly smaller than the TFT substrate 20. With. A liquid crystal layer 22 is provided between the TFT substrate 20 and the CF substrate 21. The TFT substrate 20 and the CF substrate 21 are bonded together by a frame-shaped sealing material 23 bonded to the peripheral portions of the TFT substrate 20 and the CF substrate 21. The liquid crystal layer 22 is formed by sealing a liquid crystal material with a sealing material 23 between the TFT substrate 20 and the CF substrate 21.
　図３に示すように、ＴＦＴ基板２０上にはマトリクス状に複数のゲート線１１ａ及びソース線１２ａが配されている。図３においては、左右方向がＴＦＴ基板の長手方向であり、上下方向がＴＦＴ基板の短手方向である。ゲート線１１ａはＴＦＴ基板２０の短手方向に等間隔に並べられ、長手方向に延びている。ソース線１２ａはＴＦＴ基板２０の長手方向に等間隔に並べられ、短手方向に延びている。ゲート線１１ａとソース線１２ａとは、ＴＦＴ基板上の異なる層に形成されている。更に、各ゲート線１１ａの間には、補助容量配線１１ｃがゲート線１１ａに平行に配されている。ゲート線１１ａと補助容量配線１１ｃとはＴＦＴ基板２０上の同じ層に形成されている。ゲート線１１ａ及び補助容量配線１１ｃは、例えば酸化シリコン（ＳｉＯｘ）により、ＴＦＴ基板２０の端部を除く略全体にわたって形成されたゲート絶縁膜１６（図５、図６参照）により覆われている。ソース線１２ａは、ゲート絶縁膜１６上に形成されている。すなわち、ゲート１１ａ線とソース線１２ａと補助容量配線１１ｃとは互いに電気的に独立している。 As shown in FIG. 3, a plurality of gate lines 11a and source lines 12a are arranged on the TFT substrate 20 in a matrix. In FIG. 3, the horizontal direction is the longitudinal direction of the TFT substrate, and the vertical direction is the short direction of the TFT substrate. The gate lines 11a are arranged at equal intervals in the lateral direction of the TFT substrate 20 and extend in the longitudinal direction. The source lines 12a are arranged at equal intervals in the longitudinal direction of the TFT substrate 20 and extend in the short direction. The gate line 11a and the source line 12a are formed in different layers on the TFT substrate. Further, an auxiliary capacitance line 11c is arranged between the gate lines 11a in parallel with the gate line 11a. The gate line 11 a and the auxiliary capacitance line 11 c are formed in the same layer on the TFT substrate 20. The gate line 11a and the auxiliary capacitance line 11c are covered with a gate insulating film 16 (see FIGS. 5 and 6) formed over substantially the entire surface excluding the end portion of the TFT substrate 20, for example, with silicon oxide (SiOx). The source line 12 a is formed on the gate insulating film 16. That is, the gate 11a line, the source line 12a, and the storage capacitor line 11c are electrically independent from each other.
　ＴＦＴ基板２０上のゲート線１１ａとソース線１２ａとにより区切られた矩形領域夫々には、一つの角が切り欠けられた矩形状の画素電極１３が、ＩＴＯ（Indium Tin Oxide）等の透明導電膜により形成されている。画素電極１３の切り欠き部には、ＴＦＴ１４が形成されている。 In each of the rectangular regions separated by the gate line 11a and the source line 12a on the TFT substrate 20, a rectangular pixel electrode 13 with one corner notched is formed as a transparent conductive film such as ITO (Indium Tin Oxide). It is formed by. A TFT 14 is formed in the notch portion of the pixel electrode 13.
　図４に示すように、各ＴＦＴ１４は、ゲート１１ｂ、ゲート絶縁膜１６（図５、図６参照）、チャネル１５ａを有する半導体層１５、ソース１２ｂ、及びドレイン１２ｃを有する。各ＴＦＴ１４において、ゲート１１ｂはゲート線１１ａから画素電極１３の切り欠き部に突出している。ゲート１１ｂ上の略全域に、ゲート絶縁膜１６を介して、半導体層１５が形成されている。更に半導体層１５上に、ソース線１２ａから、コの字形状のソース１２ｂが、コの字の開口部がソース線１２ａとは反対側に向くように突出している。ソース１２ｂのコの字の開口部に、ソース１２ｂと略一定の間隔を隔てて、画素電極１３に電気的に接続されたドレイン１２ｃが形成されている。半導体層１５におけるソース１２ｂとドレイン１２ｃとの間の部分はコの字形状に曲がっている。斯かるコの字形状の部分は、チャネル１５ａを構成する。すなわち、ＴＦＴ１４はゲート１１ｂの上にチャネル１５ａが形成されたボトムゲート型ＴＦＴである。ボトムゲート型ＴＦＴは、トップゲート型と比較して製造時の工程数が少ないため、大型のＴＦＴ基板の製造に対して有利である。 As shown in FIG. 4, each TFT 14 includes a gate 11b, a gate insulating film 16 (see FIGS. 5 and 6), a semiconductor layer 15 having a channel 15a, a source 12b, and a drain 12c. In each TFT 14, the gate 11 b protrudes from the gate line 11 a to the notch of the pixel electrode 13. A semiconductor layer 15 is formed over substantially the entire area of the gate 11b with a gate insulating film 16 therebetween. Further, a U-shaped source 12b protrudes from the source line 12a on the semiconductor layer 15 so that the U-shaped opening is directed to the opposite side of the source line 12a. A drain 12c electrically connected to the pixel electrode 13 is formed in the U-shaped opening of the source 12b with a substantially constant distance from the source 12b. A portion of the semiconductor layer 15 between the source 12b and the drain 12c is bent in a U shape. Such a U-shaped portion constitutes a channel 15a. That is, the TFT 14 is a bottom gate type TFT in which a channel 15a is formed on the gate 11b. The bottom gate type TFT has an advantage in the production of a large TFT substrate because the number of steps in production is smaller than that of the top gate type.
　図３中に点線で囲んで示す、画素電極１３、ＴＦＴ１４、ゲート線１１ａのうち画素電極１３に図中下側で沿う部分、及びソース線１２ａのうち画素電極１３に図中右側で沿う部分を含む領域は、サブ画素３０である。 Of the pixel electrode 13, TFT 14, and gate line 11 a surrounded by a dotted line in FIG. 3, a portion along the pixel electrode 13 on the lower side in the drawing, and a portion of the source line 12 a along the pixel electrode 13 on the right side in the drawing. The area to be included is the sub-pixel 30.
　ここで画素電極１３は透明であるのに対して、ＴＦＴ１４、ゲート線１１ａ、ソース線１２ａ、及び画素電極１３の下層に配された補助容量配線１１ｃは光を透過させない。各サブ画素３０の全面積のうち光を透過させる部分、すなわちＴＦＴ１４、ゲート線１１ａ、ソース線１２ａ、及び補助容量配線１１ｃを除く部分の面積が占める割合は、開口率と呼ばれる。 Here, while the pixel electrode 13 is transparent, the TFT 14, the gate line 11a, the source line 12a, and the auxiliary capacitance line 11c arranged under the pixel electrode 13 do not transmit light. The proportion of the area of each sub-pixel 30 that occupies light, that is, the area excluding the TFT 14, the gate line 11a, the source line 12a, and the auxiliary capacitance line 11c, is called an aperture ratio.
　ＣＦ基板２１上における、ＴＦＴ基板２０の各サブ画素３０に対向する位置に、Ｒ（Red）、Ｇ（Green）、Ｂ（Blue）の３色のカラーフィルタ（不図示）のいずれかが設けられている。ここで例えば、ＴＦＴ基板の長手方向においては、Ｒ、Ｇ、Ｂの各カラーフィルタが同じ順番で交互に繰り返されるように並べられている。各カラーフィルタの間には光を遮るブラックマトリクス（不図示）が形成されている。更に、各カラーフィルタ及びブラックマトリクス上には、ＩＴＯ等の透明導電膜で形成された単一の共通電極（不図示）が形成されている。だたし、ＩＰＳ方式の液晶表示装置においては、共通電極は、画素電極１３と同様にＴＦＴ基板２０上に形成されている。 One of three color filters (not shown) of R (Red), G (Green), and B (Blue) is provided on the CF substrate 21 at a position facing each sub pixel 30 of the TFT substrate 20. ing. Here, for example, in the longitudinal direction of the TFT substrate, the R, G, and B color filters are arranged so as to be alternately repeated in the same order. A black matrix (not shown) that blocks light is formed between the color filters. Furthermore, a single common electrode (not shown) made of a transparent conductive film such as ITO is formed on each color filter and black matrix. However, in the IPS liquid crystal display device, the common electrode is formed on the TFT substrate 20 in the same manner as the pixel electrode 13.
　隣り合ったＲ、Ｇ、Ｂの３つのカラーフィルタに対向する３つのサブ画素３０により１つの画素が構成されている。 One pixel is composed of three sub-pixels 30 facing the adjacent three R, G, and B color filters.
　次に、ＴＦＴ基板２０の断面構造について詳述する。図５は、実施の形態１に係るＴＦＴ基板２０を図４のＶ－Ｖ線で切断した断面図である。図６は、実施の形態１に係るＴＦＴ基板２０を図４のＶＩ－ＶＩ線で切断した断面図である。ＴＦＴ基板２０は、ガラス基板１０の一の主面上に、ゲート１１ｂを含むゲート線１１ａ及び補助容量配線１１ｃ（図５及び図６には示さず）、ゲート絶縁膜１６、半導体層１５、ソース１２ｂを含むソース線１２ａ及びドレイン１２ｃ、パッシベーション膜１７、層間絶縁膜１８、並びに画素電極１３が、この順番で積層されて構成されている。 Next, the cross-sectional structure of the TFT substrate 20 will be described in detail. FIG. 5 is a cross-sectional view of the TFT substrate 20 according to the first embodiment taken along line VV in FIG. FIG. 6 is a cross-sectional view of the TFT substrate 20 according to the first embodiment taken along line VI-VI in FIG. The TFT substrate 20 has a gate line 11a including a gate 11b and an auxiliary capacitance line 11c (not shown in FIGS. 5 and 6), a gate insulating film 16, a semiconductor layer 15, and a source on one main surface of the glass substrate 10. The source line 12a and the drain 12c including 12b, the passivation film 17, the interlayer insulating film 18, and the pixel electrode 13 are stacked in this order.
　ゲート線１１ａはゲート層１１から形成されている。ゲート層１１は例えば、チタン、クロム又はタンタル等を成分とする下地金属層１１０と、第１ゲートＣｕ層１１１と、チタン、ニッケル又はタングステン等を成分とするエッチストッパ層１１２と、第２ゲートＣｕ層１１３とが、この順にガラス基板１０に積層されて形成されている。第１ゲートＣｕ層１１１及び第２ゲートＣｕ層１１３夫々の厚さは、下地金属層１１０又はエッチストッパ層１１２の厚さより大きい。下地金属層１１０は、Ｃｕとガラス基板１０との接着性を高めるために設けられている。エッチストッパ層１１２は、後述するＴＦＴ基板２０の製造工程において行われるゲート線１１ａ形成時の２段階のエッチングを制御するために設けられている。また、ゲート層１１からは補助容量配線１１ｃも同様に形成されている。尚、Ｃｕの代わりにＡｌ等の他の金属が用いられてもよい。 The gate line 11 a is formed from the gate layer 11. The gate layer 11 includes, for example, a base metal layer 110 containing titanium, chromium, tantalum, or the like, a first gate Cu layer 111, an etch stopper layer 112 containing titanium, nickel, tungsten, or the like, and a second gate Cu. A layer 113 is laminated on the glass substrate 10 in this order. The thickness of each of the first gate Cu layer 111 and the second gate Cu layer 113 is larger than the thickness of the base metal layer 110 or the etch stopper layer 112. The base metal layer 110 is provided to improve the adhesion between Cu and the glass substrate 10. The etch stopper layer 112 is provided to control two-stage etching when forming the gate line 11a, which is performed in the manufacturing process of the TFT substrate 20 described later. In addition, an auxiliary capacitance line 11c is similarly formed from the gate layer 11. Other metals such as Al may be used instead of Cu.
　第２ゲートＣｕ層１１３は、後述するようにドライエッチングによりパターン形成されて、図６に示すゲート１１ｂの上部に、ゲート絶縁膜１６及びチャネル１５ａに対して突出した畝状の凸部１１３ａを形成している。ここで凸部１１３ａは例えば、平面視してコの字形状に形成されたチャネル１５ａのうちＴＦＴ基板２０の長手方向に形成された第１部分１５ａ１及び第２部分１５ａ２を横切るようにして、ＴＦＴ基板２０の短手方向に延びている。換言すると、凸部１１３ａは、チャネル１５ａの第１部分１５ａ１及び第２部分１５ａ２において、ソース１２ｂとドレイン１２ｃとが相対する方向に延びている。また、凸部１１３ａは両側面がテーパ形状を有するように形成されている。テーパ状の両側面は、底面に対して４５°から６０°程度の角度をなすことが望ましい。 The second gate Cu layer 113 is patterned by dry etching as will be described later, and a hook-shaped protrusion 113a protruding from the gate insulating film 16 and the channel 15a is formed on the gate 11b shown in FIG. is doing. Here, for example, the convex portion 113a traverses the first portion 15a1 and the second portion 15a2 formed in the longitudinal direction of the TFT substrate 20 in the channel 15a formed in a U shape in plan view, so that the TFT It extends in the short direction of the substrate 20. In other words, the protrusion 113a extends in the direction in which the source 12b and the drain 12c face each other in the first portion 15a1 and the second portion 15a2 of the channel 15a. Moreover, the convex part 113a is formed so that both sides | surfaces may have a taper shape. Both side surfaces of the taper shape preferably form an angle of about 45 ° to 60 ° with respect to the bottom surface.
　ゲート層１１の上には、前述のようにゲート絶縁膜１６がＴＦＴ基板２０の端部を除く略全体にわたって形成されている。 On the gate layer 11, as described above, the gate insulating film 16 is formed over substantially the entire portion excluding the end portion of the TFT substrate 20.
　半導体層１５は、ゲート絶縁膜１６上に、各ゲート１１ｂが形成されている位置において島状に形成されている。半導体層１５は例えば、非晶質シリコン（ａ－Ｓｉ）を成分とするａ－Ｓｉ層１５０と、ａ－Ｓｉにリン等のドナーが高濃度でドーピングされたｎ＋半導体を成分とするｎ＋層１５１とが、この順に積層されて構成されている。ｎ＋層１５１のキャリア密度はａ－Ｓｉ層１５０より高く、したがってｎ＋層１５１は導電性がａ－Ｓｉ層１５０より高い。ｎ＋層１５１は、ソース１２ｂ及びドレイン１２ｃとａ－Ｓｉ層１５０との間で抵抗率を低くするために設けられている。尚、半導体層１５として、ａ－Ｓｉ以外に多結晶シリコン（ｐ－Ｓｉ）又はＩｎＧａＺｎＯ等の酸化物半導体が用いられてもよい。 The semiconductor layer 15 is formed in an island shape on the gate insulating film 16 at a position where each gate 11b is formed. The semiconductor layer 15 includes, for example, an a-Si layer 150 containing amorphous silicon (a-Si) as a component, and an n + layer containing a component of n + semiconductor in which a donor such as phosphorus is doped at high concentration in a-Si. 151 are stacked in this order. The carrier density of n + layer 151 is higher than that of a-Si layer 150, and therefore n + layer 151 has higher conductivity than a-Si layer 150. The n + layer 151 is provided to reduce the resistivity between the source 12b and drain 12c and the a-Si layer 150. In addition to the a-Si, an oxide semiconductor such as polycrystalline silicon (p-Si) or InGaZnO may be used as the semiconductor layer 15.
　図６に示すように、ゲート１１ｂが凸部１１３ａを有するため、チャネル１５ａを含む半導体層１５には、ゲート絶縁膜１６を介して凸部１１３ａの凸形状に沿ってゲート１１ｂとは反対側に屈曲している屈曲部１５ｂが形成されている。屈曲部１５ｂは、コの字形状のチャネル１５ａの第１部分１５ａ１及び第２部分１５ａ２の一部として、ソース１２ｂとドレイン１２ｃとが相対する方向に延びるように畝状に形成されている。チャネル１５ａの第１部分１５ａ１及び第２部分１５ａ２における半導体層１５の形状に沿った長手方向の長さは、屈曲部１５ｂが形成されない場合とくらべて長い。尚、該長手方向の長さは、チャネル１５ａの第１部分１５ａ１及び第２部分１５ａ２においてソース１２ｂとドレイン１２ｃとが相対する方向に垂直な長さであり、一般にチャネル幅と呼ばれる。 As shown in FIG. 6, since the gate 11b has the convex portion 113a, the semiconductor layer 15 including the channel 15a is provided on the opposite side of the gate 11b along the convex shape of the convex portion 113a with the gate insulating film 16 interposed therebetween. A bent portion 15b that is bent is formed. The bent portion 15b is formed in a bowl shape so as to extend in a direction in which the source 12b and the drain 12c face each other as a part of the first portion 15a1 and the second portion 15a2 of the U-shaped channel 15a. The length in the longitudinal direction along the shape of the semiconductor layer 15 in the first portion 15a1 and the second portion 15a2 of the channel 15a is longer than that in the case where the bent portion 15b is not formed. The length in the longitudinal direction is a length perpendicular to the direction in which the source 12b and the drain 12c face each other in the first portion 15a1 and the second portion 15a2 of the channel 15a, and is generally called a channel width.
　ソース１２ｂを含むソース線１２ａとドレイン１２ｃとは、後述するように、半導体層１５上に形成されたソースドレイン層１２がエッチングされることにより形成されている。ソースドレイン層１２は例えば、Ｃｕにより形成されている。ただし、ソースドレイン層１２は、Ｃｕの代わりにＡｌ等の他の金属により形成されていてもよい。 The source line 12a including the source 12b and the drain 12c are formed by etching the source / drain layer 12 formed on the semiconductor layer 15 as described later. The source / drain layer 12 is made of Cu, for example. However, the source / drain layer 12 may be formed of another metal such as Al instead of Cu.
　ソース１２ｂを含むソース線１２ａ、ドレイン１２ｃ、半導体層１５のチャネル１５ａ、及びゲート絶縁膜１６の上には、それらを覆い保護するパッシベーション膜１７が形成されている。更に、パッシベーション膜１７を覆うように層間絶縁膜１８が形成されている。層間絶縁膜１８の上面はガラス基板１０の主面と平行に形成されており、層間絶縁膜１８より下側の層の凹凸を平坦化する機能を有している。 A passivation film 17 that covers and protects the source line 12a including the source 12b, the drain 12c, the channel 15a of the semiconductor layer 15, and the gate insulating film 16 is formed. Further, an interlayer insulating film 18 is formed so as to cover the passivation film 17. The upper surface of the interlayer insulating film 18 is formed in parallel with the main surface of the glass substrate 10 and has a function of flattening the unevenness of the layer below the interlayer insulating film 18.
　図５、図６に示すように、画素電極１３が層間絶縁膜１８上に形成されている。画素電極１３は、層間絶縁膜１８に開口された図示しないコンタクトホールを介して、ドレイン１２ｃと電気的に接続されている。 As shown in FIGS. 5 and 6, the pixel electrode 13 is formed on the interlayer insulating film 18. The pixel electrode 13 is electrically connected to the drain 12 c through a contact hole (not shown) opened in the interlayer insulating film 18.
　次に表示装置１の動作について説明する。表示装置１において、デコーダ４が復号した画像信号、又は外部の装置から入力された画像信号が、画像処理回路（不図示）に入力される。画像処理回路は画像信号に基づいて、ゲートドライバ及びソースドライバ（共に不図示）に、ソースドライバ制御信号及びゲートドライバ制御信号を夫々出力する。ゲートドライバは、水平同期信号に同期して順次的にゲート線１１ａにゲート信号を出力し、当該ゲート線１１ａに含まれるゲート１１ｂにゲート信号が入力される。ゲート１１ｂにゲート信号が入力された各ＴＦＴ１４がオンになり、ソース１２ｂとドレイン１２ｃとがチャネル１５ａを介して導通する。オンになったＴＦＴ１４のソース１２ｂにソースドライバからソース線１２ａを介してソース信号が入力される。ソース１２ｂに入力されたソース信号は、ドレイン１２ｃを介して各画素電極１３の電位を変化させる。 Next, the operation of the display device 1 will be described. In the display device 1, an image signal decoded by the decoder 4 or an image signal input from an external device is input to an image processing circuit (not shown). The image processing circuit outputs a source driver control signal and a gate driver control signal to a gate driver and a source driver (both not shown) based on the image signal. The gate driver sequentially outputs the gate signal to the gate line 11a in synchronization with the horizontal synchronization signal, and the gate signal is input to the gate 11b included in the gate line 11a. Each TFT 14 to which the gate signal is input to the gate 11b is turned on, and the source 12b and the drain 12c are conducted through the channel 15a. A source signal is input from the source driver to the source 12b of the TFT 14 that is turned on via the source line 12a. The source signal input to the source 12b changes the potential of each pixel electrode 13 through the drain 12c.
　各画素電極１３に対向する共通電極の電位は一定の接地電位に保たれており、したがって各画素電極１３の電位の変化により各画素電極１３と共通電極との間の電圧が変化する。よって、各画素電極１３と共通電極との間に挟まれた液晶分子の向きが変化するため、各サブ画素３０の光透過率が変化する。このようにして、各サブ画素３０において光透過率が制御された表示パネル２にバックライトから光が照射されることにより、表示パネル２に画像が表示される。 The potential of the common electrode facing each pixel electrode 13 is kept at a constant ground potential, and therefore the voltage between each pixel electrode 13 and the common electrode changes due to the change in potential of each pixel electrode 13. Therefore, since the direction of the liquid crystal molecules sandwiched between each pixel electrode 13 and the common electrode changes, the light transmittance of each sub-pixel 30 changes. In this way, the display panel 2 whose light transmittance is controlled in each sub-pixel 30 is irradiated with light from the backlight, whereby an image is displayed on the display panel 2.
　以上に述べたように、本実施の形態に係るＴＦＴ１４においては、ゲート１１ｂは凸部１１３ａを有し、半導体層１５のチャネル１５ａは、凸部１１３ａ上に凸形状に沿ってゲート１１ｂとは反対側に屈曲している屈曲部１５ｂを有する。このため、平面的なチャネルのチャネル幅と比較して、立体的に形成されたチャネル１５ａのチャネル幅は長い。ＴＦＴ１４に流れるオン電流はチャネル幅に比例するため、チャネル１５ａに屈曲部１５ｂを有するＴＦＴ１４はより大きなオン電流を流すことが可能である。したがって、オン電流を減少させることなく、ＴＦＴ１４の投影面積が減少させられ各サブ画素３０の開口率が高められ得る。 As described above, in the TFT 14 according to the present embodiment, the gate 11b has the convex 113a, and the channel 15a of the semiconductor layer 15 is opposite to the gate 11b along the convex shape on the convex 113a. It has the bending part 15b bent to the side. For this reason, the channel width of the three-dimensionally formed channel 15a is longer than the channel width of the planar channel. Since the on-current flowing through the TFT 14 is proportional to the channel width, the TFT 14 having the bent portion 15b in the channel 15a can flow a larger on-current. Therefore, the projected area of the TFT 14 can be reduced and the aperture ratio of each sub-pixel 30 can be increased without reducing the on-current.
　次に、本実施の形態に係るＴＦＴ基板２０の製造方法について説明する。図７Ａから図７Ｌまでは、実施の形態１に係るＴＦＴ基板２０の製造工程を順に示す断面図である。最初に、ガラス基板１０の回路が形成される側の主面が洗浄され、乾燥される。その後、図７Ａに示すように、洗浄された主面の全体にスパッタリングにより連続的に、下地金属層１１０、第１ゲートＣｕ層１１１、エッチストッパ層１１２、及び第２ゲートＣｕ層１１３が順に積層され、金属薄膜からなるゲート層１１が形成される。 Next, a method for manufacturing the TFT substrate 20 according to this embodiment will be described. 7A to 7L are cross-sectional views sequentially showing manufacturing steps of the TFT substrate 20 according to the first embodiment. First, the main surface on the side where the circuit of the glass substrate 10 is formed is cleaned and dried. After that, as shown in FIG. 7A, the base metal layer 110, the first gate Cu layer 111, the etch stopper layer 112, and the second gate Cu layer 113 are sequentially stacked on the entire cleaned main surface by sputtering. As a result, a gate layer 11 made of a metal thin film is formed.
　続いて、図７Ｂに示すように、形成されたゲート層１１の上面全体に、例えばポジ型のフォトレジスト４０が塗布される。フォトレジスト４０が塗布された後、焼成炉でフォトレジスト４０がプリベークされる。次に、図７Ｃに示すように、露光装置によりフォトレジスト４０に、多階調フォトマスク５０を介して露光され、多階調フォトマスク５０に形成されたパターンが光で転写される。多階調フォトマスク５０は、透過部５０ａと遮光部５０ｂと半透過部５０ｃとがパターン形成されたグレイトーンマスク又はハーフトーンマスク等である。多階調フォトマスク５０を使用した露光により、フォトレジスト４０に、半透過部５０ｃにより減光された光が露光された中間露光部分４０ａと、遮光部５０ｂにより光が遮られた未露光部分４０ｂと、透過部５０ａにより光が露光された露光部分４０ｃとからなるパターンが形成される。 Subsequently, as shown in FIG. 7B, for example, a positive photoresist 40 is applied to the entire upper surface of the formed gate layer 11. After the photoresist 40 is applied, the photoresist 40 is pre-baked in a baking furnace. Next, as shown in FIG. 7C, the exposure apparatus exposes the photoresist 40 through the multi-tone photomask 50, and the pattern formed on the multi-tone photomask 50 is transferred with light. The multi-tone photomask 50 is a gray-tone mask or a halftone mask in which a transmissive part 50a, a light-shielding part 50b, and a semi-transmissive part 50c are patterned. By exposure using the multi-tone photomask 50, the intermediate exposure portion 40a where the light reduced by the semi-transmissive portion 50c is exposed to the photoresist 40 and the unexposed portion 40b where light is blocked by the light shielding portion 50b. Then, a pattern including the exposed portion 40c where the light is exposed by the transmission portion 50a is formed.
　露光工程の後、現像液を用いてフォトレジスト４０が現像され、露光部分４０ｃが除去される。このとき、図７Ｄに示すように、中間露光部分４０ａについてはフォトレジスト４０の一部が除去され、フォトレジスト４０の厚さが減少する。未露光部分４０ｂのフォトレジスト４０は第２ゲートＣｕ層１１３上に残る。現像後、ガラス基板１０が洗浄及び乾燥され、更に焼成炉でフォトレジスト４０がポストベークされる。 After the exposure process, the photoresist 40 is developed using a developer, and the exposed portion 40c is removed. At this time, as shown in FIG. 7D, a part of the photoresist 40 is removed from the intermediate exposure portion 40a, and the thickness of the photoresist 40 is reduced. The photoresist 40 in the unexposed portion 40 b remains on the second gate Cu layer 113. After the development, the glass substrate 10 is washed and dried, and the photoresist 40 is post-baked in a baking furnace.
　続いて、図７Ｅに示すように、ウェットエッチング工程においてエッチング液により、ゲート層１１のフォトレジスト４０が除去された部分が除去され、ガラス基板１０上にゲート１１ｂを含むゲート線１１ａ及び補助容量配線１１ｃ（共に図３参照）のパターンが形成される。ウェットエッチング後、同様にガラス基板１０は洗浄及び乾燥される。 Subsequently, as shown in FIG. 7E, a portion of the gate layer 11 where the photoresist 40 is removed is removed by an etchant in a wet etching process, and the gate line 11a including the gate 11b and the auxiliary capacitance wiring are formed on the glass substrate 10. A pattern 11c (both see FIG. 3) is formed. After the wet etching, the glass substrate 10 is similarly cleaned and dried.
　その後、図７Ｆに示すように、アッシング工程においてフォトレジスト４０の中間露光部分４０ａが除去される。続いて図７Ｇに示すように、ドライエッチング工程において、第２ゲートＣｕ層１１３のうち中間露光部分４０ａが剥離された部分が除去され、凸部１１３ａが形成される。このとき、エッチストッパ層１１２が第１ゲートＣｕ層１１１をドライエッチングから保護するため、第１ゲートＣｕ層１１１は除去されない。ドライエッチング工程の後、図７Ｈに示すようにレジスト剥離工程において、残った未露光部分４０ｂが剥離され、更に洗浄及び乾燥される。 Thereafter, as shown in FIG. 7F, the intermediate exposure portion 40a of the photoresist 40 is removed in the ashing process. Subsequently, as shown in FIG. 7G, in the dry etching process, a portion of the second gate Cu layer 113 where the intermediate exposure portion 40a is peeled is removed, and a convex portion 113a is formed. At this time, since the etch stopper layer 112 protects the first gate Cu layer 111 from dry etching, the first gate Cu layer 111 is not removed. After the dry etching step, as shown in FIG. 7H, in the resist stripping step, the remaining unexposed portion 40b is stripped, and further washed and dried.
　上記工程により凸部１１３ａが形成されたゲート１１ｂを含むゲート線１１ａ、及び補助容量配線１１ｃからなるゲート層１１の上に、図７Ｉに示すようにＣＶＤ（Chemical Vapor Deposition）法により、ゲート絶縁膜１６、並びにａ－Ｓｉ層１５０及びｎ＋層１５１から成る半導体層１５が連続的に、積層されて形成される。このとき、ゲート絶縁膜１６、ａ－Ｓｉ層１５０、及びｎ＋層１５１は、層間の境界面の清浄を保つためにＣＶＤチャンバ内で連続的に形成される。形成されたａ－Ｓｉ層１５０及びｎ＋層１５１は、レジスト塗布、露光、現像、エッチング、及びレジスト剥離を含むフォトリソグラフィを経て、図７Ｊに示すようなゲート１１ｂ上のパターンに形成される。 As shown in FIG. 7I, a gate insulating film is formed on the gate layer 11 including the gate line 11a including the gate 11b on which the convex portion 113a is formed by the above process and the auxiliary capacitance wiring 11c by the CVD (Chemical Vapor Deposition) method. 16, and the semiconductor layer 15 composed of the a-Si layer 150 and the n + layer 151 are continuously laminated. At this time, the gate insulating film 16, the a-Si layer 150, and the n + layer 151 are continuously formed in the CVD chamber in order to keep the interface between the layers clean. The formed a-Si layer 150 and n + layer 151 are formed into a pattern on the gate 11b as shown in FIG. 7J through photolithography including resist coating, exposure, development, etching, and resist stripping.
　続いて、スパッタリングにより、ａ－Ｓｉ層１５０及びｎ＋層１５１から成る半導体層１５の上にソースドレイン層１２が形成される。図７Ｋに示すように、形成されたソースドレイン層１２に対して、レジスト塗布、露光、現像、エッチング、及びレジスト剥離を含むフォトリソグラフィが行われ、ソース１２ｂが形成される。同時に、ソース１２線ａ（図３参照）、及びドレイン１２ｃ（図４、図５参照）も形成される。ｎ＋層１５１のチャネル１５ａに形成された部分はソースドレイン層１２のエッチング時に除去される。その後、図７Ｌに示すように、パッシベーション膜１７、層間絶縁膜１８、及び画素電極１３が順次形成される。 Subsequently, the source / drain layer 12 is formed on the semiconductor layer 15 including the a-Si layer 150 and the n + layer 151 by sputtering. As shown in FIG. 7K, the formed source / drain layer 12 is subjected to photolithography including resist coating, exposure, development, etching, and resist stripping to form a source 12b. At the same time, the source 12 line a (see FIG. 3) and the drain 12c (see FIGS. 4 and 5) are also formed. The portion formed in the channel 15 a of the n + layer 151 is removed when the source / drain layer 12 is etched. Thereafter, as shown in FIG. 7L, a passivation film 17, an interlayer insulating film 18, and a pixel electrode 13 are sequentially formed.
　以上に示したＴＦＴ基板２０の製造工程において、チャネル１５ａに屈曲部１５ｂを設けるための凸部１１３ａはゲート層１１に対する２回のエッチングによりゲート１１ｂ上に形成される。したがって、ゲート絶縁膜１６又はａ－Ｓｉ層１５０に対して２回のエッチングを行う必要がないため、ゲート絶縁膜１６とａ－Ｓｉ層１５０の間の境界面、又はａ－Ｓｉ層１５０とｎ＋層１５１との境界面の清浄性が保たれる。 In the manufacturing process of the TFT substrate 20 described above, the convex portion 113a for providing the bent portion 15b in the channel 15a is formed on the gate 11b by etching twice on the gate layer 11. Therefore, since it is not necessary to perform the etching twice on the gate insulating film 16 or the a-Si layer 150, the boundary surface between the gate insulating film 16 and the a-Si layer 150 or the a-Si layer 150 and the n + The cleanliness of the interface with the layer 151 is maintained.
　また、多階調フォトマスク５０を使用するため、露光回数及び使用されるマスクの枚数が削減され、したがって製造費用が削減される。ただし、多階調フォトマスク以外のフォトマスクを使用する方法が用いられてもよい。 Also, since the multi-tone photomask 50 is used, the number of exposures and the number of masks used are reduced, and thus the manufacturing cost is reduced. However, a method using a photomask other than the multi-tone photomask may be used.
　（実施の形態１の変形例）
　図８は、実施の形態１の変形例に係るＴＦＴ基板２０の断面図である。図８は、実施の形態１の図６に対応する。図８に示すように、本変形例に係るＴＦＴ１４においては、ゲート１１ｂは、ゲート絶縁膜１６及びチャネル１５ａとは反対側に窪み、ソース１２ｂとドレイン１２ｃとが相対する方向に延びる溝状の凹部１１３ｂを有する。チャネル１５ａは、ゲート絶縁膜１６を介して凹部１１３ｂ上に凹形状に沿って形成されている。このためチャネル１５ａは、ソース１２ｂとドレイン１２ｃとが相対する方向に延び、ゲート１１ｂ側に屈曲している屈曲部１５ｂを有する。 (Modification of Embodiment 1)
FIG. 8 is a cross-sectional view of a TFT substrate 20 according to a modification of the first embodiment. FIG. 8 corresponds to FIG. 6 of the first embodiment. As shown in FIG. 8, in the TFT 14 according to this modification, the gate 11b is recessed on the opposite side to the gate insulating film 16 and the channel 15a, and a groove-like recess extending in a direction in which the source 12b and the drain 12c face each other. 113b. The channel 15a is formed along the concave shape on the concave 113b via the gate insulating film 16. For this reason, the channel 15a has a bent portion 15b that extends in a direction in which the source 12b and the drain 12c face each other and is bent toward the gate 11b.
　したがって、本変形例に係るＴＦＴ１４においては、実施の形態１と同様に、平面的なチャネル１５ａと比較してチャネル幅が長く形成される。ＴＦＴ１４に流れるオン電流はチャネル幅に比例するため、チャネル１５ａに屈曲部１５ｂを有するＴＦＴ１４はより大きなオン電流を流すことが可能である。したがって、オン電流を減少させることなく、ＴＦＴ１４の投影面積が減少させられ各サブ画素３０の開口率が高められ得る。 Therefore, in the TFT 14 according to this modification, the channel width is formed longer than that of the planar channel 15a, as in the first embodiment. Since the on-current flowing through the TFT 14 is proportional to the channel width, the TFT 14 having the bent portion 15b in the channel 15a can flow a larger on-current. Therefore, the projected area of the TFT 14 can be reduced and the aperture ratio of each sub-pixel 30 can be increased without reducing the on-current.
　本変形例のその他の構成、及び製造方法は実施の形態１と同様であるため、同一の符号を付して詳細な説明を省略する。 Since the other configurations and the manufacturing method of this modification are the same as those of the first embodiment, the same reference numerals are given and detailed description is omitted.
　（実施の形態２）
　図９は、実施の形態２に係るＴＦＴ基板２０の断面図である。図９は、実施の形態１の図６に対応する。本実施の形態に係るＴＦＴ基板２０においては、ガラス基板１０に、一の主面に対して突出した畝状の基部１０ａが形成されている。基部１０ａはガラス基板１０と一体となっており、ソース１２ｂとドレイン１２ｃとが相対する方向に延びている。チャネル１５ａは、ゲート絶縁膜１６を介して基部１０ａ上に凸形状に沿って形成されている。このため、チャネル１５ａはソース１２ｂとドレイン１２ｃとが相対する方向に延び、ゲート１１ｂとは反対側に屈曲している屈曲部１５ｂを有する。 (Embodiment 2)
FIG. 9 is a cross-sectional view of the TFT substrate 20 according to the second embodiment. FIG. 9 corresponds to FIG. 6 of the first embodiment. In the TFT substrate 20 according to the present embodiment, the glass substrate 10 is formed with a bowl-shaped base portion 10a that protrudes from one main surface. The base 10a is integrated with the glass substrate 10 and extends in a direction in which the source 12b and the drain 12c face each other. The channel 15 a is formed along the convex shape on the base portion 10 a via the gate insulating film 16. For this reason, the channel 15a has a bent portion 15b that extends in a direction in which the source 12b and the drain 12c face each other and is bent on the opposite side to the gate 11b.
　したがって、本実施例に係るＴＦＴ１４においては、実施の形態１と同様に、平面的なチャネルと比較してチャネル幅が長く形成される。ＴＦＴ１４に流れるオン電流はチャネル幅に比例するため、チャネル１５ａに屈曲部１５ｂを有するＴＦＴ１４はより大きなオン電流を流すことが可能である。よって、オン電流が減少することなくＴＦＴ１４の面積を小さくすることができるため、各サブ画素３０の開口率を高めることができる。 Therefore, in the TFT 14 according to this example, the channel width is formed longer than that of the planar channel as in the first embodiment. Since the on-current flowing through the TFT 14 is proportional to the channel width, the TFT 14 having the bent portion 15b in the channel 15a can flow a larger on-current. Therefore, since the area of the TFT 14 can be reduced without reducing the on-current, the aperture ratio of each subpixel 30 can be increased.
　尚、基部１０ａはガラス基板１０の主面に対して窪んだ溝状に形成されてあってもよい。この場合、基部１０ａ上に形成されたチャネル１５ａはソース１２ｂとドレイン１２ｃとが相対する方向に延び、ゲート１１ｂ側に屈曲している屈曲部１５ｂを有し、同じ効果が得られる。 The base 10 a may be formed in a groove shape that is recessed with respect to the main surface of the glass substrate 10. In this case, the channel 15a formed on the base portion 10a has a bent portion 15b extending in a direction in which the source 12b and the drain 12c face each other and bent toward the gate 11b, and the same effect can be obtained.
　本実施の形態に係るＴＦＴ基板２０のその他の構成は実施の形態１と同様である。 Other configurations of the TFT substrate 20 according to the present embodiment are the same as those of the first embodiment.
　次に、本実施の形態に係るＴＦＴ基板２０の製造方法について説明する。図１０Ａから図１０Ｃまでは、実施の形態２に係るＴＦＴ基板２０の製造工程を順に示す断面図である。初めにガラス基板１０の一の主面全体にフォトレジストを塗布し、露光、現像、エッチング、レジスト剥離を順次行い、図１０Ａに示すように、ガラス基板１０に基部１０ａを含むトレンチパターンを形成する。換言すると、ガラス基板１０に対してトレンチエッチングが行われる。このとき、エッチングで除去されるガラスの量を削減してエッチング液の再利用を容易にするために、ガラス基板１０のうちＴＦＴ１４が形成される領域が盆地状に部分的に除去され、基部１０ａが形成されることが望ましい。また、基部１０ａの両側面は、ガラス基板１０の一の主面に対して４５°から６０°程度の角度をなすテーパ状に形成されることが望ましい。 Next, a method for manufacturing the TFT substrate 20 according to this embodiment will be described. 10A to 10C are cross-sectional views sequentially showing manufacturing steps of the TFT substrate 20 according to the second embodiment. First, a photoresist is applied to the entire main surface of the glass substrate 10, and exposure, development, etching, and resist removal are sequentially performed to form a trench pattern including a base 10a on the glass substrate 10 as shown in FIG. 10A. . In other words, trench etching is performed on the glass substrate 10. At this time, in order to reduce the amount of glass removed by etching and facilitate the reuse of the etching solution, the region of the glass substrate 10 where the TFT 14 is formed is partially removed in a basin shape, and the base 10a. Is preferably formed. Moreover, it is desirable that both side surfaces of the base portion 10a are formed in a tapered shape having an angle of about 45 ° to 60 ° with respect to one main surface of the glass substrate 10.
　続いて、図１０Ｂに示すように、基部１０ａが形成されたガラス基板１０の全面に、スパッタリングによって下地金属層１１０、第１ゲートＣｕ層１１１が連続的に形成される。その後、図１０Ｃに示すように、形成されたゲート層１１に対して、レジスト塗布、露光、現像、エッチング、レジスト剥離を含むフォトリソグラフィにより、ゲート１１ｂを含むゲート線１１ａ、及び補助容量配線１１ｃのパターンが形成される。 Subsequently, as shown in FIG. 10B, the base metal layer 110 and the first gate Cu layer 111 are continuously formed by sputtering on the entire surface of the glass substrate 10 on which the base portion 10a is formed. Thereafter, as shown in FIG. 10C, the formed gate layer 11 is subjected to resist coating, exposure, development, etching, photolithography including resist stripping, and the gate line 11a including the gate 11b and the auxiliary capacitance wiring 11c. A pattern is formed.
　以降、実施の形態１と同様に、ゲート絶縁膜１６、半導体層１５、ソース１２ｂを含むソース線１２ａ及びドレイン１２ｃ、パッシベーション膜１７、層間絶縁膜１８、並びに画素電極１３が順次形成され、図９に示すＴＦＴ基板２０が製造される。 Thereafter, as in the first embodiment, the gate insulating film 16, the semiconductor layer 15, the source line 12a and the drain 12c including the source 12b, the passivation film 17, the interlayer insulating film 18, and the pixel electrode 13 are sequentially formed. The TFT substrate 20 shown in FIG.
　本実施の形態おいては、ガラス基板１０に凸状又は凹状の基部１０ａを形成するため、ゲート１１ｂに凸部を形成する必要がなく、したがってゲート１１ｂを形成する工程が簡略化される。 In the present embodiment, since the convex or concave base portion 10a is formed on the glass substrate 10, it is not necessary to form a convex portion on the gate 11b, and therefore the process of forming the gate 11b is simplified.
　本実施の形態のその他の構成、及び製造方法は実施の形態１と同様であるため、同一の符号を付して詳細な説明を省略する。 Since other configurations and manufacturing methods of the present embodiment are the same as those of the first embodiment, the same reference numerals are given and detailed description thereof is omitted.
　（実施の形態３）
　図１１は、実施の形態３に係るＴＦＴ基板２０の断面図である。本実施の形態においては、ガラス基板１０上に、一の主面に対して突出した畝状の基部１９ａが形成されている。基部１９ａは、ソース１２ｂとドレイン１２ｃとが相対する方向に延びている。ここで基部１９ａは、実施の形態２とは異なり、ガラス基板１０上にコーティングされたスピンオンガラス層１９によって形成されている。チャネル１５ａは、ゲート絶縁膜１６を介して基部１９ａ上に凸形状に沿って形成されている。このため、チャネル１５ａは、ソース１２ｂとドレイン１２ｃとが相対する方向に延び、ゲート１１ｂとは反対側に屈曲している屈曲部１５ｂを有する。したがって、本実施の形態に係るＴＦＴ１４においては、他の実施の形態と同様に、平面的なチャネルと比較してチャネル幅が長く形成される。 (Embodiment 3)
FIG. 11 is a cross-sectional view of the TFT substrate 20 according to the third embodiment. In the present embodiment, a bowl-shaped base portion 19 a protruding from one main surface is formed on the glass substrate 10. The base 19a extends in a direction in which the source 12b and the drain 12c face each other. Here, unlike the second embodiment, the base portion 19a is formed by a spin-on glass layer 19 coated on the glass substrate 10. The channel 15a is formed along the convex shape on the base 19a via the gate insulating film 16. For this reason, the channel 15a has a bent portion 15b that extends in a direction in which the source 12b and the drain 12c face each other and is bent on the opposite side to the gate 11b. Therefore, in the TFT 14 according to the present embodiment, the channel width is formed longer than that of the planar channel, as in the other embodiments.
　尚、基部１９ａはガラス基板１０の主面に対して窪んだ溝状に形成されてあってもよい。この場合であっても、チャネル１５ａは、ソース１２ｂとドレイン１２ｃとが相対する方向に延び、ゲート１１ｂ側に屈曲している屈曲部１５ｂを有する。 The base portion 19a may be formed in a groove shape that is recessed with respect to the main surface of the glass substrate 10. Even in this case, the channel 15a has a bent portion 15b that extends in a direction in which the source 12b and the drain 12c face each other and is bent toward the gate 11b.
　本実施の形態に係るＴＦＴ基板２０のその他の構成は実施の形態２と同様である。 Other configurations of the TFT substrate 20 according to the present embodiment are the same as those of the second embodiment.
　次に、本実施の形態に係るＴＦＴ基板２０の製造方法について説明する。図１２Ａから図１２Ｄまでは、実施の形態３に係るＴＦＴ基板２０の製造工程を順に示す断面図である。最初に、図１２Ａに示すように、ガラス基板１０の一の主面全体にスピンオンガラス層１９が形成される。具体的には、液体状のガラス材料がガラス基板１０に滴下され、スピンコートにより厚さの均一な薄膜として形成される。その後、スピンオンガラス層１９は焼成炉においてプリベークされる。続いて、形成されたスピンオンガラス層１９に対して、レジスト塗布、露光、現像、エッチング、レジスト剥離を含むフォトリソグラフィ工程が行われることにより、図１２Ｂに示すような基部１９ａが形成される。このとき、エッチングで除去されるガラスの量を削減してエッチング液の再利用を容易にするために、スピンオンガラス層１９のうちＴＦＴ１４が形成される領域が盆地状に部分的に除去され、基部１９ａが形成されることが望ましい。また、基部１９ａの両側面は、ガラス基板１０の一の主面に対して４５°から６０°程度の角度をなすテーパ状に形成されることが望ましい。 Next, a method for manufacturing the TFT substrate 20 according to this embodiment will be described. 12A to 12D are cross-sectional views sequentially showing manufacturing steps of the TFT substrate 20 according to the third embodiment. First, as shown in FIG. 12A, the spin-on glass layer 19 is formed on the entire main surface of the glass substrate 10. Specifically, a liquid glass material is dropped onto the glass substrate 10 and formed as a thin film having a uniform thickness by spin coating. Thereafter, the spin-on glass layer 19 is pre-baked in a baking furnace. Subsequently, a photolithography process including resist coating, exposure, development, etching, and resist stripping is performed on the formed spin-on glass layer 19, thereby forming a base 19a as shown in FIG. 12B. At this time, in order to reduce the amount of glass removed by etching and facilitate the reuse of the etching solution, the region where the TFT 14 is formed in the spin-on glass layer 19 is partially removed in a basin shape, and the base portion Preferably 19a is formed. Moreover, it is desirable that both side surfaces of the base portion 19a are formed in a tapered shape that forms an angle of about 45 ° to 60 ° with respect to one main surface of the glass substrate 10.
　また、以降の工程におけるアラインメントを容易にするため、スピンオンガラスが着色されていてもよい。ただし、スピンオンガラスに着色を施す場合には、表示される画像に影響を与えないように、開口部となる領域においてスピンオンガラス層１９が除去される必要がある。 Also, the spin-on glass may be colored in order to facilitate alignment in the subsequent steps. However, when coloring the spin-on glass, it is necessary to remove the spin-on glass layer 19 in the region to be the opening so as not to affect the displayed image.
　その後、実施の形態２と同様に、図１２Ｃに示すように、基部１９ａが形成されたガラス基板１０の全面に、スパッタリングによって下地金属層１１０、第１ゲートＣｕ層１１１が連続的に形成され、更に、図１２Ｄに示すように、フォトリソグラフィにより、ゲート１１ｂのパターンが形成される。同時に、ゲート１１ｂを含むゲート線１１ａ、及び補助容量配線１１ｃ（共に図３参照）のパターンも形成される。 Thereafter, as in the second embodiment, as shown in FIG. 12C, the base metal layer 110 and the first gate Cu layer 111 are continuously formed by sputtering on the entire surface of the glass substrate 10 on which the base portion 19a is formed. Further, as shown in FIG. 12D, a pattern of the gate 11b is formed by photolithography. At the same time, a pattern of the gate line 11a including the gate 11b and the auxiliary capacitance line 11c (both see FIG. 3) is also formed.
　以降、他の実施の形態と同様に、ゲート絶縁膜１６、半導体層１５、ソース１２ｂを含むソース線１２ａ及びドレイン１２ｃ、パッシベーション膜１７、層間絶縁膜１８、並びに画素電極１３が順次形成され、図１１に示すＴＦＴ基板２０が製造される。 Thereafter, as in the other embodiments, the gate insulating film 16, the semiconductor layer 15, the source line 12a and drain 12c including the source 12b, the passivation film 17, the interlayer insulating film 18, and the pixel electrode 13 are sequentially formed. 11 is manufactured.
　本実施の形態において、基部１９ａの形成に使用されるスピンオンガラスはガラス材料であるためガラス基板１０と材料特性が似ており、したがってガラス基板１０上に形成された場合に内部応力が少ない。そのため、クラック等の不具合が発生しにくい。したがって、大型のＴＦＴ基板の製造においても基部１９ａのパターン形成が容易であるという利点を有する。ここで、スピンオンガラスはガラス基板１０と屈折率が略同じであり、且つ光透過率が高いため、スピンオンガラス層１９をガラス基板１０上に形成することによる表示パネル２の光学的品位への影響は少ない。 In the present embodiment, the spin-on glass used for forming the base portion 19a is a glass material, and therefore has similar material characteristics to the glass substrate 10, and therefore has a low internal stress when formed on the glass substrate 10. Therefore, defects such as cracks are unlikely to occur. Therefore, there is an advantage that the patterning of the base portion 19a is easy even in manufacturing a large TFT substrate. Here, since the spin-on glass has substantially the same refractive index as that of the glass substrate 10 and has a high light transmittance, the influence on the optical quality of the display panel 2 by forming the spin-on glass layer 19 on the glass substrate 10. There are few.
　本実施の形態のその他の構成、及び製造方法は他実施の形態と同様であるため、同一の符号を付して詳細な説明を省略する。 Since other configurations and manufacturing methods of the present embodiment are the same as those of the other embodiments, the same reference numerals are given and detailed description is omitted.
　（実施の形態４）
　本実施の形態に係るＴＦＴ基板２０は、図１１で示す実施の形態３に係るＴＦＴ基板と同様に、ガラス基板１０上に、一の主面に対して突出した畝状の基部１９ａが形成されている。ここで、本実施の形態においては、基部１９ａは感光性を有するスピンオンガラスにより形成されている。その他の構成については、実施の形態３と同様である。 (Embodiment 4)
In the TFT substrate 20 according to the present embodiment, like the TFT substrate according to the third embodiment shown in FIG. 11, a bowl-shaped base portion 19 a protruding from one main surface is formed on the glass substrate 10. ing. Here, in the present embodiment, the base portion 19a is formed of spin-on glass having photosensitivity. Other configurations are the same as those in the third embodiment.
　次に、本実施の形態に係るＴＦＴ基板の製造方法について説明する。最初に、実施の形態３の図１２Ａに示す場合と同様に、ガラス基板１０の一の主面全体に感光性を有するスピンオンガラス層１９がスピンコートにより形成される。続いて、形成された感光性を有するスピンオンガラス層１９に対して、露光及び現像が行われ、図１２Ｂに示す場合と同様に基部１９ａのパターンが形成される。パターン形成後、スピンオンガラス層１９はポストベークされる。 Next, a manufacturing method of the TFT substrate according to the present embodiment will be described. First, similarly to the case shown in FIG. 12A of the third embodiment, the spin-on glass layer 19 having photosensitivity is formed on the entire main surface of the glass substrate 10 by spin coating. Subsequently, exposure and development are performed on the formed spin-on glass layer 19 having photosensitivity, and a pattern of the base portion 19a is formed as in the case shown in FIG. 12B. After pattern formation, the spin-on glass layer 19 is post-baked.
　その後、実施の形態２及び３と同様に基部１９ａが形成されたガラス基板１０の全面に、スパッタリングによって下地金属層１１０、第１ゲートＣｕ層１１１が連続的に形成され、更にフォトリソグラフィにより、ゲート１１ｂを含むゲート線１１ａ、及び補助容量配線１１ｃのパターンが形成される。 Thereafter, as in the second and third embodiments, the base metal layer 110 and the first gate Cu layer 111 are continuously formed by sputtering on the entire surface of the glass substrate 10 on which the base portion 19a is formed, and the gate is further formed by photolithography. A pattern of the gate line 11a including 11b and the auxiliary capacitance line 11c is formed.
　以降、他の実施の形態と同様に、ゲート絶縁膜１６、半導体層１５、ソース１２ｂを含むソース線１２ａ及びドレイン１２ｃ、パッシベーション膜１７、層間絶縁膜１８、並びに画素電極１３が順次形成され、ＴＦＴ基板２０が製造される。 Thereafter, as in the other embodiments, the gate insulating film 16, the semiconductor layer 15, the source line 12a and drain 12c including the source 12b, the passivation film 17, the interlayer insulating film 18, and the pixel electrode 13 are sequentially formed, and the TFT The substrate 20 is manufactured.
　本実施の形態においては、スピンオンガラスが感光性を有するため、スピンオンガラス層１９から基部１９ａのパターンを形成する際に、スピンオンガラス層１９にフォトレジストを塗布する工程、エッチング工程、及び塗布されたフォトレジストを剥離する工程がいずれも不要である。したがって、本実施の形態に係るＴＦＴ基板は、実施の形態３の利点に加えて更に、フォトレジストが不要であるために製造工程が少ない利点を有する。 In the present embodiment, since the spin-on glass has photosensitivity, when the pattern of the base portion 19a is formed from the spin-on glass layer 19, a step of applying a photoresist to the spin-on glass layer 19, an etching step, and a coating step are performed. Any step of stripping the photoresist is unnecessary. Therefore, the TFT substrate according to the present embodiment has an advantage that the number of manufacturing steps is small because a photoresist is unnecessary in addition to the advantage of the third embodiment.
　本実施の形態のその他の構成、及び製造方法は他実施の形態と同様であるため、同一の符号を付して詳細な説明を省略する。 Since other configurations and manufacturing methods of the present embodiment are the same as those of the other embodiments, the same reference numerals are given and detailed description is omitted.
　尚、上述の各実施の形態において、表示装置はテレビジョンチューナ及びデコーダを備えていなくても良い。 In each of the above-described embodiments, the display device may not include a television tuner and a decoder.
　また、上述の各実施の形態において、表示装置はアクティブマトリクス型液晶表示装置に限定されない。例えば表示装置はアクティブマトリクス型有機エレクトロルミネッセンス（ＥＬ）表示装置であってもよい。 In each of the above-described embodiments, the display device is not limited to an active matrix liquid crystal display device. For example, the display device may be an active matrix organic electroluminescence (EL) display device.
　今回開示された実施の形態はすべての点で例示であって、制限的なものではないと考えられるべきである。本発明の範囲は、上記した意味ではなく、請求の範囲によって示され、請求の範囲と均等の意味及び範囲内でのすべての変更が含まれることが意図される。 It should be considered that the embodiment disclosed this time is illustrative in all respects and not restrictive. The scope of the present invention is defined not by the above-described meaning but by the scope of claims, and is intended to include all modifications within the meaning and scope equivalent to the scope of claims.
　１　表示装置
　２　表示パネル
　３　テレビジョンチューナ
　４　デコーダ
　１０　ガラス基板
　１０ａ　基部
　１１　ゲート層
　１１ａ　ゲート線
　１１ｂ　ゲート１１ｂ
　１１ｃ　補助容量配線
　１１０　下地金属層
　１１１　第１ゲートＣｕ層
　１１２　エッチストッパ層
　１１３　第２ゲートＣｕ層
　１１３ａ　凸部
　１１３ｂ　凹部
　１２　ソースドレイン層
　１２ａ　ソース線
　１２ｂ　ソース
　１２ｃ　ドレイン
　１３　画素電極
　１４　ＴＦＴ
　１５　半導体層
　１５ａ　チャネル
　１５ｂ　屈曲部
　１５０　ａ－Ｓｉ層
　１５１　ｎ＋層
　１６　ゲート絶縁膜
　１７　パッシベーション膜
　１８　層間絶縁膜
　１９　スピンオンガラス層
　１９ａ　基部
　２０　ＴＦＴ基板
　２１　ＣＦ基板
　２２　液晶層
　２３　シール材
　３０　サブ画素
　４０　フォトレジスト
　５０　多階調フォトマスク DESCRIPTION OF SYMBOLS 1 Display apparatus 2 Display panel 3 Television tuner 4 Decoder 10 Glass substrate 10a Base 11 Gate layer 11a Gate line 11b Gate 11b
11c Auxiliary capacitance wiring 110 Underlying metal layer 111 First gate Cu layer 112 Etch stopper layer 113 Second gate Cu layer 113a Protrusion 113b Concavity 12 Source drain layer 12a Source line 12b Source 12c Drain 13 Pixel electrode 14 TFT
DESCRIPTION OF SYMBOLS 15 Semiconductor layer 15a Channel 15b Bending part 150 a-Si layer 151 n + layer 16 Gate insulating film 17 Passivation film 18 Interlayer insulating film 19 Spin-on glass layer 19a Base 20 TFT substrate 21 CF substrate 22 Liquid crystal layer 23 Sealing material 30 Subpixel 40 Photoresist 50 Multi-tone photomask

Claims (13)

  1. 　ゲートと、該ゲートを覆う絶縁膜と、該絶縁膜の上に形成され、チャネルを有する半導体層と、該半導体層の上に間隔を空けて対向するように形成されたソース及びドレインとを備え、前記ソースとドレインとの間に前記チャネルが位置する薄膜トランジスタにおいて、
    　前記チャネルは、前記ソースとドレインとが対向する方向に延び、前記ゲート側又は前記ゲートとは反対側に屈曲している屈曲部を有することを特徴とする薄膜トランジスタ。     A gate; an insulating film covering the gate; a semiconductor layer having a channel formed on the insulating film; and a source and a drain formed on the semiconductor layer so as to face each other with a space therebetween. In the thin film transistor in which the channel is located between the source and the drain,
    The thin film transistor, wherein the channel has a bent portion that extends in a direction in which the source and the drain face each other and is bent toward the gate side or the opposite side of the gate.
  2. 　前記ゲートは、前記ソースとドレインとが対向する方向に延び、前記チャネル側に突出した凸部、又は、前記ソースとドレインとが対向する方向に延び、前記チャネルとは反対側に窪んだ凹部を有し、
    　前記屈曲部は、前記凸部又は前記凹部の形状に沿って形成されていることを特徴とする請求項１に記載の薄膜トランジスタ。     The gate extends in a direction in which the source and the drain face each other and protrudes toward the channel side, or extends in a direction in which the source and the drain face each other and is recessed in a direction opposite to the channel. Have
    The thin film transistor according to claim 1, wherein the bent portion is formed along a shape of the convex portion or the concave portion.
  3. 　前記ゲートの下層に、前記ソースとドレインとが対向する方向に延びるように形成された凸状又は凹状の基部を備え、
    　前記屈曲部は、前記基部の形状に沿って形成されていることを特徴とする請求項１に記載の薄膜トランジスタ。     A convex or concave base formed so as to extend in a direction in which the source and the drain face each other under the gate,
    The thin film transistor according to claim 1, wherein the bent portion is formed along a shape of the base portion.
  4. 　基板と、該基板の一の主面上に形成されたゲートと、該ゲートを覆う絶縁膜と、該絶縁膜の上に形成され、チャネルを有する半導体層と、該半導体層の上に間隔を空けて対向するように形成されたソース及びドレインとを備え、前記ソースとドレインとの間に前記チャネルが位置するＴＦＴ基板において、
    　前記チャネルは、前記ソースとドレインとが対向する方向に延び、前記ゲート側又は前記ゲートとは反対側に屈曲している屈曲部を有することを特徴とするＴＦＴ基板。     A substrate; a gate formed on one main surface of the substrate; an insulating film covering the gate; a semiconductor layer formed on the insulating film and having a channel; and a gap on the semiconductor layer. In a TFT substrate comprising a source and a drain formed so as to face each other, and the channel is located between the source and the drain,
    The TFT substrate according to claim 1, wherein the channel has a bent portion that extends in a direction in which the source and the drain face each other and is bent on the gate side or the opposite side of the gate.
  5. 　前記ゲートは、前記ソースとドレインとが対向する方向に延び、前記チャネル側に突出した凸部、又は、前記ソースとドレインとが対向する方向に延び、前記チャネルとは反対側に窪んだ凹部を有し、
    　前記屈曲部は、前記凸部又は前記凹部の形状に沿って形成されていることを特徴とする請求項４に記載のＴＦＴ基板。     The gate extends in a direction in which the source and the drain face each other and protrudes toward the channel side, or extends in a direction in which the source and the drain face each other and is recessed in a direction opposite to the channel. Have
    The TFT substrate according to claim 4, wherein the bent portion is formed along a shape of the convex portion or the concave portion.
  6. 　前記一の主面上の前記ゲートの下層に、前記ソースとドレインとが対向する方向に延びるように形成された凸状又は凹状の基部を備え、
    　前記屈曲部は、前記基部の形状に沿って形成されていることを特徴とする請求項４に記載のＴＦＴ基板。     A convex or concave base formed so as to extend in a direction in which the source and the drain face each other below the gate on the one main surface;
    The TFT substrate according to claim 4, wherein the bent portion is formed along the shape of the base portion.
  7. 　前記基部は、前記基板の一部であることを特徴とする請求項６に記載のＴＦＴ基板。 The TFT substrate according to claim 6, wherein the base is a part of the substrate.
  8. 　前記基板はガラス基板であり、前記基部はスピンオンガラスにより形成されていることを特徴とする請求項６に記載のＴＦＴ基板。 The TFT substrate according to claim 6, wherein the substrate is a glass substrate, and the base is formed of spin-on glass.
  9. 　請求項４から８までのいずれか一つのＴＦＴ基板を有する表示パネルを備えることを特徴とする表示装置。 A display device comprising a display panel having any one TFT substrate according to claim 4.
  10. 　基板上に金属薄膜を形成し、
    　該金属薄膜上にレジストを塗布し、
    　半透過部を有するフォトマスクを用いて前記レジストに露光し、
    　前記レジストを現像した後、前記金属薄膜をエッチングしてゲートを形成し、
    　該ゲートを部分的にエッチングして、一方向に延びる凸部又は凹部を前記ゲートに形成し、
    　該ゲートが形成された基板上に絶縁膜及び半導体層を順に形成し、
    　該半導体層上に金属薄膜を形成し、該金属薄膜をエッチングして、前記半導体層のうち前記凸部又は凹部上に形成された部分を挟んで前記一方向に対向するソース及びドレインを形成する
    　ことを特徴とするＴＦＴ基板の製造方法。     A metal thin film is formed on the substrate,
    Applying a resist on the metal thin film,
    Exposing the resist using a photomask having a semi-transmissive portion;
    After developing the resist, the metal thin film is etched to form a gate,
    The gate is partially etched to form a protrusion or recess extending in one direction in the gate,
    An insulating film and a semiconductor layer are sequentially formed on the substrate on which the gate is formed,
    A metal thin film is formed on the semiconductor layer, and the metal thin film is etched to form a source and a drain facing in one direction across a portion of the semiconductor layer formed on the convex portion or the concave portion. A manufacturing method of a TFT substrate characterized by the above.
  11. 　基板をエッチングして一方向に延びる凸状又は凹状のパターンを形成し、
    　該パターンが形成された前記基板上に金属薄膜を形成し、
    　該金属薄膜をエッチングして前記パターンの上にゲートを形成し、
    　該ゲートが形成された基板上に絶縁膜及び半導体層を順に形成し、
    　該半導体層上に金属薄膜を形成し、該金属薄膜をエッチングして、前記半導体層のうち前記パターン上に形成された部分を挟んで前記一方向に対向するソース及びドレインを形成する
    　ことを特徴とするＴＦＴ基板の製造方法。     Etching the substrate to form a convex or concave pattern extending in one direction,
    Forming a metal thin film on the substrate on which the pattern is formed;
    Etching the metal thin film to form a gate on the pattern,
    An insulating film and a semiconductor layer are sequentially formed on the substrate on which the gate is formed,
    A metal thin film is formed on the semiconductor layer, and the metal thin film is etched to form a source and a drain facing in one direction across a portion of the semiconductor layer formed on the pattern. A method for manufacturing a TFT substrate.
  12. 　ガラス基板上にスピンオンガラス層を形成し、
    　該スピンオンガラス層をエッチングして一方向に延びる凸状又は凹状のパターンを形成し、
    　該パターンが形成された前記基板上に金属薄膜を形成し、
    　該金属薄膜をエッチングして前記パターンの上にゲートを形成し、
    　前記ゲートが形成された基板上に絶縁膜及び半導体層を順に形成し、
    　該半導体層上に金属薄膜を形成し、該金属薄膜をエッチングして、前記半導体層のうち前記パターン上に形成された部分を挟んで前記一方向に対向するソース及びドレインを形成する
    　ことを特徴とするＴＦＴ基板の製造方法。     Forming a spin-on glass layer on a glass substrate;
    Etching the spin-on glass layer to form a convex or concave pattern extending in one direction,
    Forming a metal thin film on the substrate on which the pattern is formed;
    Etching the metal thin film to form a gate on the pattern,
    An insulating film and a semiconductor layer are sequentially formed on the substrate on which the gate is formed,
    A metal thin film is formed on the semiconductor layer, and the metal thin film is etched to form a source and a drain facing in one direction across a portion of the semiconductor layer formed on the pattern. A method for manufacturing a TFT substrate.
  13. 　前記スピンオンガラス層は感光性を有することを特徴とする請求項１２に記載のＴＦＴ基板の製造方法。 The method for manufacturing a TFT substrate according to claim 12, wherein the spin-on glass layer has photosensitivity.
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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02140980A (en) * 1988-11-22 1990-05-30 Fuji Xerox Co Ltd Thin film transistor
JPH11354796A (en) * 1998-06-09 1999-12-24 Nec Corp Thin-film transistor
JP2005150328A (en) * 2003-11-14 2005-06-09 Canon Inc Field effect transistor and method of manufacturing the field effect transistor
JP2006245371A (en) * 2005-03-04 2006-09-14 Toppan Printing Co Ltd Thin film transistor and its manufacturing method
JP2006339265A (en) * 2005-05-31 2006-12-14 Sony Corp Field effect transistor
JP2007194297A (en) * 2006-01-17 2007-08-02 Seiko Epson Corp Semiconductor device, method of manufacturing the same and electronic equipment

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02140980A (en) * 1988-11-22 1990-05-30 Fuji Xerox Co Ltd Thin film transistor
JPH11354796A (en) * 1998-06-09 1999-12-24 Nec Corp Thin-film transistor
JP2005150328A (en) * 2003-11-14 2005-06-09 Canon Inc Field effect transistor and method of manufacturing the field effect transistor
JP2006245371A (en) * 2005-03-04 2006-09-14 Toppan Printing Co Ltd Thin film transistor and its manufacturing method
JP2006339265A (en) * 2005-05-31 2006-12-14 Sony Corp Field effect transistor
JP2007194297A (en) * 2006-01-17 2007-08-02 Seiko Epson Corp Semiconductor device, method of manufacturing the same and electronic equipment

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