JP4586345B2 - Field effect transistor - Google Patents

Description

  The present invention relates to a field effect transistor, and more particularly to a so-called organic field effect transistor in which a channel formation region is composed of an organic semiconductor layer.

  When manufacturing a semiconductor device from a conventional silicon semiconductor substrate or the like, a photolithography technique and various thin film forming techniques are used. However, these production techniques are complicated, require a long time for manufacturing the semiconductor device, and are a great obstacle to reducing the manufacturing cost of the semiconductor device. Further, the conventional semiconductor device is so-called bulk, and it is difficult to apply it to a field where flexibility and flexibility are required. Furthermore, as symbolized by Moore's Law, the limits of speeding up (accumulation) are becoming visible.

  Research and development of an electronic element that replaces a semiconductor device based on such a conventional silicon semiconductor substrate, such as a field effect transistor (FET), using an electroconductive polymer material has been eagerly advanced. In addition, a new field of inexpensive plastic electronics is being developed.

  So-called organic field effect transistors in which a channel formation region is composed of an organic semiconductor layer are well known from, for example, Japanese Patent Laid-Open Nos. 10-270712 and 2000-269515.

JP 10-270712 A JP 2000-269515 A Special table 2002-522907

  By the way, in such an organic field effect transistor, the edge of one source / drain electrode and the edge of the other source / drain electrode opposite to the one source / drain electrode are parallel to each other. It is composed of straight lines. In addition, many organic semiconductor crystals constituting the channel formation region exhibit electrical anisotropy. Then, when a channel formation region composed of an organic semiconductor crystal layer is formed by applying and drying an organic semiconductor material, for example, in some cases, many of the crystal axes having high electrical conductivity of the organic semiconductor crystal are In some cases, the channel formation region formed of the organic semiconductor crystal layer exhibits only low electrical conductivity as a whole because it is parallel to the edge of the drain electrode.

  JP-T-2002-522907 discloses a thin film transistor in which a source electrode and a drain electrode each have a spiral extension, and a channel formation region of the thin film transistor is made of amorphous silicon. JP-T-2002-522907 does not refer to any organic field effect transistor, nor does it refer to any problems inherent to a field effect transistor having a channel formation region composed of an organic semiconductor layer having electrical anisotropy. Not.

  Accordingly, an object of the present invention is to provide a field effect transistor having a structure in which a channel formation region formed of an organic semiconductor layer having electrical anisotropy can exhibit high electrical conductivity.

In order to achieve the above object, a field effect transistor of the present invention includes a gate electrode, a source / drain electrode, and a channel formation region provided between the source / drain electrodes.
The channel formation region is composed of an organic semiconductor layer having electrical anisotropy,
At least the edge of the other source / drain electrode facing the edge of one of the source / drain electrodes is not a straight line.

  In the field effect transistor of the present invention, the edge of one source / drain electrode may be linear, but the edge of one source / drain electrode is preferably not straight. In this case, the distance from the edge of one source / drain electrode to the edge of the other source / drain electrode is invariable (equal distance), that is, broadly, the edge of one source / drain electrode. More preferably, the portion and the edge of the other source / drain electrode are parallel. Specifically, it is more preferable that the distance from any point on the edge of one source / drain electrode to the point where the normal passing through this point intersects the other source / drain electrode is equal. It is desirable that the maximum value of the angle formed by the direction in which the source / drain electrodes extend and the normal line is as large as possible. For example, the maximum value may be ± 80 degrees. Furthermore, the trace drawn by the edge of one source / drain electrode and the edge of the other source / drain electrode may be essentially an arbitrary curve, but the edge of one source / drain electrode And a locus drawn by at least one of the edges of the other source / drain electrode is, for example, a part of a circle; a part of a combination of parts of a circle; a part of an ellipse; a part of an ellipse; Combined trajectory; part of a hyperbola; a part of a hyperbola, a combined trajectory; a part of a curve expressed by a polynomial of quadratic or higher; a part of a curve expressed by a polynomial of quadratic or higher; Combined trajectory; “S” curve; part of sine curve or cosine curve; part of circle, part of ellipse, part of hyperbola, part of curve expressed by higher order polynomial, sine curve Or you can combine any part of the cosine curve It is preferred that the trajectory that was. Alternatively, a combination of three or more line segments is preferable. When combining three or more line segments, specifically, for example, regular hexagonal three sides, regular heptagonal three sides, regular octagonal three sides or four sides, regular octagonal three sides or four sides The three sides, four sides or five sides of a regular decagon can be exemplified. Moreover, the part which a line segment and a line segment join may be roundish.

  The following four types of structures can be illustrated as specific structures of the field effect transistor of the present invention.

That is, the field effect transistor having the first structure is
(A) a gate electrode formed on the substrate;
(B) a gate insulating film formed on the gate electrode;
(C) source / drain electrodes formed on the gate insulating film, and
(D) a channel forming region formed of an organic semiconductor layer having electrical anisotropy formed between the source / drain electrodes and on the gate insulating film;
It has.

The field effect transistor having the second structure is
(A) a gate electrode formed on the substrate;
(B) a gate insulating film formed on the gate electrode;
(C) a channel formation region formed of an organic semiconductor layer having electrical anisotropy formed on the gate insulating film, and
(D) source / drain electrodes formed on the organic semiconductor layer;
It has.

Furthermore, the field effect transistor having the third structure is:
(A) a channel forming region formed of an organic semiconductor layer having electrical anisotropy formed on a substrate;
(B) source / drain electrodes formed on the organic semiconductor layer,
(C) a gate insulating film formed on the source / drain electrodes and the organic semiconductor layer, and
(D) a gate electrode formed on the gate insulating film,
It has.

The field effect transistor having the fourth structure is
(A) Source / drain electrodes formed on the substrate,
(B) a channel forming region comprising an organic semiconductor layer having electrical anisotropy formed on the source / drain electrodes and the substrate,
(C) a gate insulating film formed on the organic semiconductor layer, and
(D) a gate electrode formed on the gate insulating film,
It has.

  In the field effect transistor of the present invention, pentacene, copper phthalocyanine (CuPc), and tetrathiafulvalene-tetracyanoquinodimethane (TTF-TCNQ) are exemplified as materials constituting the organic semiconductor layer having electrical anisotropy. be able to.

Here, the electrical anisotropy is a ratio between the largest electrical conductivity σ _MAX and the smallest electrical conductivity σ _MIN among the electrical conductivities in the a-axis, b-axis, and c-axis of the organic crystal structure ( It means that the value of (σ _MAX / σ _MIN ) is 1.25 or more. The semiconductor layer refers to a layer having a volume resistivity on the order of 10 ⁻⁴ Ω · m to 10 ¹² Ω · m .

  As a method for forming the organic semiconductor layer, although depending on the material constituting the organic semiconductor layer, a physical vapor deposition method (PVD method) exemplified by a vacuum deposition method or a sputtering method; various chemical vapor deposition methods ( CVD method); spin coating method; printing method such as screen printing method and inkjet printing method; air doctor coater method, blade coater method, rod coater method, knife coater method, squeeze coater method, reverse roll coater method, transfer roll coater method, Any one of various coating methods such as a gravure coater method, a kiss coater method, a cast coater method, a spray coater method, a slit orifice coater method, a calendar coater method, and an immersion method; and a spray method can be used.

  In the field effect transistor of the present invention, platinum (Pt), gold (Au), palladium (Pd), chromium (Cr), nickel (Ni), aluminum are used as materials constituting the gate electrode and the source / drain electrode. (Al), silver (Ag), tantalum (Ta), tungsten (W), titanium (Ti), copper (Cu), indium (In), tin (Sn) and other metals, or including these metal elements An alloy, conductive particles made of these metals, conductive particles of an alloy containing these metals can be given, and a layered structure of layers containing these elements can also be used. Furthermore, an organic material such as poly (3,4-ethylenedioxythiophene) / polystyrene sulfonic acid [PEDOT / PSS] can also be used as a material constituting the gate electrode and the source / drain electrode. As a method of forming the gate electrode, source / drain electrode, and wiring, depending on the material constituting these electrodes, a combination of PVD method and etching technology exemplified by vacuum deposition method and sputtering method; Combination of etching technology; Combination of spin coating method and etching technology; Printing method such as screen printing method and inkjet printing method; Combination of various coating methods and etching technology described above; Lift-off method; Shadow mask method; A combination with an etching technique can be mentioned.

As materials constituting the gate insulating film, not only inorganic insulating materials exemplified by SiO ₂ , SiN, spin-on-glass (SOG), metal oxide high dielectric insulating film, but also polymethyl methacrylate (PMMA), Organic insulating materials exemplified by polyvinyl phenol (PVP) and polyvinyl alcohol (PVA) can be mentioned, and combinations thereof can also be used. As a method for forming the gate insulating film, PVD method exemplified by vacuum deposition method and sputtering method; various CVD methods; spin coating method; printing method such as screen printing method and inkjet printing method; various coating methods described above; immersion method; Any of a casting method and a spray method can be mentioned. In some cases, the surface of the gate electrode can be formed by oxidation or nitridation. As a method for oxidizing the surface of the gate electrode, although depending on the material constituting the gate electrode, an oxidation method using O ₂ plasma and an anodic oxidation method can be exemplified. Further, as a method of nitriding the surface of the gate electrode, although it depends on the material constituting the gate electrode, a nitriding method using N ₂ plasma can be exemplified. Alternatively, for example, for an Au electrode, it is immersed by an insulating molecule having a functional group that can form a chemical bond with the gate electrode, such as a linear hydrocarbon modified at one end with a mercapto group. An insulating film can be formed on the surface of the gate electrode by coating the surface of the gate electrode in a self-organized manner by a method such as a method.

  Examples of the substrate include various glass substrates, various glass substrates having an insulating layer formed on the surface, a quartz substrate, a quartz substrate having an insulating layer formed on the surface, and a silicon substrate having an insulating layer formed on the surface. it can. Furthermore, examples of the substrate include a plastic film, a plastic sheet, and a plastic substrate made of a polymer material exemplified by polyethersulfone (PES), polyimide, polycarbonate, and polyethylene terephthalate (PET). If a substrate made of such a flexible polymer material is used, for example, a field effect transistor can be incorporated or integrated into a display device or electronic device having a curved shape.

  In the field effect transistor of the present invention, at least the edge of the other source / drain electrode facing the edge of one of the source / drain electrodes is not a straight line. Therefore, when the channel forming region is formed from the organic semiconductor layer having electrical anisotropy, the direction (for example, the crystal axis) of the material constituting the organic semiconductor layer having the high electrical conductivity is the edge of the source / drain electrode. Therefore, it is possible to reliably avoid the phenomenon that the channel formation region exhibits only low electrical conductivity as a whole, and an optimal conduction path (current path) can be obtained. As a result, the operation of the field effect transistor can be stabilized, the mobility can be improved, and the characteristics of the field effect transistor can be improved.

  In addition, the formation of the organic semiconductor layer usually does not require a high temperature, and in some cases, the organic semiconductor layer may be formed based on a method not using a vacuum technique exemplified by a spin coating method, a printing method, and a spray method. it can. In this case, a field effect transistor can be produced at low cost on a flexible substrate such as a plastic film, a plastic sheet, or a plastic substrate. For example, a display device having a curved shape In addition, it is possible to incorporate or integrate field effect transistors in electronic devices.

  Hereinafter, the present invention will be described based on examples with reference to the drawings. However, the structure of the conventional field effect transistor is not changed at all, and the structure is slightly changed, so that the channel formation region has a low electric power as a whole. It is possible to realize a so-called organic field effect transistor that can surely avoid the occurrence of a phenomenon that exhibits only conductivity.

  Example 1 relates to a field effect transistor (hereinafter abbreviated as FET) of the present invention. FIG. 3A shows a schematic partial cross-sectional view when the FET of Example 1 is cut along a virtual vertical plane perpendicular to the extending direction of the gate electrode, and the planar shape of the gate electrode and the source / drain electrode is shown in FIG. A schematic diagram is shown in FIG. Note that the gate electrode extends in the vertical direction of FIG.

  The FET of Example 1 is a thin film transistor (TFT) including a gate electrode 12, a source / drain electrode 14, and a channel formation region 16 provided between the source / drain electrodes 14. The channel formation region 16 is composed of an organic semiconductor layer 15 having electrical anisotropy, and at least the edge portion 14b of the other source / drain electrode 14B facing the edge portion 14a of the one source / drain electrode 14A is It is not a straight line. Furthermore, the edge portion 14a of one of the source / drain electrodes 14A is not a straight line. Here, the distance from the edge portion 14a of one source / drain electrode 14A to the edge portion 14b of the other source / drain electrode 14B is invariable (equal distance). The locus drawn by the edge 14a of 14A and the edge 14b of the other source / drain electrode 14B is a part of a circle.

The FET of Example 1 has the first structure. That is, the FET of Example 1 is a so-called bottom gate type and bottom contact type TFT,
(A) a gate electrode 12 formed on the substrate 11;
(B) a gate insulating film 13 formed on the gate electrode 12;
(C) a source / drain electrode 14 formed on the gate insulating film 13, and
(D) a channel forming region 16 formed of an organic semiconductor layer 15 having electrical anisotropy formed between the source / drain electrodes 14 and on the gate insulating film 13;
It has.

In Example 1, the organic semiconductor layer 15 was made of pentacene. The electrical anisotropy of the organic semiconductor layer 15 is as follows.
Electrical conductivity in the a-axis = 5 × 10 ⁸ Ω · cm
Electrical conductivity at b-axis = 2.5 × 10 ⁶ Ω · cm
c-axis electrical conductivity = 3 × 10 ¹⁰ Ω · cm

Moreover, the support body 10 was comprised from the silicon substrate, and the base | substrate 11 was comprised from the polyether sulfone (PES). Further, the gate electrode 12 and the source / drain electrode 14 are composed of two layers of gold (Au) layer / Ti layer, and the gate insulating film 13 is composed of SiO ₂ .

  Hereinafter, with reference to FIGS. 1A to 1D, FIGS. 2A to 2C, and FIG. An outline of a method for manufacturing an FET will be described.

[Step-100]
First, the gate electrode 12 is formed on the substrate 11. Specifically, a pattern for forming a gate electrode is formed on a base 11 made of polyethersulfone (PES) bonded to a support 10 made of a silicon substrate based on a resist layer 31 ((A) in FIG. 1). reference).

  Next, a Ti layer as an adhesion layer and an Au layer / Ti layer as a gate electrode 12 are formed on the substrate 11 and the resist layer 31 by a vacuum deposition method (see FIG. 1B). In the drawings, the adhesion layer is not shown. When vapor deposition is performed, the support 10 to which the substrate 11 is bonded is placed on a support holder that can adjust the temperature, and an increase in the temperature of the support during vapor deposition can be suppressed. 11 can be formed while minimizing the deformation of 11.

  Thereafter, the resist layer 31 is removed by a lift-off method, whereby the gate electrode 12 can be obtained (see FIG. 1C).

[Step-110]
Next, the gate insulating film 13 is formed on the base 11 including the gate electrode 12. Specifically, the gate insulating film 13 made of SiO ₂ is formed on the gate electrode 12 and the substrate 11 based on the sputtering method. When forming the gate insulating film 13, by covering a part of the gate electrode 12 with a hard mask, a gate electrode extraction portion (not shown) can be formed without a photolithography process. Further, when the gate insulating film 13 is formed, the support 10 to which the substrate 11 is bonded is placed on a support holder whose temperature can be adjusted, so that the temperature of the support during film formation of SiO ₂ can be reduced. Since the increase can be suppressed, the film formation with the deformation of the substrate 11 minimized can be performed.

[Step-120]
Next, source / drain electrodes 14 are formed on the gate insulating film 13. Specifically, a pattern for forming source / drain electrodes is formed on the entire surface based on the resist layer 32 (see FIG. 1D).

  Next, a Ti layer as an adhesion layer and an Au layer / Ti layer as a source / drain electrode 14 are formed on the gate insulating film 13 and the resist layer 32 by a vacuum deposition method (see FIG. 2A). In the drawings, the adhesion layer is not shown. When vapor deposition is performed, the support 10 to which the substrate 11 is bonded is placed on a support holder that can adjust the temperature, and an increase in the temperature of the support during vapor deposition can be suppressed. 11 can be formed while minimizing the deformation of 11.

  Thereafter, the resist layer 32 is removed by a lift-off method, whereby the source / drain electrode 14 can be obtained (see FIG. 2B).

[Step-130]
Next, the organic semiconductor layer 15 is formed over the gate insulating film 13 (see FIG. 2C). Specifically, an organic semiconductor layer 15 made of pentacene is formed on the source / drain electrode 14 and the gate insulating film 13 based on the vacuum deposition method illustrated in Table 1 below. When the organic semiconductor layer 15 is formed, the organic semiconductor layer 15 can be formed without a photolithography process by covering part of the gate insulating film 13 and the source / drain electrodes 14 with a hard mask.

[Table 1]
Support temperature: 60 ° C
Deposition rate: 3 nm / min Pressure: 5 × 10 ⁻⁴ Pa

[Step-140]
Next, after an insulating layer 20 made of SiO ₂ is formed on the entire surface, an opening is formed in the portion of the insulating layer 20 above the gate electrode 12 and the source / drain electrode 14, and the insulating layer 20 including the inside of these openings is formed. A wiring material layer is formed on this, and this wiring material layer is patterned to form a wiring (not shown) connected to the gate electrode 12 and a wiring 21 connected to the source / drain electrode 14. Yes (Figure 3). Thus, the FET of Example 1 can be obtained.

  4A to 4C schematically show a modification of the edge of the source / drain electrode in the FET of the first embodiment. The modification is made from the edge 14a of one source / drain electrode 14A to the other source. / The distance to the edge 14b of the drain electrode 14B is unchanged (equal distance). That is, the edge 14a of one source / drain electrode 14A and the edge 14b of the other source / drain electrode 14B are parallel. Specifically, in the example shown in FIG. 4A, the locus drawn by the edge 14b of the other source / drain electrode 14B is a part of an ellipse. In the example shown in FIG. 4B, the locus drawn by the edge 14a of one source / drain electrode 14A and the edge 14b of the other source / drain electrode 14B is a combination of three or more line segments ( Specifically, they are three sides of a regular octagon. Furthermore, in the example shown in FIG. 4C, the locus drawn by the edge 14a of one source / drain electrode 14A and the edge 14b of the other source / drain electrode 14B is a combination of three or more line segments. (Specifically, three sides of a regular octagon), but the line segment and the part where the line segment joins are rounded. The trajectories drawn by the edge portions 14a and 14b of the source / drain electrodes 14A and 14B are not limited to the examples shown in FIGS. 3B and 4A to 4C. Moreover, the example of the locus | trajectory which the edge parts 14a and 14b of such source / drain electrodes 14A and 14B draw can be applied also to Example 2, Example 3, and Example 4 demonstrated below.

The second embodiment is a modification of the first embodiment. The FET of Example 2 has the second structure. That is, the FET of Example 2 is a so-called bottom gate type as shown in FIG. 5 which is a schematic partial sectional view when the FET is cut along a virtual vertical plane perpendicular to the extending direction of the gate electrode. And a top contact type TFT,
(A) a gate electrode 12 formed on the substrate 11;
(B) a gate insulating film 13 formed on the gate electrode 12;
(C) a channel forming region 16 made of an organic semiconductor layer 15 having electrical anisotropy formed on the gate insulating film 13, and
(D) source / drain electrodes 14 formed on the organic semiconductor layer 15;
It has.

  In the FET of the second embodiment, the arrangement state of the source / drain electrodes 14 and the organic semiconductor layer 15 in the vertical direction is opposite to that of the FET of the first embodiment. Can be the same. Therefore, detailed description of the FET of Example 2 is omitted. Further, the FET of Example 2 can be obtained by reversing the order of [Step-120] and [Step-130] in the FET manufacturing method described in Example 1, so that the FET of Example 2 can be obtained. A detailed description of the FET manufacturing method is omitted.

The third embodiment is also a modification of the first embodiment. The FET of Example 3 has the third structure. That is, the FET of Example 3 is a so-called top gate as shown in FIG. 6A, which is a schematic partial cross-sectional view when the FET is cut along a virtual vertical plane perpendicular to the extending direction of the gate electrode. Type and top contact type TFT,
(A) a channel forming region 16 formed of an organic semiconductor layer 15 having electrical anisotropy formed on the substrate 11;
(B) source / drain electrodes 14 formed on the organic semiconductor layer 15;
(C) the gate insulating film 13 formed on the source / drain electrode 14 and the organic semiconductor layer 15, and
(D) a gate electrode 12 formed on the gate insulating film 13,
It has.

  The FET of the third embodiment is thus different in structure from the FET of the first embodiment, but the materials constituting each component can be the same as the FET of the first embodiment. Therefore, detailed description of the FET of Example 3 is omitted. The outline of the method for manufacturing the FET of Example 3 will be described below.

[Step-300]
First, the organic semiconductor layer 15 is formed on the substrate 11 in the same manner as in [Step-130] of Example 1.

[Step-310]
Next, the source / drain electrodes 14 are formed on the organic semiconductor layer 15 in the same manner as in [Step-120] of Example 1.

[Step-320]
Thereafter, the gate insulating film 13 is formed on the source / drain electrodes 14 and the organic semiconductor layer 15 in the same manner as in [Step-110] in Example 1.

[Step-330]
Next, the gate electrode 12 is formed on the gate insulating film 13 in the same manner as in [Step-100] in Example 1.

[Step-340]
Thereafter, the insulating layer 20 made of SiO ₂ is formed on the entire surface in the same manner as in [Step-140] of Example 1, and then an opening is formed in the insulating layer 20 above the gate electrode 12 and the source / drain electrode 14. , Forming a wiring material layer on the insulating layer 20 including the inside of these openings, and patterning the wiring material layer, thereby connecting a wiring (not shown) connected to the gate electrode 12 and a source / A wiring 21 connected to the drain electrode 14 is formed. Thus, the FET of Example 3 can be obtained.

The fourth embodiment is a modification of the third embodiment. The FET of Example 4 has the fourth structure. That is, the FET of Example 4 is a so-called top gate as shown in FIG. 6B, which is a schematic partial cross-sectional view when the FET is cut along a virtual vertical plane perpendicular to the extending direction of the gate electrode. Type and bottom contact type TFT,
(A) source / drain electrodes 14 formed on the substrate 11;
(B) a channel forming region 16 made of an organic semiconductor layer 15 having electrical anisotropy formed on the source / drain electrodes 14 and the substrate 11;
(C) the gate insulating film 13 formed on the organic semiconductor layer 15, and
(D) a gate electrode 12 formed on the gate insulating film 13,
It has.

  In the FET of the fourth embodiment, the vertical arrangement state of the source / drain electrodes 14 and the organic semiconductor layer 15 is opposite to that of the FET of the third embodiment. Can be the same. Therefore, detailed description of the FET of Example 4 is omitted. In addition, the FET of Example 4 can be obtained by reversing the order of [Step-300] and [Step-310] in the FET manufacturing method described in Example 3, so that the FET of Example 4 can be obtained. A detailed description of the FET manufacturing method is omitted.

  As mentioned above, although this invention was demonstrated based on the preferable Example, this invention is not limited to these Examples. The structure and manufacturing conditions of the field effect transistor are illustrative and can be changed as appropriate. When the FET of the present invention is applied to and used in display devices and various electronic devices, it may be a monolithic integrated circuit in which a large number of FETs are integrated on a substrate, or individualized by cutting each FET into discrete components. May be used.

1A to 1D are schematic partial cross-sectional views of a support and the like for explaining the method for manufacturing the field-effect transistor of Example 1. FIG. 2A to 2C are schematic partial cross-sectional views of a support and the like for explaining the method for manufacturing the field-effect transistor of Example 1 following FIG. 1D. . FIG. 3A is a schematic partial cross-sectional view of a support and the like for explaining the method of manufacturing the field effect transistor of Example 1 following FIG. (B) is a schematic diagram for explaining the planar shape of the gate electrode and the source / drain electrode. 4A to 4C are schematic views showing modifications of the edge of the source / drain electrode in the field effect transistor of the present invention. FIG. 5 is a schematic partial cross-sectional view of the field-effect transistor of Example 2. 6A and 6B are schematic partial cross-sectional views of the field effect transistors of Example 3 and Example 4. FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Support body, 11 ... Base | substrate, 12 ... Gate electrode, 13 ... Gate insulating film, 14, 14A, 14B ... Source / drain electrode, 14a, 14b ... Source / drain Edge of electrode, 15 ... organic semiconductor layer, 16 ... channel forming region, 20 ... insulating layer, 21 ... wiring, 31, 32 ... resist layer

Claims (1)

A field effect transistor comprising a gate electrode, a source / drain electrode, and a channel formation region provided between the source / drain electrodes,
The channel formation region is composed of an organic semiconductor layer having electrical anisotropy,
One end portion of the source / drain electrode is opposed to the other end portion of the source / drain electrodes,
Locus drawn by the other tip portion of one of the tip and the source / drain electrode of the source / drain electrodes, regular hexagon three sides, three sides of the regular heptagon, three sides of the octagonal or four sides, positive Nonagon 3 sides or 4 sides, 3 sides, 4 sides or 5 sides of a regular decagon,
One from any point of the tip portion, the distance to the point where the normal line passing through this point intersects the other of the other of the source / drain electrode is equal field effect transistor of the source / drain electrodes.

Images