JP5617214B2 - THIN FILM TRANSISTOR, MANUFACTURING METHOD THEREOF, AND IMAGE DISPLAY DEVICE - Google Patents
THIN FILM TRANSISTOR, MANUFACTURING METHOD THEREOF, AND IMAGE DISPLAY DEVICE Download PDFInfo
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- JP5617214B2 JP5617214B2 JP2009226506A JP2009226506A JP5617214B2 JP 5617214 B2 JP5617214 B2 JP 5617214B2 JP 2009226506 A JP2009226506 A JP 2009226506A JP 2009226506 A JP2009226506 A JP 2009226506A JP 5617214 B2 JP5617214 B2 JP 5617214B2
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
- C23C16/48—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating by irradiation, e.g. photolysis, radiolysis, particle radiation
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
- H05B33/00—Electroluminescent light sources
- H05B33/12—Light sources with substantially two-dimensional radiating surfaces
- H05B33/14—Light sources with substantially two-dimensional radiating surfaces characterised by the chemical or physical composition or the arrangement of the electroluminescent material, or by the simultaneous addition of the electroluminescent material in or onto the light source
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Chemical & Material Sciences (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Liquid Crystal (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Nonlinear Science (AREA)
- Formation Of Insulating Films (AREA)
- Chemical Vapour Deposition (AREA)
- Manufacturing & Machinery (AREA)
- Electroluminescent Light Sources (AREA)
- Thin Film Transistor (AREA)
- Crystallography & Structural Chemistry (AREA)
- Optics & Photonics (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- General Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Materials Engineering (AREA)
- Mechanical Engineering (AREA)
- Metallurgy (AREA)
- Organic Chemistry (AREA)
- Ceramic Engineering (AREA)
Description
本発明は、各種画像表示装置の駆動素子や各種論理回路の論理素子等に用いることができる薄膜トランジスタ及びその製造方法並びに画像表示装置に関するものである。 The present invention relates to a thin film transistor that can be used for a drive element of various image display devices, a logic element of various logic circuits, a manufacturing method thereof, and an image display device.
現在、一般的な平面薄型画像表示装置（Ｆｌａｔ Ｐａｎｅｌ Ｄｉｓｐｌａｙ；ＦＰＤ）としては、半導体に非晶質シリコンや多結晶シリコンを用いた電界効果型薄膜トランジスタにより駆動するアクティブマトリックスタイプのものが主流となっている。 At present, as a general flat panel display (FPD), an active matrix type driven by a field effect thin film transistor using amorphous silicon or polycrystalline silicon as a semiconductor is mainly used. Yes.
そして、上述の電界効果型薄膜トランジスタの半導体層を被覆し、外部環境から保護する層（保護層）としては無機絶縁層、例えば、酸化シリコン等が用いられている。 An inorganic insulating layer such as silicon oxide is used as a layer (protective layer) that covers the semiconductor layer of the above-described field-effect thin film transistor and protects it from the external environment.
上述の保護層は、一般に微細加工が可能なフォトリソグラフィー法を用いてパターニングされる（非特許文献１）。 The above-described protective layer is generally patterned using a photolithography method that allows fine processing (Non-Patent Document 1).
一方、フォトリソグラフィー法を用いたパターニング工程は、レジスト形成、プレベーク、フォトマスクを用いた露光、現像、エッチング、レジスト剥離、洗浄、乾燥を含む非常に複雑な工程であり、製造コストの低減と、歩留まりの向上を達成するためにはフォトリソグラフィー法を用いたパターニング工程を一工程でも削減することが求められている。 On the other hand, the patterning process using the photolithography method is a very complicated process including resist formation, pre-baking, exposure using a photomask, development, etching, resist stripping, washing, and drying, and the reduction of manufacturing cost, In order to achieve an improvement in yield, it is required to reduce the patterning process using a photolithography method even in one process.
本発明の目的は、製造コストを低減することができ、かつ、歩留まりの高い薄膜トランジスタを提供することにある。 An object of the present invention is to provide a thin film transistor which can reduce the manufacturing cost and has a high yield.
請求項１の発明に係る薄膜トランジスタの製造方法は、絶縁基板上の一部に形成されたゲート電極と、前記絶縁基板及び前記ゲート電極の上に形成されたゲート絶縁層と、前記ゲート絶縁層の上の一部に形成された半導体層と、前記半導体層が形成されていない前記ゲート絶縁層の上の一部および前記半導体層の上の一部に形成された保護層と、前記ゲート絶縁層の上の一部及び前記半導体層の上の一部にかけて形成され前記保護層から露出したソース電極及びドレイン電極と、を少なくとも具備する薄膜トランジスタの製造方法であって、前記絶縁基板上に、前記ゲート電極と、前記ゲート絶縁層と、前記半導体層と、前記ソース電極と前記ドレイン電極とを順に形成した後、前記ゲート絶縁層の上の全面に前記保護層となる膜を成膜する工程と、前記保護層となる膜をパターニングなしにエッチングし前記ソース電極と前記ドレイン電極の表面を露出させ前記保護層のパターンを形成する工程を具備し、前記保護層は真空紫外光ＣＶＤ法により形成されており、前記半導体層上の前記ソース電極及び前記ドレイン電極の膜厚は、前記半導体層と前記ゲート電極との膜厚の合計値よりも厚い、ことを特徴とする。
請求項２の発明に係る薄膜トランジスタの製造方法は、前記ソース電極と前記ドレイン電極を構成する材料における前記保護層をエッチングする時のエッチャントに対するエッチングレートは、前記保護層となる材料のエッチングレートよりも小さいことを特徴とする。
請求項３の発明に係る薄膜トランジスタの製造方法は、前記保護層は酸化シリコンを含む材料で形成されていることを特徴とする。
請求項４の発明に係る薄膜トランジスタの製造方法は、前記保護層を形成後に１００℃以上で熱処理を行うことを特徴とする。
請求項５の発明に係る薄膜トランジスタは、絶縁基板上の一部に形成されたゲート電極と、前記絶縁基板及び前記ゲート電極の上に形成されたゲート絶縁層と、前記ゲート絶縁層の上の一部に形成された半導体層と、前記半導体層が形成されていない前記ゲート絶縁層の上の一部および前記半導体層の上の一部に形成された保護層と、前記ゲート絶縁層の上の一部及び前記半導体層の上の一部にかけて形成され前記保護層から露出したソース電極及びドレイン電極と、を少なくとも具備する薄膜トランジスタであって、前記半導体層上の前記ソース電極及び前記ドレイン電極の膜厚は、前記半導体層と前記ゲート電極との膜厚の合計値よりも厚く、前記保護層は、前記絶縁基板上に、前記ゲート電極と、前記ゲート絶縁層と、前記半導体層と、前記ソース電極と前記ドレイン電極とを順に形成した後に、前記半導体層の前記ソース電極及び前記ドレイン電極が形成されていない領域と少なくとも前記ゲート絶縁膜の上の一部とに、真空紫外光ＣＶＤ法により形成され、前記ゲート絶縁膜の上の保護層の膜厚は、前記半導体層の膜厚と前記ゲート電極に対応する前記ゲート絶縁層の上の隆起高さとの合計値よりも大きく、かつ、前記ゲート絶縁膜の上の前記保護層の膜厚は、前記半導体層の膜厚と前記ソース電極及び前記ドレイン電極の膜厚と前記ゲート電極に対応する前記ゲート絶縁層の上の隆起高さとの合計値よりも小さくなり、前記半導体層の上の保護層の膜厚は、前記半導体層の上の前記ソース電極及び前記ドレイン電極の膜厚よりも小さくなるように形成されている、ことを特徴とする。
請求項６の発明に係る薄膜トランジスタは、前記保護層が酸化シリコンを含む材料で形成されていることを特徴する。
請求項７の発明に係る画像表示装置は、請求項５または６に記載の薄膜トランジスタのアレイと、前記薄膜トランジスタのアレイのソース電極又はドレイン電極に接続された画素電極と、前記画素電極上に配置された画像表示媒体と、を具備することを特徴とする。
請求項８の発明に係る画像表示装置は、前記画像表示媒体が電気泳動方式によるものであることを特徴とする。
Method for manufacturing a thin film transistor according to a first aspect of the invention, a gate electrode formed on a part of the insulating substrate, a gate insulating layer formed on the insulating substrate and the gate electrode, the gate insulating layer A semiconductor layer formed on a part of the semiconductor layer; a protective layer formed on a part of the gate insulating layer on which the semiconductor layer is not formed and a part of the semiconductor layer; and the gate insulating layer A thin film transistor including at least a source electrode and a drain electrode formed over a part of the semiconductor layer and a part of the semiconductor layer exposed from the protective layer , wherein the gate electrode is formed on the insulating substrate. and electrode, and the gate insulating layer, said semiconductor layer, after the said drain electrode and the source electrode are formed in this order, forming the protective layer and the film on the entire surface of the gate insulating layer And etching the film to be the protective layer without patterning to expose the surfaces of the source electrode and the drain electrode to form a pattern of the protective layer. The protective layer is formed by a vacuum ultraviolet light CVD method. The film thickness of the source electrode and the drain electrode on the semiconductor layer is greater than the total thickness of the semiconductor layer and the gate electrode.
In the method of manufacturing a thin film transistor according to the invention of claim 2, the etching rate for the etchant when the protective layer in the material constituting the source electrode and the drain electrode is etched is higher than the etching rate of the material to be the protective layer. It is small.
According to a third aspect of the present invention, there is provided a method for manufacturing a thin film transistor, wherein the protective layer is formed of a material containing silicon oxide.
According to a fourth aspect of the present invention, there is provided a method of manufacturing a thin film transistor, wherein heat treatment is performed at 100 ° C. or higher after the protective layer is formed.
Thin-film transistor according to the invention of claim 5 includes a gate electrode formed on a part of the insulating substrate, wherein a gate insulating layer formed on the insulating substrate and the gate electrode, one on the gate insulating layer a semiconductor layer formed on the part, and a protective layer in which the semiconductor layer is formed on a part of a portion over the gate insulating layer is not formed and the semiconductor layer, on top of the gate insulating layer some and a thin film transistor characterized by at least a source electrode and a drain electrode are exposed from the protective layer is formed over the portion on said semiconductor layer, film of the source electrode and the drain electrode on the semiconductor layer the thickness, the rather thick than the sum of the thicknesses of the semiconductor layer and the gate electrode, the protective layer is on the insulating substrate, and the gate electrode, the gate insulating layer, said semiconductor layer After forming the source electrode and the drain electrode in order, a vacuum ultraviolet light CVD method is applied to a region of the semiconductor layer where the source electrode and the drain electrode are not formed and at least a part on the gate insulating film. And the thickness of the protective layer on the gate insulating film is greater than the sum of the thickness of the semiconductor layer and the height of the protrusion on the gate insulating layer corresponding to the gate electrode, and The film thickness of the protective layer on the gate insulating film is the film thickness of the semiconductor layer, the film thickness of the source electrode and the drain electrode, and the raised height on the gate insulating layer corresponding to the gate electrode. smaller than the total value, the thickness of the protective layer over the semiconductor layer is formed to be smaller than the thickness of the source electrode and the drain electrode on the semiconductor layer, it And features.
The thin film transistor according to the invention of claim 6 is characterized in that the protective layer is made of a material containing silicon oxide.
An image display device according to a seventh aspect of the invention is disposed on the pixel electrode, the thin film transistor array according to the fifth or sixth aspect , a pixel electrode connected to a source electrode or a drain electrode of the thin film transistor array, and the pixel electrode. And an image display medium.
An image display device according to an invention of claim 8 is characterized in that the image display medium is of an electrophoretic type.
本発明によれば、保護層のパターンを、フォトリソグラフィー法によるレジストパターニングを行わなくとも、エッチングのみで簡易に形成することができるため、製造コストが低減され、歩留まりの高い薄膜トランジスタを提供することができる。 According to the present invention, since the pattern of the protective layer can be easily formed only by etching without performing resist patterning by a photolithography method, a manufacturing cost is reduced and a thin film transistor with a high yield can be provided. it can.
また、本発明によれば、真空紫外光ＣＶＤ法を用いて成膜した高い自己平坦化特性(埋め込み特性)を持つ膜を用いることで，製造コストが低減され、歩留まりの高い薄膜トランジスタアレイを提供することができる。真空紫外光ＣＶＤ法を用いて成膜した膜が高い自己平坦化性を持つのは，真空紫外光ＣＶＤ法においては気相中で光分解して発生したラジカル等の反応活性種が表面をマイグレーションしフローしながら堆積し薄膜が形成され、基板の材料や表面形状によらず膜が形成されるためである。 In addition, according to the present invention, a thin film transistor array having a high yield can be provided by reducing the manufacturing cost by using a film having a high self-flattening characteristic (embedding characteristic) formed by using a vacuum ultraviolet light CVD method. be able to. The film deposited using the vacuum ultraviolet light CVD method has high self-flattening property. In the vacuum ultraviolet light CVD method, reactive active species such as radicals generated by photolysis in the gas phase migrate the surface. This is because the thin film is formed by deposition while flowing, and the film is formed regardless of the material and surface shape of the substrate.
また、本発明によれば、絶縁基板上にボトムゲート-トップコンタクト型の薄膜トランジスタを形成し、保護層となる膜を真空紫外光ＣＶＤ法により埋め込み成膜し、その後エッチングによりソース電極及びドレイン電極を露出させることで、ソース電極及びドレイン電極の非パターン部に保護層のパターンを形成することができる。これに対し、保護層となる膜が埋め込み成膜ではなく、通常の熱ＣＶＤ法やプラズマＣＶＤ法等により形成される場合には、半導体層上とソース−ドレイン電極上に一様の膜厚で膜が成膜されるため、エッチングによりソース電極及びドレイン電極を露出させる時に、半導体層も露出してしまうため、半導体層上に保護層を形成することは不可能となる。 In addition, according to the present invention, a bottom gate-top contact type thin film transistor is formed on an insulating substrate, a film serving as a protective layer is embedded by vacuum ultraviolet light CVD, and then a source electrode and a drain electrode are formed by etching. By exposing, the pattern of a protective layer can be formed in the non-pattern part of a source electrode and a drain electrode. On the other hand, when the film serving as the protective layer is formed not by buried film formation but by ordinary thermal CVD method, plasma CVD method, etc., the film thickness is uniform on the semiconductor layer and the source-drain electrode. Since the film is formed, when the source electrode and the drain electrode are exposed by etching, the semiconductor layer is also exposed. Therefore, it is impossible to form a protective layer on the semiconductor layer.
また、本発明において、ソース・ドレイン電極を構成する材料において保護層をエッチング形成する時のエッチャントに対するエッチングレートを、前記保護層となる材料のエッチングレートよりも小さくした場合には、保護層をエッチング形成する時にソース電極及びドレイン電極が消失してしまうことを防ぐことができる。 In the present invention, when the etching rate for the etchant when the protective layer is formed by etching in the material constituting the source / drain electrode is lower than the etching rate of the material to be the protective layer, the protective layer is etched. It is possible to prevent the source electrode and the drain electrode from being lost during formation.
また、本発明において、上記のパターニング方法を実施するためには、前記ソース電極及びドレイン電極の膜厚を、前記半導体層と前記ゲート電極の膜厚の合計値よりも厚くした場合には、上述のエッチング方法により半導体層を露出させることなくソース電極及びドレイン電極の全面を露出させることができるため、配線や画素電極との接続が容易である。 In the present invention, in order to carry out the patterning method described above, when the film thickness of the source electrode and the drain electrode is larger than the total value of the film thickness of the semiconductor layer and the gate electrode, Since the entire surface of the source electrode and the drain electrode can be exposed without exposing the semiconductor layer by this etching method, the connection with the wiring and the pixel electrode is easy.
また、本発明において、保護層を酸化シリコンを含む材料で形成する場合には、優れた絶縁特性を持つ薄膜トランジスタを提供することができる。 In the present invention, when the protective layer is formed using a material containing silicon oxide, a thin film transistor having excellent insulating characteristics can be provided.
また、本発明において、真空紫外光ＣＶＤ法で形成した酸化シリコン膜が１００℃以上で熱処理を行なわれる場合には、より優れた絶縁性を実現することが可能となる。真空紫外光ＣＶＤ法で酸化シリコンを室温形成する場合、有機シリコン化合物のシロキサン等を材料として形成される。その時材料ガスが完全に分解するのではなく、一部は分解されて生成された反応活性種がマイグレーションし、フローしながら膜を形成するため、材料ガスに含まれるＳｉ−ＣＨ３等も膜中に多く含まれる。このため、本発明で用いる保護層は膜中に未分解原料を含むから、１００℃以上で熱処理を行うことにより、未分解原料量を減らし、より優れた絶縁性を実現することが可能となる。 In the present invention, when the silicon oxide film formed by the vacuum ultraviolet light CVD method is subjected to heat treatment at 100 ° C. or higher, it is possible to realize better insulation. When silicon oxide is formed at room temperature by a vacuum ultraviolet light CVD method, it is formed using siloxane or the like of an organic silicon compound as a material. At that time, the material gas is not completely decomposed, but a part of the reactive active species generated by decomposition is migrated to form a film while flowing. Therefore, Si—CH 3 and the like contained in the material gas are also contained in the film. Many are included. For this reason, since the protective layer used in the present invention contains undecomposed raw materials in the film, it is possible to reduce the amount of undecomposed raw materials and realize better insulation by performing heat treatment at 100 ° C. or higher. .
以下、本発明の実施の形態について、図面を参照して詳細に説明する。実施の形態及びに実施例おいて、同一の構成要素には同一符号を付け、重複する説明は省略する。 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the embodiments and examples, the same components are denoted by the same reference numerals, and redundant description is omitted.
（実施の形態１）
図１は、本発明の実施の形態１に係る薄膜トランジスタを示す模式図である。本発明の実施の形態１に係る薄膜トランジスタは、絶縁基板１０の上に、ゲート電極１１、ゲート絶縁層１２、半導体層１３、ソース電極１４、ドレイン電極１５、保護層１６が順次形成されているボトムゲート−トップコンタクト型のものである。
(Embodiment 1)
FIG. 1 is a schematic diagram showing a thin film transistor according to Embodiment 1 of the present invention. The thin film transistor according to the first embodiment of the present invention has a bottom in which a gate electrode 11, a gate insulating layer 12, a semiconductor layer 13, a source electrode 14, a drain electrode 15, and a protective layer 16 are sequentially formed on an insulating substrate 10. Gate-top contact type.
ゲート電極１１は、絶縁基板１０の上の一部に形成されている。ゲート絶縁層１２は、絶縁基板１０及びゲート電極１１の上に形成されている。保護層１６は、ゲート絶縁層１２の上の一部に形成されている。半導体層１３は、保護層１６が形成されていないゲート絶縁層１２の上の一部に形成されている。ソース電極１４及びドレイン電極１５は、ゲート絶縁層１２及び半導体層１３の上に形成されている。 The gate electrode 11 is formed on a part of the insulating substrate 10. The gate insulating layer 12 is formed on the insulating substrate 10 and the gate electrode 11. The protective layer 16 is formed on a part of the gate insulating layer 12. The semiconductor layer 13 is formed on a part of the gate insulating layer 12 where the protective layer 16 is not formed. The source electrode 14 and the drain electrode 15 are formed on the gate insulating layer 12 and the semiconductor layer 13.
本発明の実施の形態１に係る薄膜トランジスタは、ゲート絶縁層１２の上の全面に保護層１６となる膜を成膜する工程と、保護層１６となる膜をパターニングなしにエッチングしソース電極１４とドレイン電極１５の表面を露出させ保護層１６のパターンを形成する工程と、を具備している。 The thin film transistor according to Embodiment 1 of the present invention includes a step of forming a film to be the protective layer 16 on the entire surface of the gate insulating layer 12, and etching the film to be the protective layer 16 without patterning, And exposing the surface of the drain electrode 15 to form a pattern of the protective layer 16.
絶縁基板１０は、例えば、ガラスやプラスチック基板で形成される。このプラスチック基板としては、例えば、ポリメチルメタクリレート、ポリアクリレート、ポリカーボネート、ポリスチレン、ポリエチレンサルファイド、ポリエーテルスルホン（ＰＥＳ）、ポリオレフィン、ポリエチレンテレフタレート、ポリエチレンナフタレート（ＰＥＮ）、シクロオレフィンポリマー、ポリエーテルサルフェン、トリアセチルセルロース、ポリビニルフルオライドフィルム、エチレン-テトラフルオロエチレン共重合樹脂、耐候性ポリエチレンテレフタレート、耐候性ポリプロピレン、ガラス繊維強化アクリル樹脂フィルム、ガラス繊維強化ポリカーボネート、透明性ポリイミド、フッ素系樹脂又は環状ポリオレフィン系樹脂等が使用される。これらの基板は単独で使用することもでき、二種以上を積層した複合の基板を使用することもできる。また、絶縁基板１０は、ガラスやプラスチック基板上に樹脂層、例えば、カラーフィルタが形成された基板を使用することもできる。 The insulating substrate 10 is made of, for example, glass or a plastic substrate. Examples of the plastic substrate include polymethyl methacrylate, polyacrylate, polycarbonate, polystyrene, polyethylene sulfide, polyethersulfone (PES), polyolefin, polyethylene terephthalate, polyethylene naphthalate (PEN), cycloolefin polymer, polyethersulfene, Triacetyl cellulose, polyvinyl fluoride film, ethylene-tetrafluoroethylene copolymer resin, weather resistant polyethylene terephthalate, weather resistant polypropylene, glass fiber reinforced acrylic resin film, glass fiber reinforced polycarbonate, transparent polyimide, fluororesin or cyclic polyolefin Resin or the like is used. These substrates can be used alone, or a composite substrate in which two or more kinds are laminated can be used. The insulating substrate 10 may be a substrate in which a resin layer such as a color filter is formed on a glass or plastic substrate.
ソース電極１４とドレイン電極１５を構成する材料における保護層１６となる膜をエッチングする時のエッチャントに対するエッチングレートは、保護層１６となる材料のエッチングレートよりも小さいことが必須である。保護層１６となる膜のエッチングにおいて、ソース電極１４とドレイン電極１５を構成する材料のエッチングレートが大きいと保護層１６をエッチングする時にソース電極１４及びドレイン電極１５が消失してしまう可能性があるが、上記のようなエッチングレートであれば、保護層１６をエッチング形成する時にソース電極１４及びドレイン電極１５が消失してしまうことを防ぐことができる。 It is essential that the etching rate for the etchant when etching the film to be the protective layer 16 in the material constituting the source electrode 14 and the drain electrode 15 is smaller than the etching rate of the material to be the protective layer 16. In etching the film to be the protective layer 16, if the etching rate of the material constituting the source electrode 14 and the drain electrode 15 is large, the source electrode 14 and the drain electrode 15 may disappear when the protective layer 16 is etched. However, when the etching rate is as described above, the source electrode 14 and the drain electrode 15 can be prevented from disappearing when the protective layer 16 is formed by etching.
ゲート電極１１、ソース電極１４及びドレイン電極１５の材料として、Ａｕ、Ａｇ、Ｃｕ、Ｃｒ、Ａｌ、Ｍｇ、Ｌｉなどの低抵抗金属材料が好適である。また、ゲート電極１１、ソース電極１４及びドレイン電極１５の材料として、酸化インジウム（Ｉｎ２Ｏ３）、酸化スズ（ＳｎＯ２）、酸化亜鉛（ＺｎＯ）、酸化カドミウム（ＣｄＯ）、酸化インジウムカドミウム（ＣｄＩｎ２Ｏ４）、酸化カドミウムスズ（Ｃｄ２ＳｎＯ４）、酸化亜鉛スズ（Ｚｎ２ＳｎＯ４）又は酸化インジウム亜鉛（Ｉｎ−Ｚｎ−Ｏ）等の酸化物材料が好適に用いられる。 As a material for the gate electrode 11, the source electrode 14, and the drain electrode 15, a low resistance metal material such as Au, Ag, Cu, Cr, Al, Mg, Li is suitable. As materials for the gate electrode 11, the source electrode 14, and the drain electrode 15, indium oxide (In 2 O 3 ), tin oxide (SnO 2 ), zinc oxide (ZnO), cadmium oxide (CdO), and indium cadmium oxide (CdIn An oxide material such as 2 O 4 ), cadmium tin oxide (Cd 2 SnO 4 ), zinc tin oxide (Zn 2 SnO 4 ), or indium zinc oxide (In—Zn—O) is preferably used.
また、ゲート電極１１、ソース電極１４及びドレイン電極１５の材料が酸化物材料である場合、この酸化物材料に不純物をドープすることも導電率を上げるために好ましい。不純物としては、例えば、酸化インジウムにスズやモリブデン、チタンをドープしたもの、酸化スズにアンチモンやフッ素をドープしたもの、酸化亜鉛にインジウム、アルミニウム又はガリウムなどである。この中では、特に、酸化インジウムにスズをドープした酸化インジウムスズ（通称ＩＴＯ)が低い抵抗率のために特に好適に用いられる。また、ゲート電極１１、ソース電極１４及びドレイン電極１５の材料として、導電性酸化物材料と低抵抗金属材料を複数積層したものも使用できる。この場合、金属材料の酸化や経時劣化を防ぐために導電性酸化物薄膜／金属薄膜／導電性酸化物薄膜の順に積層した３層構造が特に好適に用いられる。ゲート電極１１、ソース電極１４及びドレイン電極１５は、全て同じ材料であっても構わないし、また全て違う材料であっても構わない。しかし、工程数を減らすためにソース電極１４とドレイン電極１５は同一の材料であることがより望ましい。 In addition, when the material of the gate electrode 11, the source electrode 14, and the drain electrode 15 is an oxide material, it is preferable to add impurities to the oxide material in order to increase the conductivity. Examples of the impurity include indium oxide doped with tin, molybdenum, and titanium, tin oxide doped with antimony or fluorine, and zinc oxide with indium, aluminum, or gallium. Among these, indium tin oxide (commonly called ITO) in which tin is doped in indium oxide is particularly preferably used because of its low resistivity. In addition, as the material for the gate electrode 11, the source electrode 14, and the drain electrode 15, a material in which a plurality of conductive oxide materials and low resistance metal materials are stacked can be used. In this case, a three-layer structure in which a conductive oxide thin film / metal thin film / conductive oxide thin film is laminated in order in order to prevent oxidation or deterioration with time of the metal material is particularly preferably used. The gate electrode 11, the source electrode 14, and the drain electrode 15 may all be the same material, or may be all different materials. However, in order to reduce the number of steps, it is more desirable that the source electrode 14 and the drain electrode 15 are made of the same material.
これらの電極は、真空蒸着法、イオンプレーティング法、スパッタ法、レーザーアブレーション法、プラズマＣＶＤ（Ｃｈｅｍｉｃａｌ Ｖａｐｏｒ Ｄｅｐｏｓｉｔｉｏｎ）法，ホットワイヤーＣＶＤ法等で形成される。また、これらの電極は、上述の導電性材料をインキ状、ペースト状にしたものをスクリーン印刷、凸版印刷又はインクジェット法等で塗布し焼成して形成することもできるが、これらに限定されるものではない。 These electrodes are formed by a vacuum deposition method, an ion plating method, a sputtering method, a laser ablation method, a plasma CVD (Chemical Vapor Deposition) method, a hot wire CVD method, or the like. In addition, these electrodes can be formed by applying the above-mentioned conductive material in ink or paste form by screen printing, letterpress printing or ink jet method, etc., and firing, but are not limited thereto. is not.
ゲート絶縁層１２の材料としては、酸化シリコン、窒化シリコン、シリコンオキシナイトライド、酸化アルミニウム、酸化タンタル、酸化イットリウム、酸化ハフニウム、ハフニウムアルミネート、酸化ジルコニア、酸化チタン等の無機材料、又は、ＰＭＭＡ（ポリメチルメタクリレート）等のポリアクリレート、ＰＶＡ（ポリビニルアルコール）、ＰＳ（ポリスチレン）、透明性ポリイミド、ポリエステル、エポキシ、ポリビニルフェノール又はポリビニルアルコール等が挙げられるがこれらに限定されるものではない。 As a material of the gate insulating layer 12, an inorganic material such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, yttrium oxide, hafnium oxide, hafnium aluminate, zirconia oxide, titanium oxide, or PMMA ( Polyacrylate such as polymethylmethacrylate), PVA (polyvinyl alcohol), PS (polystyrene), transparent polyimide, polyester, epoxy, polyvinylphenol, polyvinyl alcohol, and the like are exemplified, but not limited thereto.
ゲート絶縁層１２の材料としては、ゲートリーク電流を抑えるためには、絶縁材料の抵抗率は１０１１Ωｃｍ以上、特に１０１４Ωｃｍ以上であるものが好ましい。ゲート絶縁層１２は、真空蒸着法、イオンプレーティング法、スパッタ法、レーザーアブレーション法、プラズマＣＶＤ法、光ＣＶＤ法、ホットワイヤーＣＶＤ法、スピンコート、ディップコート又はスクリーン印刷などの方法を用いて形成される。ゲート絶縁層１２は、膜の成長方向に向けて組成を傾斜したものもまた好適に用いられる。 As a material of the gate insulating layer 12, in order to suppress a gate leakage current, it is preferable that the insulating material has a resistivity of 10 11 Ωcm or more, particularly 10 14 Ωcm or more. The gate insulating layer 12 is formed using a method such as vacuum deposition, ion plating, sputtering, laser ablation, plasma CVD, photo CVD, hot wire CVD, spin coating, dip coating, or screen printing. Is done. The gate insulating layer 12 having a composition inclined toward the film growth direction is also preferably used.
半導体層１３の材料として、水素化アモルファスシリコン、微結晶シリコン、多結晶シリコン又は単結晶シリコン等のシリコン半導体が挙げられる。また、半導体層１３の材料として、非シリコン半導体として亜鉛、インジウム、スズ、タングステン、マグネシウム、ガリウムのうち一種類以上の元素を含む酸化物が挙げられる。この酸化物として、例えば酸化亜鉛、酸化インジウム、酸化インジウム亜鉛、酸化スズ、酸化タングステン、酸化亜鉛ガリウムインジウム（Ｉｎ−Ｇａ−Ｚｎ−Ｏ）等公知の材料が挙げられるがこれらに限定されるものではない。これらの材料は、ＣＶＤ法、スパッタ法、パルスレーザー堆積法、真空蒸着法、ゾルゲル法等の方法を用いて形成される。ＣＶＤ法としてはホットワイヤーＣＶＤ法、プラズマＣＶＤ法、スパッタ法としてはＲＦマグネトロンスパッタ法、ＤＣスパッタ法、真空蒸着としては加熱蒸着、電子ビーム蒸着又はイオンプレーティング法、などが挙げられるがこれらに限定されるものではない。 Examples of the material of the semiconductor layer 13 include silicon semiconductors such as hydrogenated amorphous silicon, microcrystalline silicon, polycrystalline silicon, or single crystal silicon. In addition, examples of the material of the semiconductor layer 13 include oxides containing one or more elements of zinc, indium, tin, tungsten, magnesium, and gallium as a non-silicon semiconductor. Examples of the oxide include known materials such as zinc oxide, indium oxide, indium zinc oxide, tin oxide, tungsten oxide, and zinc gallium indium oxide (In—Ga—Zn—O), but are not limited thereto. Absent. These materials are formed using a method such as a CVD method, a sputtering method, a pulse laser deposition method, a vacuum evaporation method, or a sol-gel method. Examples of the CVD method include a hot wire CVD method, a plasma CVD method, a sputtering method such as an RF magnetron sputtering method, a DC sputtering method, and a vacuum deposition method such as heating evaporation, electron beam evaporation, or ion plating method. Is not to be done.
また、半導体層１３としては、テトラセン、ペンタセン、オリゴチオフェン誘導体、フタロシアニン類、ベリレン誘導体等の低分子有機半導体や、ポリフルオレン、ポリフェニレンビニレン、ポリトリアリルアミン等の高分子有機半導体も挙げられるがこれらに限定されるものではない。これらの材料はスピンコート、ディップコート、スクリーン印刷、インクジェット法等を用いて形成される。 Examples of the semiconductor layer 13 include low molecular organic semiconductors such as tetracene, pentacene, oligothiophene derivatives, phthalocyanines, and berylene derivatives, and high molecular organic semiconductors such as polyfluorene, polyphenylene vinylene, and polytriallylamine. It is not limited. These materials are formed using spin coating, dip coating, screen printing, an ink jet method, or the like.
保護層１６は、真空紫外光ＣＶＤ法により成膜することで、ソース電極１４、ドレイン電極１５及び半導体層１３の形成領域と、ゲート絶縁層１２の上に均一で平坦な膜を形成することができる。真空紫外光ＣＶＤ法を用いて成膜した膜は、基板の表面形状によらず高い自己平坦化特性を持つためである。これは、表面反応によって膜が形成されるのではなく、気相中で光分解して発生したラジカル等の反応活性種が、表面をマイグレーションしフローしながら堆積し、薄膜が形成されるためである。このため、ボトムゲート・トップコンタクト型の薄膜トランジスタにおいて、ソース電極１４及びドレイン電極１５を形成した後にゲート絶縁層１２の上の全面を被覆するように保護層１６となる膜を真空紫外光ＣＶＤ法により成膜し、保護層１６となる膜をエッチングする。 The protective layer 16 can be formed by a vacuum ultraviolet light CVD method to form a uniform and flat film on the formation region of the source electrode 14, the drain electrode 15, and the semiconductor layer 13 and the gate insulating layer 12. it can. This is because a film formed using the vacuum ultraviolet light CVD method has high self-flattening characteristics regardless of the surface shape of the substrate. This is because a film is not formed by a surface reaction, but reactive species such as radicals generated by photolysis in the gas phase are deposited while migrating and flowing on the surface to form a thin film. is there. For this reason, in the bottom gate / top contact type thin film transistor, after forming the source electrode 14 and the drain electrode 15, a film serving as the protective layer 16 is formed by vacuum ultraviolet light CVD so as to cover the entire surface of the gate insulating layer 12. A film is formed and the film to be the protective layer 16 is etched.
このエッチング工程によって、ソース電極１４及びドレイン電極１５が露出される。しかし、半導体層１６を被覆させる必要があるので、所定の膜となった段階でエッチングが停止される。つまり、保護層１６は、ゲート絶縁膜１２の上の保護層１６の膜厚Ｄ１が半導体層１３の膜厚ＤＳとゲート電極１１に対応するゲート絶縁層１２の上の隆起高さＨＧとの合計値よりも大きく、かつ、半導体層１３の膜厚とソース電極１４及びドレイン電極１５の膜厚ＤＳＤとゲート電極１１に対応するゲート絶縁層１２の上の隆起高さＨＧとの合計値よりも小さくなる。すなわち、ＤＳ＋ＨＧ＜Ｄ１＜ＤＳ＋ＤＳＤ＋ＨＧの条件が成立するように保護層１６は形成される。 By this etching process, the source electrode 14 and the drain electrode 15 are exposed. However, since it is necessary to coat the semiconductor layer 16, the etching is stopped at the stage where the predetermined film is obtained. That is, the protective layer 16 has a thickness D1 of the protective layer 16 on the gate insulating film 12 that is the sum of the film thickness DS of the semiconductor layer 13 and the raised height HG on the gate insulating layer 12 corresponding to the gate electrode 11. Larger than the value and smaller than the total value of the film thickness of the semiconductor layer 13, the film thickness DSD of the source electrode 14 and the drain electrode 15, and the raised height HG on the gate insulating layer 12 corresponding to the gate electrode 11. Become. That is, the protective layer 16 is formed so that the condition DS + HG <D1 <DS + DSD + HG is satisfied.
また、半導体層１３の上の保護層１６について見ると、半導体層１３の上の保護層１６の膜厚Ｄ２と半導体層１３の膜厚ＤＳとゲート電極１１に対応するゲート絶縁層１２も上の隆起高さＨＧとの合計値が、ゲート絶縁膜１２の上の保護層１６の膜厚と実質的に等しく、かつ、半導体層１３の上の保護層１６の膜厚が半導体層１３の上のソース電極１４及びドレイン電極１５の膜厚よりも小さくなる（Ｄ１＝Ｄ２＋ＤＳ＋ＨＧ、Ｄ２＜ＤＳＤ）ように形成される。このようにすることで、ソース電極１４とドレイン電極１５の表面を露出させることで、フォトリソグラフィー法を用いたレジストパターニングの工程を省き、エッチングのみで保護層１６のパターンを形成することができる。 Looking at the protective layer 16 on the semiconductor layer 13, the thickness D2 of the protective layer 16 on the semiconductor layer 13, the thickness DS of the semiconductor layer 13, and the gate insulating layer 12 corresponding to the gate electrode 11 are also on the upper side. The total value of the raised height HG is substantially equal to the film thickness of the protective layer 16 on the gate insulating film 12, and the film thickness of the protective layer 16 on the semiconductor layer 13 is above the semiconductor layer 13. It is formed to be smaller than the film thickness of the source electrode 14 and the drain electrode 15 (D1 = D2 + DS + HG, D2 <DSD). In this way, by exposing the surfaces of the source electrode 14 and the drain electrode 15, a resist patterning process using a photolithography method can be omitted, and the pattern of the protective layer 16 can be formed only by etching.
ゲート絶縁膜を真空蒸着法や通常のＣＶＤのような成膜方法で形成する場合、ゲート絶縁層１２がゲート電極１１の膜厚ＤＧの分だけ隆起するために、半導体層１３の上に被覆される保護層１６の膜厚が変わってくる。したがって、ゲート電極１１に対応するゲート絶縁層１２の上の隆起高さＨＧは、ＨＧ＝ＤＧの条件を満足するものであり、保護層１６の基板上の高さレベルが一定であるとすると、Ｄ１とＤ２の関係はＤ１＝Ｄ２＋ＤＳ＋ＤＧとなる。 When the gate insulating film is formed by a film forming method such as vacuum deposition or normal CVD, the gate insulating layer 12 is covered on the semiconductor layer 13 in order to protrude by the film thickness DG of the gate electrode 11. The film thickness of the protective layer 16 changes. Therefore, the raised height HG on the gate insulating layer 12 corresponding to the gate electrode 11 satisfies the condition HG = DG, and the height level on the substrate of the protective layer 16 is constant. The relationship between D1 and D2 is D1 = D2 + DS + DG.
さらに、ソース電極１４及びドレイン電極１５の膜厚が、半導体層１３の膜厚とゲート電極１１に対応するゲート絶縁層１２の上の隆起高さとの合計値よりも厚ければ（ＤＳＤ＞ＤＳ＋ＨＧ）、上述のエッチング方法により半導体層１３を露出させることなくソース電極１４及びドレイン電極１５の全面を露出させることができるため、配線や画素電極との接続が容易である。ＨＧ＝０，すなわち、ゲート絶縁層１２を真空紫外光ＣＶＤ法や各種のウェットコーティング法などの自己平坦化性の高い成膜方法で成膜する場合には、ソース電極１４及びドレイン電極１５の膜厚が、半導体層１３の膜厚よりも厚ければ（ＤＳＤ＞ＤＳ）よい。 Furthermore, if the film thickness of the source electrode 14 and the drain electrode 15 is larger than the total value of the film thickness of the semiconductor layer 13 and the raised height on the gate insulating layer 12 corresponding to the gate electrode 11 (DSD> DS + HG). Since the entire surface of the source electrode 14 and the drain electrode 15 can be exposed without exposing the semiconductor layer 13 by the above-described etching method, connection with a wiring or a pixel electrode is easy. When HG = 0, that is, when the gate insulating layer 12 is formed by a film forming method having high self-flattening properties such as a vacuum ultraviolet light CVD method and various wet coating methods, the film of the source electrode 14 and the drain electrode 15 The thickness should be larger than the thickness of the semiconductor layer 13 (DSD> DS).
保護層１６は、酸化シリコンを含む材料で形成されている。保護層１６を形成する場合には、出発材料として、オクタメチルシクロテトラシロキサン又はテトラエトキシシラン/Ｏ２等が挙げられる。保護層１６の抵抗値は、１０１１Ω・ｃｍ以上が好ましく、より好ましくは１０１４Ω・ｃｍ以上である。 The protective layer 16 is formed of a material containing silicon oxide. In the case where the protective layer 16 is formed, the starting material includes octamethylcyclotetrasiloxane or tetraethoxysilane / O 2 . The resistance value of the protective layer 16 is preferably 10 11 Ω · cm or more, more preferably 10 14 Ω · cm or more.
保護層１６を成膜後に、１００℃以上の熱処理が行われることが好ましい。例えば、真空紫外光ＣＶＤ法で酸化シリコンを、室温形成する場合に、有機シリコン化合物のシロキサン等を材料として形成される。その時、材料ガスが完全に分解するのではなく、一部は分解されて生成された反応活性種がマイグレーションし、フローしながら膜が形成するため、材料ガスに含まれるＳｉ−ＣＨ３等も膜中に多く含まれる。このため、保護層１６は、膜中に未分解材料を含む。保護層１６の膜中の未分解材料により膜の抵抗値が低下する場合があるが、熱処理を行うことにより、膜中に含まれる未分解材料が減少し、上記に示す高い抵抗値を得ることが可能となる。 It is preferable that a heat treatment at 100 ° C. or higher is performed after forming the protective layer 16. For example, when silicon oxide is formed at room temperature by a vacuum ultraviolet light CVD method, the organic silicon compound siloxane or the like is used as a material. At that time, the material gas is not completely decomposed, but a part of the reaction active species generated by decomposition is migrated and a film is formed while flowing. Therefore, Si—CH 3 or the like contained in the material gas is also formed in the film. Many are included. For this reason, the protective layer 16 contains an undecomposed material in the film. Although the resistance value of the film may decrease due to the undecomposed material in the film of the protective layer 16, the undecomposed material contained in the film is reduced by performing heat treatment, and the high resistance value shown above is obtained. Is possible.
以下、本発明の実施例１を説明する。実施例１では図２に示すようなボトムゲート−トップコンタクト型の薄膜トランジスタのアレイ基板が作製された。この薄型トランジスタのアレイ基板は、１画素のサイズが１２５μｍ×１２５μｍであり、この画素が４８０×６４０個あるものである。図３は、１画素分を拡大して示す略拡大図である。絶縁基板１０としてＰＥＮ基材（帝人デュポン社製Ｑ６５ 厚さ１２５μｍ）上に、ＤＣマグネトロンスパッタ装置を用いて厚さが５０ｎｍのＩＴＯが成膜され、フォトリソグラフィー法を用いたエッチングによりゲート電極１１、ゲート配線２１、キャパシタ電極２２、キャパシタ配線２３が形成された。 Embodiment 1 of the present invention will be described below. In Example 1, an array substrate of bottom gate-top contact type thin film transistors as shown in FIG. 2 was produced. This thin transistor array substrate has a size of one pixel of 125 μm × 125 μm and 480 × 640 pixels. FIG. 3 is a schematic enlarged view showing one pixel enlarged. An ITO substrate having a thickness of 50 nm is formed on a PEN base material (Q65 thickness 125 μm manufactured by Teijin DuPont) as an insulating substrate 10 by using a DC magnetron sputtering apparatus, and the gate electrode 11 is formed by etching using a photolithography method. Gate wiring 21, capacitor electrode 22, and capacitor wiring 23 were formed.
ＩＴＯ成膜時の投入電力は１００Ｗとされ、ガス流量はＡｒ＝５０ＳＣＣＭ、Ｏ２＝０．１ＳＣＣＭとされ、成膜圧力は１．０Ｐａとされた。次に、ＲＦマグネトロンスパッタ装置を用いてＳｉＯＮからなる厚さが３００ｎｍのゲート絶縁層１２が投入電力は５００Ｗ、Ａｒ＝５０ＳＣＣＭ、Ｏ２＝２０ＳＣＣＭ、成膜圧力１．０Ｐａの条件で成膜された。また、Ｉｎ―Ｇａ―Ｚｎ―Ｏ系酸化物からなる厚さが３０ｎｍの半導体層１３が投入電力１００Ｗ、Ａｒ＝１００ＳＣＣＭ、Ｏ２＝２ＳＣＣＭ、成膜圧力１．０Ｐａの条件で連続成膜された。 The input power during the ITO film formation was 100 W, the gas flow rates were Ar = 50 SCCM, O 2 = 0.1 SCCM, and the film formation pressure was 1.0 Pa. Next, a gate insulating layer 12 made of SiON and having a thickness of 300 nm was formed using an RF magnetron sputtering apparatus under conditions of an input power of 500 W, Ar = 50 SCCM, O 2 = 20 SCCM, and a film forming pressure of 1.0 Pa. . Further, a semiconductor layer 13 made of an In—Ga—Zn—O-based oxide and having a thickness of 30 nm was continuously formed under the conditions of an input power of 100 W, Ar = 100 SCCM, O 2 = 2 SCCM, and a film formation pressure of 1.0 Pa. .
半導体層１３がフォトリソグラフィー法を用いてエッチングにより形成された後、さらにレジストが塗布され、乾燥及び現像を行った後、ＤＣマグネトロンスパッタ装置を用いて厚さが１５０ｎｍのＩＴＯが投入電力１００Ｗ、Ａｒ＝５０ＳＣＣＭ、Ｏ２＝０．１ＳＣＣＭ、成膜圧力１．０Ｐａの条件で形成され、リフトオフによりソース電極１４、ソース配線２４、ドレイン電極１５及び画素電極２５が形成された。その上に図４に示すように、真空紫外光ＣＶＤ装置を用いて保護層１６となる厚さが３００ｎｍのＳｉＯ２膜（ゲート配線２１が形成されている部分のゲート絶縁層の表面を基準面とした膜厚）が成膜された。 After the semiconductor layer 13 is formed by etching using a photolithography method, a resist is further applied, and after drying and development, ITO having a thickness of 150 nm is applied using a DC magnetron sputtering apparatus with an input power of 100 W, Ar = 50 SCCM, O 2 = 0.1 SCCM, and a film forming pressure of 1.0 Pa. The source electrode 14, the source wiring 24, the drain electrode 15, and the pixel electrode 25 were formed by lift-off. Further, as shown in FIG. 4, a SiO 2 film having a thickness of 300 nm serving as the protective layer 16 using a vacuum ultraviolet light CVD apparatus (the surface of the gate insulating layer where the gate wiring 21 is formed is used as a reference plane). Film thickness) was formed.
このＳｉＯ２膜は、原料としてオクタメチルシクロテトラシロキサンが５SCCM流され、投入電力が１００Ｗとされ、成膜圧力が１０Ｐａとされて成膜された。成膜後、リアクティブイオンエッチング装置を用いてソース電極１４、ソース配線２４、ドレイン電極１５及び画素電極２５の表面が露出され、半導体層１３上の保護層１６の膜厚が５０ｎｍになるまでＳｉＯ２がエッチングされ、保護層１６のパターンが形成された（図５）。エッチングガスはＣＦ４が用いられ、投入電力は３００Ｗとされ、エッチング圧力は５Ｐａとされた。最後に薄膜トランジスタのアレイ基板に対して１５０℃で３時間、大気中で熱処理が行なわれ、対向電極との間に電気泳動媒体を挟んで駆動されたところ、良好な表示がなされた。 The SiO 2 film was formed with 5 SCCM of octamethylcyclotetrasiloxane as a raw material, an input power of 100 W, and a film forming pressure of 10 Pa. After the film formation, the surface of the source electrode 14, the source wiring 24, the drain electrode 15, and the pixel electrode 25 is exposed using a reactive ion etching apparatus until the film thickness of the protective layer 16 on the semiconductor layer 13 becomes 50 nm. 2 was etched, and the pattern of the protective layer 16 was formed (FIG. 5). The etching gas used was CF 4 , the input power was 300 W, and the etching pressure was 5 Pa. Finally, the thin film transistor array substrate was heat-treated at 150 ° C. for 3 hours in the atmosphere, and when driven with the electrophoretic medium sandwiched between the counter electrode, good display was obtained.
本発明の実施の形態においては、ボトムゲート−トップコンタクト型の薄膜トランジスタにおいて、保護層１６のパターンをフォトリソグラフィー法を使わずに簡易に形成することで、製造コストが低減され、歩留まりの高い薄膜トランジスタ及びこの薄膜トランジスタを具備する画像表示装置を提供することができる。 In the embodiment of the present invention, in the bottom gate-top contact type thin film transistor, the pattern of the protective layer 16 is simply formed without using a photolithography method, so that the manufacturing cost is reduced and the thin film transistor with high yield is obtained. An image display device including the thin film transistor can be provided.
このような本発明の薄膜トランジスタは、電子ペーパー、ＬＣＤ又は有機ＥＬディスプレイ等のスイッチング素子として利用できる。また、本発明の薄膜トランジスタは、特に、フレキシブル基材を基板とするフレキシブルディスプレイ、ＩＣカード又はＩＣタグ等にも広く応用することができる。 Such a thin film transistor of the present invention can be used as a switching element for electronic paper, LCD, organic EL display or the like. In addition, the thin film transistor of the present invention can be widely applied to a flexible display, an IC card, an IC tag, or the like using a flexible substrate as a substrate.
１０ 絶縁基板
１１ ゲート電極
１２ ゲート絶縁層
１３ 半導体層
１４ ソース電極
１５ ドレイン電極
１６ 保護層
２１ ゲート配線
２２ キャパシタ電極
２３ キャパシタ配線
２４ ソース配線
２５ 画素電極
DESCRIPTION OF SYMBOLS 10 Insulating substrate 11 Gate electrode 12 Gate insulating layer 13 Semiconductor layer 14 Source electrode 15 Drain electrode 16 Protective layer 21 Gate wiring 22 Capacitor electrode 23 Capacitor wiring 24 Source wiring 25 Pixel electrode
Claims (8)
前記絶縁基板上に、前記ゲート電極と、前記ゲート絶縁層と、前記半導体層と、前記ソース電極と前記ドレイン電極とを順に形成した後、前記ゲート絶縁層の上の全面に前記保護層となる膜を成膜する工程と、前記保護層となる膜をパターニングなしにエッチングし前記ソース電極と前記ドレイン電極の表面を露出させ前記保護層のパターンを形成する工程を具備し、
前記保護層は真空紫外光ＣＶＤ法により形成されており、
前記半導体層上の前記ソース電極及び前記ドレイン電極の膜厚は、前記半導体層と前記ゲート電極との膜厚の合計値よりも厚い、
ことを特徴とする薄膜トランジスタの製造方法。 A gate electrode formed on a part of an insulating substrate; a gate insulating layer formed on the insulating substrate and the gate electrode; a semiconductor layer formed on a part of the gate insulating layer; a protective layer formed on a part of a portion over the gate insulating layer where the semiconductor layer is not formed and the semiconductor layer, one on part and the semiconductor layer on said gate insulating layer A method of manufacturing a thin film transistor comprising at least a source electrode and a drain electrode that are formed over a portion and exposed from the protective layer ,
The gate electrode, the gate insulating layer, the semiconductor layer, the source electrode, and the drain electrode are sequentially formed on the insulating substrate, and then the protective layer is formed on the entire surface of the gate insulating layer. A step of forming a film, and a step of etching the film to be the protective layer without patterning to expose the surfaces of the source electrode and the drain electrode to form a pattern of the protective layer,
The protective layer is formed by a vacuum ultraviolet light CVD method,
The film thickness of the source electrode and the drain electrode on the semiconductor layer is thicker than the total thickness of the semiconductor layer and the gate electrode,
A method for manufacturing a thin film transistor.
前記半導体層上の前記ソース電極及び前記ドレイン電極の膜厚は、前記半導体層と前記ゲート電極との膜厚の合計値よりも厚く、
前記保護層は、前記絶縁基板上に、前記ゲート電極と、前記ゲート絶縁層と、前記半導体層と、前記ソース電極と前記ドレイン電極とを順に形成した後に、前記半導体層の前記ソース電極及び前記ドレイン電極が形成されていない領域と少なくとも前記ゲート絶縁膜の上の一部とに、真空紫外光ＣＶＤ法により形成され、
前記ゲート絶縁膜の上の保護層の膜厚は、前記半導体層の膜厚と前記ゲート電極に対応する前記ゲート絶縁層の上の隆起高さとの合計値よりも大きく、かつ、前記ゲート絶縁膜の上の前記保護層の膜厚は、前記半導体層の膜厚と前記ソース電極及び前記ドレイン電極の膜厚と前記ゲート電極に対応する前記ゲート絶縁層の上の隆起高さとの合計値よりも小さくなり、前記半導体層の上の保護層の膜厚は、前記半導体層の上の前記ソース電極及び前記ドレイン電極の膜厚よりも小さくなるように形成されている、
ことを特徴とする薄膜トランジスタ。 A gate electrode formed on a part of an insulating substrate; a gate insulating layer formed on the insulating substrate and the gate electrode; a semiconductor layer formed on a part of the gate insulating layer; a protective layer formed on a part of a portion over the gate insulating layer where the semiconductor layer is not formed and the semiconductor layer, one on part and the semiconductor layer on said gate insulating layer A thin film transistor comprising at least a source electrode and a drain electrode that are formed over a portion and exposed from the protective layer ,
The thickness of the source electrode and the drain electrode on the semiconductor layer, rather thick than the sum of the thickness of the gate electrode and the semiconductor layer,
The protective layer is formed on the insulating substrate by sequentially forming the gate electrode, the gate insulating layer, the semiconductor layer, the source electrode, and the drain electrode, and then the source electrode and the semiconductor layer. Formed in a region where the drain electrode is not formed and at least a part on the gate insulating film by a vacuum ultraviolet light CVD method,
The film thickness of the protective layer on the gate insulating film is larger than the total value of the film thickness of the semiconductor layer and the raised height on the gate insulating layer corresponding to the gate electrode, and the gate insulating film The film thickness of the protective layer on the substrate is greater than the sum of the film thickness of the semiconductor layer, the film thickness of the source and drain electrodes, and the raised height on the gate insulating layer corresponding to the gate electrode. The thickness of the protective layer on the semiconductor layer is smaller than the thickness of the source electrode and the drain electrode on the semiconductor layer;
A thin film transistor.
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