JP3694470B2 - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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Publication number
JP3694470B2
JP3694470B2 JP2001163787A JP2001163787A JP3694470B2 JP 3694470 B2 JP3694470 B2 JP 3694470B2 JP 2001163787 A JP2001163787 A JP 2001163787A JP 2001163787 A JP2001163787 A JP 2001163787A JP 3694470 B2 JP3694470 B2 JP 3694470B2
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Japan
Prior art keywords
insulating film
film layer
protrusion
semiconductor substrate
manufacturing
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Expired - Fee Related
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JP2001163787A
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Japanese (ja)
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JP2002359241A (en
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清彦 歳川
理一 本山
淳一 宮野
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Oki Electric Industry Co Ltd
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Oki Electric Industry Co Ltd
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Priority to JP2001163787A priority Critical patent/JP3694470B2/en
Priority to US10/059,174 priority patent/US20020182845A1/en
Priority to US10/307,280 priority patent/US20030119234A1/en
Publication of JP2002359241A publication Critical patent/JP2002359241A/en
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Publication of JP3694470B2 publication Critical patent/JP3694470B2/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/04—Coating on selected surface areas, e.g. using masks
    • C23C16/045—Coating cavities or hollow spaces, e.g. interior of tubes; Infiltration of porous substrates
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
    • C23C16/40—Oxides
    • C23C16/401—Oxides containing silicon
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    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/48—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating by irradiation, e.g. photolysis, radiolysis, particle radiation
    • C23C16/482—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating by irradiation, e.g. photolysis, radiolysis, particle radiation using incoherent light, UV to IR, e.g. lamps
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
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    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
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Description

【０００１】
【発明の属する技術分野】
本発明は、ＭＯＳＦＥＴのような半導体装置の製造に好適な製造方法に関し、特に、層間絶縁膜、ダマシン法による配線、ＦＥＴのゲートあるいはメモリキャパシタの電極の形成等に適用し得る絶縁膜層の製造方法に関する。
【０００２】
【従来の技術】
半導体基板上に集合的に形成されるＭＯＳＦＥＴのような半導体素子の集合体からなる半導体装置の集積度を高める技術の１つに多層配線構造がある。この多層配線構造をフォトリソエッチング法で実現する上で、半導体基板上の半導体素子を埋め込む平坦性に優れた絶縁膜層を形成する技術は、極めて重要である。
【０００３】
本願発明者等は、２０００年３月３１日に日本で開催された電子情報通信学会総合大会において、その予稿集の第８４頁および第８５頁に示されているとおり、半導体基板に形成された絶縁膜上に減圧ＣＶＤ法を用いて絶縁膜層を形成する方法を提案した。
【０００４】
この絶縁膜層の形成方法によれば、絶縁膜層を成長させるべき半導体基板が配置された減圧ＣＶＤ装置の反応室に、原料ガスとして、ＴＥＯＳを供給しかつ添加ガスとして酸素ガスを供給し、前記半導体基板の前記絶縁膜上に真空紫外光を照射した状態で前記絶縁膜層を成長させることにより、良好な絶縁膜層を形成することができる。
【０００５】
【発明が解決しようとする課題】
本発明は、さらに良質な絶縁膜層を形成することができる新規な方法を含む、半導体装置の製造に好適かつ有益な新規な方法を提供することを目的とする。
また、本発明の他の目的は、半導体基板上の突起部により規定される凹所を好適に埋め込むことにより、平坦化特性に優れた絶縁膜層を形成し得る新規な方法を提供することにある。
さらに、本発明の他の目的は、層間絶縁膜、ダマシン法による配線、ＦＥＴのゲートあるいはメモリキャパシタの電極の形成等に適用するのに好適でありかつ新規な、半導体装置の製造方法を提供することにある。
【０００６】
【課題を解決するための手段】
本発明は、半導体基板上の選択された領域に減圧ＣＶＤ法を用いて絶縁膜層を形成する工程を含む半導体装置の製造方法において、原料ガスとして、ヘキサメチルジシロキサン（(CH3)3SiOSi(CH3)3）を用いるという基本構想に立脚する。
【０００７】
すなわち、本発明に係る半導体装置の製造方法は、半導体基板上の選択された領域に減圧ＣＶＤ法を用いて絶縁膜層を形成する工程を含む半導体装置の製造方法であって、前記絶縁膜層の形成工程は、前記絶縁膜層を成長させるべき前記半導体基板が配置された減圧ＣＶＤ装置の反応室に、原料ガスとして、ヘキサメチルジシロキサンを供給しかつ添加ガスとして酸素を供給し、前記半導体基板上に真空紫外光を照射した状態で前記絶縁膜層を成長させることを特徴とする。
【０００８】
本発明に係る前記製造方法によれば、たとえば前記基板上に形成された突起部を埋め込むように、層間絶縁膜として望ましい特性である低誘電率を示しかつ良質な絶縁膜層を選択的に成長させることができる。
【０００９】
前記突起部は、有機成分を含むフォトレジスト材料または導電性材料により、形成することができ、前記半導体基板上の前記突起部を除く領域、すなわち前記突起部により規定される凹所に前記絶縁膜層を選択的に成長させることができる。
【００１０】
前記製造方法は、配線あるいはゲートのような導電部の形成に利用できる。たとえばダマシン法による配線の形成では、前記半導体基板上に導電性材料からなる導電部を形成し、該導電部が形成された前記半導体基板における前記導電部を除く領域に、前記ＣＶＤ法を用いて前記導電部とほぼ同一の高さ位置まで前記絶縁膜層を成長させ、その後、前記絶縁膜層および該絶縁膜層から露出する前記導電部の表面を覆うべく、新たに絶縁材料を堆積させることができる。
【００１１】
この新たな絶縁材料は、たとえば前記ＣＶＤ装置を用い、前記真空紫外光の照射下でその反応室に前記酸素の供給を絶った状態でヘキサメチルジシロキサンを供給することにより、堆積させることができる。また、これに代えて、従来の種々の堆積方法を用いて前記した新たな絶縁材料を堆積させることができる。
【００１２】
また、ゲートのような導電部の形成では、前記半導体基板上に形成された絶縁膜上に有機成分を含むフォトレジスト材料により、所望のゲートに対応した形状の突起部を形成することができる。前記突起部が形成された前記半導体基板の前記絶縁膜における前記突起部を除く領域に、前記ＣＶＤ法を用いて前記導電部とほぼ同一の高さ位置まで前記絶縁膜層を成長させ、その後、前記フォトレジスト材料からなる前記突起部が除去される。この突起部の除去によって、前記絶縁膜層により規定される凹所内は、導電部のための導電性材料で埋め込むまれ、これにより、ゲートのような導電部を形成することができる。このゲートの形成では、前記絶縁膜は、ゲート酸化膜である。
【００１３】
本発明に係る前記方法は、多層配線のためのデュアルダマシン法に適用することができる。
すなわち、前記半導体基板上に導電性材料からなる下層配線たる導電部を形成し、該導電部上に前記フォトレジスト材料からなる柱部を形成し、該柱部が形成された前記半導体基板上における前記柱部を除く領域に、前記ＣＶＤ法を用いて前記柱部とほぼ同一の高さ位置まで絶縁膜層を成長させる。その後、前記柱部の頂面から前記絶縁膜層上に延びる、上層配線のための、前記フォトレジスト材料からなる突起部を形成し、前記絶縁膜層上の前記突起部から露出する領域に、前記ＣＶＤ法を用いて前記突起部とほぼ同一の高さ位置まで新たに前記絶縁膜層を成長させる。
その後、前記フォトレジスト材料からなる前記突起部および前記柱部を除去し、前記突起部および前記柱部の除去によって前記両絶縁膜層により規定される凹所内を導電性材料で埋め込むことにより、ダマシン法を用いた多層配線が比較的容易に実現できる。
【００１４】
本発明に係る前記方法は、電界効果型トランジスタの製造に適用でき、たとえばそのソース・ドレインに至る導電部の形成に適用することができる。
【００１５】
また、本発明に係る前記方法は、たとえばＤＲＡＭ（ダイナミック・ランダム・アクセス・メモリ）の各メモリセルのキャパシタの製造に適用することができ、たとえば、そのキャパシタの一方の電極の形成に適用することができる。
【００１６】
半導体基板上の突起部により規定される凹所内に減圧ＣＶＤ法を用いて絶縁膜層を選択的に形成する場合、前記原料ガスとして、ヘキサメチルジシロキサンに代えて、テトラエトキシオルソシリケイト（Si(OC2H5)4）を用いても、有機成分を含むフォトレジスト材料または導電性材料により形成された前記突起部により規定される凹所内の前記半導体基板上に、選択的に良好に絶縁膜層を成長させることができることが、新たに判明した。
【００１７】
【発明の実施の形態】
以下、本発明を図示の実施の形態について詳細に説明する。
〈具体例〉
図１は、本発明に係る製造方法を実施するための減圧ＣＶＤ装置を概略的に示す。減圧ＣＶＤ装置１０は、たとえばＭＯＳトランジスタのような半導体装置の製造工程で、たとえばシリコン酸化膜のような絶縁膜層の形成に用いられる。
【００１８】
減圧ＣＶＤ装置１０は、図１に示されているように、反応室１１を規定するための全体に筒状のハウジング１２と、反応室１１内を減圧状態に維持すべく前記ハウジング１２の一端に配管１３を介して接続された例えば真空ポンプからなる負圧源１４と、前記反応室１１内に、例えばシリコンからなる半導体ウエハ１５を保持するサスセプタ１６と、例えばＸeエキシマランプのような真空紫外光源１７とを備える。真空紫外光源１７として、波長が約２００ｎｍよりも短波長のいわゆる真空紫外領域の紫外光を発する光源を適宜選択することができる。
【００１９】
半導体ウエハ１５は、その表面に形成されたシリコン酸化膜１５ａを上方に向けて、サスセプタ１６上に保持されており、該サスセプタによる温度調整により、半導体ウエハ１５の温度は、室温から３５０℃の間で調整可能である。
真空紫外光源１７は、例えば２０ｍｍの厚さ寸法を有する合成石英板が装着された照射窓となる石英窓１７ａが半導体ウエハ１５の上方に位置するように、ハウジング１２に支持されており、石英窓１７ａを通して、真空紫外光を半導体ウエハ１５のシリコン酸化膜１５ａに向けて照射する。
【００２０】
本発明に係る前記製造方法では、半導体ウエハ１５のシリコン酸化膜１５ａ上への絶縁膜層を成長させるために反応室１１内に供給される原料ガスとして、ヘキサメチルジシロキサン（(CH3)3SiOSi(CH3)3：以下、単にＨＭＤＳＯと称する。）が用いられ、また、添加ガスとして、酸素（Ｏ2）が用いられる。
【００２１】
サスセプタ１６上で室温に保持された半導体ウエハ１５と真空紫外光源１７の石英窓１７ａとの間隔が、例えば約１５ｍｍに保持された状態で、真空紫外光の照度が石英窓１７ａの直下で１０ｍＷ／ｃｍ2でもって前記半導体ウエハ１５が真空紫外線の照射を受ける。この環境下で、前記ＨＭＤＳＯが例えば５０ｓｃｃｍ、前記酸素がＨＭＤＳＯと同一の流量である５０ｓｃｃｍで以て、反応室１１内に供給される。このときの反応室１１内の反応圧力は、６００ｍＴｏｒｒであった。
後述する絶縁膜層の石英窓１７ａ上への成長による該石英窓の曇りを防止する上で、この石英窓１７ａを真空紫外線源の温度を超える温度で加熱することが望ましい。
【００２２】
前記した条件下での前記減圧ＣＶＤ装置１０の約１０分間の運転により、半導体ウエハ１５のシリコン酸化膜１５ａ上には、約５０００Åの二酸化シリコンを主成分とする絶縁膜層が成長した。
【００２３】
図２は、フーリエ変換赤外分光法を用いて前記絶縁膜層の成分を分析した結果を示すグラフである。
グラフの横軸は試料である前記絶縁膜層に照射される赤外光の波長の逆数すなわち波数（ｃｍ-1）を示し、またその縦軸は、吸光度（任意単位）を示す。
前記フーリエ変換赤外分光法によれば、試料に照射される赤外光の波長を連続的にシフトしたとき、その照射を受ける物質に応じたそれぞれの波長の赤外光が高い吸収率で吸収される。従って、吸収率が急激に増加するところの波数を求めることにより、その物質の成分を知ることができる。
【００２４】
図２に示された分析結果によれば、そのグラフに示されているとおり、主成分たる二酸化シリコンに加えて、Ｓｉ2Ｏ、ＳｉＯＨおよびＳｉＣＨ3が形成されている。これらは何れも電気絶縁性を示し、特に、ＳｉＣＨ3は、有機物であり、主成分である二酸化シリコンよりも低い誘電率を示すことから、半導体装置の層間絶縁膜として優れた電気特性をもたらす。
しかも、本発明に係る前記方法によって形成される前記絶縁膜層は、平坦性に優れることから、該絶縁膜層上へのフォトリソエッチング技術に有利であり、半導体装置の種々の製造工程に適用することができる。
【００２５】
図３は、本発明に係る前記製造方法を半導体装置の層間絶縁膜の製造に利用した例を示す。
例えばＭＯＳトランジスタのような半導体装置の製造工程では、図３（ａ）に示すように、例えばシリコン半導体基板１８上に複数の配線１９が形成される。前記半導体基板１８には、ＭＯＳトランジスタのような図示しない回路素子が形成されており、前記半導体基板１８上のこれら回路素子のために、前記配線１９が、前記半導体基板１８上のシリコン酸化膜のような例えば５０００Åの厚さ寸法を有する絶縁膜１８ａ上に形成される。
【００２６】
前記配線１９は、従来よく知られているように、例えばタングステンあるいはＡｌ−Ｓｉ−Ｃｕ合金のような金属材料からなり、各配線１９は、例えば０．５μｍの高さ寸法および０．３μｍの幅寸法を有し、各配線１９は、その幅方向へ例えば０．５μｍの間隔をおいて相互に平行に伸長する。
【００２７】
前記配線１９が形成された前記半導体基板１８を図１に示した減圧ＣＶＤ装置１０のサスセプタ１６上に、前記配線１９を上方へ向けて配置し、前記したと同一の成長条件で、前記した絶縁膜層を成長させることにより、図３（ｂ）に示されているように、前記絶縁膜１８ａ上の前記配線１９から露出する領域に、二酸化シリコンを主成分としてＳｉＣＨ3を含む図２のグラフに示されたと同様な絶縁膜層２０を選択的に成長させることができた。
【００２８】
前記絶縁膜層２０は、絶縁膜１８ａ上で突起部を構成する前記配線１９上を除き、該配線間で規定される凹所２１で、集中的に堆積されることから、絶縁膜１８ａ上に選択的に成長する。この絶縁膜層２０は、約１０分間の成長により、図３（ｂ）に示すとおり、絶縁膜層２０の頂面が前記配線１９のそれに一致する迄に成長する。
【００２９】
前記絶縁膜層２０は、極めて高い平坦特性を示すことから、前記配線１９および該配線間を充填する前記絶縁膜層２０により、平坦面が規定される。従って、化学機械研磨（ＣＭＰ）あるいはプラズマドライエッチング処理等により前記した平坦面を得るためのエッチングバック処理を絶縁膜層２０に施すことなく、単に、例えば３０００Åの厚さ寸法に新たな絶縁材料（２２）を堆積させることにより、図３（ｃ）に示されているように、突起部である前記配線１９およびその間を埋設する絶縁膜層２０を覆うように、表面が平坦な層間絶縁膜２２を形成することができる。
【００３０】
新たな絶縁材料（２２）の堆積のために、前記減圧ＣＶＤ装置１０内で前記真空紫外光の照射下、前記酸素の供給を絶ち、前記ＨＭＤＳＯのみを供給することができ、これにより、平坦な層間絶縁膜２２を形成することができる。
また、これに代えて、層間絶縁膜２２の形成のために、従来よく知られたプラズマエンハンスドＣＶＤ（ＰＥＣＶＤ）、低圧ＣＶＤ（ＬＰＣＶＤ）あるいは常圧ＣＶＤ（ＡＰＣＶＤ）の各法を適宜用いることができる。
【００３１】
前記した前記突起部１９間の間隔が０．３〜０．７μｍの範囲では、絶縁膜層２０による良好な凹所２１の充填効果が認められた。
【００３２】
前記したように、本発明に係る前記方法によれば、前記半導体基板１８の絶縁膜１８ａ上に形成された前記突起部１９により規定される凹所２１内を絶縁膜層２０で適正に充填することができ、これによりエッチングバック処理を不要として平坦な層間絶縁膜２２を成長させることができることから、半導体装置の製造工程の簡素化および生産コストの低減等を図ることができる。
【００３３】
前記半導体基板１８の絶縁膜１８ａ上に形成された前記突起部１９により規定される凹所２１内を前記したと同様な絶縁膜層で適正に充填することができる現象は、図１に示した減圧ＣＶＤ装置１０を用いる方法で、原料ガスとして、前記ＨＭＤＳＯに代えて、テトラエトキシオルソシリケイト（Si(OC2H5)4：以下、単にＴＥＯＳと称する。）を用いても生じることが確認できた。
【００３４】
真空紫外光源１７が設けられた減圧ＣＶＤ装置１０への原料ガスとして、このＴＥＯＳを用いた製造方法では、前記ＴＥＯＳが例えば５０ｓｃｃｍ、前記酸素がＴＥＯＳと同一の流量である５０ｓｃｃｍで以て、反応室１１内に供給される。このときの反応室１１内の反応圧力は、ＨＭＤＳＯにおけると同様に、６００ｍＴｏｒｒであった。また、真空紫外光源１７からの真空紫外光の照度が石英窓１７ａの直下で１０ｍＷ／ｃｍ2であった。
【００３５】
このＴＥＯＳを用いた例では、サスセプタ１６上に保持された半導体ウエハ１５と真空紫外光源１７の石英窓１７ａとの間隔は、約１００ｍｍに保持され、また石英窓１７ａ直下の温度が２００℃に保持されるように、石英窓１７ａが加熱され。
【００３６】
ＴＥＯＳを用いた前記成長条件下では、約３０分間に、図３に示したと同様な前記半導体基板１８の絶縁膜１８ａ上の前記突起部１９により規定される凹所２１内で、絶縁膜１８ａ上に、約５０００Åの厚さ寸法の二酸化シリコンを主成分とする絶縁膜層が集中的に堆積した。
この絶縁膜層の前記した選択的な成長により、図３に示したと同様、前記突起部１９とその凹所２１間に充填された絶縁膜層２０とにより規定される平坦面が形成され、この平坦面上に、前記したと同様な層間絶縁膜２２を形成することにより、エッチングバックを施すことなく、平坦な層間絶縁膜２２を形成することができた。
【００３７】
図４は、原料ガスにＴＥＯＳを用いた前記方法で形成された前記絶縁膜層２０の成分の分析結果を示す図２と同様なグラフである。
図４に示すグラフによれば、主成分たる二酸化シリコン（Ｓｉ2Ｏ）に加えて、これよりも低い誘電率を示す有機系のＳｉＯＣＨ2が形成されていることから、ＴＥＯＳを原料ガスとして形成された本発明に係る前記絶縁膜層２０は、半導体装置の層間絶縁膜として優れた電気特性をもたらす。また、ＴＥＯＳを原料ガスとして形成された本発明に係る絶縁膜層２０は、ＨＭＤＳＯを原料ガスとして形成した本発明に係る前記絶縁膜層２０におけると同様に、平坦性に優れ、前記した選択成長特性により、前記突起部１９により規定される凹所２１を適正に埋め込むことができる。
【００３８】
ＨＭＤＳＯおよびＴＥＯＳを用いた前記方法は、前記した選択成長特性を利用して、種々の半導体製造工程に利用することができる。
【００３９】
図５は、本発明に係る前記方法をダマシンプロセスに利用した例を示す。
図５（ａ）に示されているように、前記半導体基板１８上には、絶縁膜１８ａが形成され、該絶縁膜上には、前記配線１９のための例えば有機成分を含むフォトレジスト材料からなる複数のダミー１９′が形成される。各ダミー１９′は、例えば０．５μｍの幅寸法および０．５μｍの高さ寸法を有し、相互に例えば０．１μｍの間隔をおいて平行に伸びる。
【００４０】
このダミー１９′の形成のために、従来のフォトレジストパターンの形成におけると同様に、絶縁膜１８ａ上に、感光性を有するフォトレジスト材料がほぼ均一な厚さ寸法に塗布される。前記フォトレジスト材料が塗布されて成るフォトレジスト層は、所望のフォトマスクを用いて選択的な露光を受け、その後、現像処理を受ける。このフォトマスクを用いたフォトレジスト材料への選択露光および現像処理を含むリソグラフィ技術により、所望形状のダミー１９′が形成される。このダミー１９′のためのフォトレジストとして、ポジティブ型、ネガティブ型のいずれかを必要に応じて選択することができる。
【００４１】
また、絶縁膜１８ａ上にフォトレジスト材料を塗布するに先立ち、絶縁膜１８ａに、必要に応じて、コンタクトホールのための例えば０．３μｍの直径を有する孔２３を形成しておくことができる。この絶縁膜１８ａへの前記孔２３の形成には、フォトリソ・エッチング技術を用いることができる。前記フォトレジスト材料は、前記孔２３内を充填すべく絶縁膜１８ａ上に塗布されることから、ダミー１９′には、前記孔２３を経て前記半導体基板１８上に達するコンタクト部１９ａ′が形成される。
【００４２】
ダミー１９′の形成後、前記ＨＭＤＳＯまたはＴＥＯＳを用いた本発明に係る前記方法により、図５（ｂ）に示されているように、突起部を構成するダミー１９′間を充填すべく該ダミーの高さ寸法にほぼ一致する厚さ寸法まで、絶縁膜層２０が成長される。
この絶縁膜層２０は、前記したとおり、突起部間の凹所に集中的に堆積され、ダミー１９′上には堆積しないことから、この選択的成長により、絶縁膜層２０およびダミー１９′により、図５（ｂ）に示されるとおり、平坦面が規定される。
【００４３】
その後、前記フォトレジスト材料は、発煙硝酸、有機剥離剤あるいは酸素プラズマ等を用いて、除去される。このフォトレジスト材料の除去により、図５（ｃ）に示されているように、ダミー１９′がそのコンタクト部１９ａ′と共に、前記半導体基板１８上から除去され、これらの除去により、絶縁膜層２０には、ダミー１９′およびコンタクト部１９ａ′に対応した空所２４が規定される。
【００４４】
前記フォトレジスト材料の除去後、前記空所２４が例えば硫酸銅溶液を用いたメッキ法により、銅のような導電性材料２５で充填される。この導電性材料２５は、前記コンタクト部１９ａ′に対応する部分を含む前記空所２４を充填すると共に、図５（ｄ）に示されているように、絶縁膜層２０上に約７０００Åの厚さ寸法で堆積される。
【００４５】
前記導電性材料２５の堆積後、絶縁膜層２０上の不要な導電性材料２５が例えばＣＭＰ法により除去され、絶縁膜層２０の表面が露出されることにより、この絶縁膜層２０に埋設された前記配線１９が形成される。
【００４６】
この配線１９を覆うべく、前記したと同様な層間絶縁膜２２が絶縁膜層２０上に形成され、さらに、この層間絶縁膜２２上には、必要に応じて上層配線が施される。
【００４７】
本発明に係る前記方法によれば、フォトレジスト材料からなるダミー１９′間を埋め込む絶縁膜層２０は、真空紫外線光の照射により、室温環境下で成長させることができることから、前記ダミーが高温下に晒されることはなく、このダミー１９′の加熱によるそれ自体の溶融あるいは焦げを防止することができることから、高精度でのダマシン配線の実現が可能となる。
【００４８】
また、絶縁膜層２０は、高い平坦性でもってダミー１９′間に堆積することから、この絶縁膜層２０にエッチングバックのような平坦化処理を施すことなく、絶縁膜層２０で良好な平坦面が得られる。従って、この絶縁膜層２０にエッチングバックのような格別な平坦化処理を施す必要が無くなることから、工程の簡素化を図ることが可能となる。
【００４９】
図６は、本発明に係る前記方法をデュアルダマシンプロセスに利用した例を示す。
図６（ａ）に示されているように、前記半導体基板１８上には、例えば５０００Åの厚さ寸法を有する絶縁膜１８ａが形成され、該絶縁膜上には、例えば３０００Åの厚さ寸法を有する図３に沿って説明したと同様な配線１９が形成されている。この配線１９は、必要に応じて、絶縁膜１８ａに形成されたコンタクトホール２７ａを経て、前記半導体基板１８の所望部分に接続されている。
【００５０】
各配線１９の所望箇所には、図５に沿って説明したダマシンプロセスにおけると同様なフォトレジスト材料へのフォトマスクを用いた選択露光および現像処理により、図６（ｂ）に示されているように、フォトレジスト材料からなる柱部２８′が形成される。フォトレジスト材料からなる各柱部２８′すなわちダミー２８′は、例えば５０００Åの高さ寸法を有し、その上端から下端へ向けて先細りする逆テーパ形状を有する。
【００５１】
前記したダミー２８′の形成後、前記ＨＭＤＳＯまたはＴＥＯＳを用いた本発明に係る前記方法により、図５（ｂ）に沿って説明したとおり、突起部を構成するダミー２８′および前記配線１９間を充填すべく、前記したと同様に、ダミー２８′の高さ位置にほぼ一致する厚さ寸法まで、絶縁膜層２０が成長される。
【００５２】
この絶縁膜層２０は、前記したとおり、前記突起部間の凹所に集中的に堆積され、ダミー２８′上には堆積しないことから、この選択的成長により、絶縁膜層２０およびダミー２８′により、図６（ｃ）に示されるとおり、平坦面が規定される。
【００５３】
さらに、絶縁膜層２０上には、前記したと同様なリソグラフィ技術により、図６（ｄ）に示されているように、ダミー２８′上を通りかつ前記配線１９に平行に伸びるフォトレジスト材料からなる突起部、すなわち、上方配線のためのダミー２９′が形成される。ダミー２９′は、例えば５０００Åの厚さ寸法を有する。ダミー２９′の形成前に、ダミー２８′の上面に付着するシリカ膜の除去のために、フッ素系プラズマあるいは希フッ酸を用いてダミー２８′の上面を浄化することが望ましい。
【００５４】
上方配線のためのダミー２９′の形成後、本発明に係る前記方法により、図７（ａ）に示されているように、前記絶縁膜層２０上でダミー２９′間を充填すべく絶縁膜層２０と同様な絶縁膜層３０が成長される。
【００５５】
この新たな絶縁膜層３０は、柱部であるダミー２９′の上面にほぼ一致するまで成長され、その後、図５（ｃ）に沿って説明したと同様な方法により、ダミー２８′およびダミー２９′が除去されることにより、図７（ｂ）に示されているように、絶縁膜層２０および３０内には、図６前記配線１９に開放するスルーホールおよび上方配線のための溝を規定する空所３１が規定される。
【００５６】
フォトレジスト材料からなるダミー２８′およびダミー２９′の除去後、前記空所３１が前記した硫酸銅溶液を用いたメッキ法により、銅のような導電性材料３２で充填される。この導電性材料３２は、前記柱部２９ａ′に対応する部分を含む前記空所３１を充填すると共に、図７（ｃ）に示されているように、絶縁膜層３０上に約７０００Åの厚さ寸法で堆積される。
【００５７】
前記導電性材料３２の堆積後、絶縁膜層３０上の不要な導電性材料２５が例えばＣＭＰ法により除去され、絶縁膜層３０の表面が露出される。これにより、この絶縁膜層３０および絶縁膜層２０下に、前記導電性材料２５で形成される上層配線２９および該上層配線を下層配線１９に接続するコンタクト部２８を有する２重配線構造がダマシン法により形成される。
【００５８】
前記２重配線構造を覆うべく、前記したと同様な層間絶縁膜２２が絶縁膜層３０上に形成される。
【００５９】
本発明に係る前記方法によれば、フォトレジスト材料からなるダミー２８′および２９′間を埋め込む絶縁膜層２０および３０は、真空紫外線光の照射により、室温環境下で成長させることができることから、前記ダミーが高温下に晒されることはなく、このダミー２８′および２９′の加熱によるそれ自体の溶融あるいは焦げを防止することができることから、高精度でのデュアルダマシン配線の実現が可能となる。
【００６０】
また、各絶縁膜層２０および３０は、高い平坦性でもってダミー２８′および２９′間に堆積することから、これら絶縁膜層２０および３０にエッチングバックのような処理を施すことなく、これら絶縁膜により良好な平坦面が得られる。従って、この絶縁膜層２０および３０へのエッチングバックのような平坦化処理が不要になることから、工程の簡素化を図ることが可能となる。
【００６１】
図８は、本発明に係る前記方法をＦＥＴ（電界効果型トランジスタ）の１つであるＭＯＳトランジスタのゲート形成プロセスに適用した例を示す。
前記半導体基板１８には、図８に示されているように、例えば従来よく知られたＬＯＣＯＳ法によりフィールド酸化膜３１が形成される。前記半導体基板１８のフィールド酸化膜３１により区画された活性領域には、例えば熱酸化法により、二酸化シリコンからなるゲート酸化膜３２が形成される。
【００６２】
前記ゲート酸化膜３２上には、ゲートのためのダミー３３′が前記したと同様なリソグラフィ技術を用いて有機成分を含む感光性のフォトレジスト材料で形成される。このゲートのためのダミー３３′は、例えば３０００Åの厚さ寸法を有し、０．１８μｍの幅寸法を有する。
【００６３】
各フィールド酸化膜３１上にダミー３３′を形成した後、前記ＨＭＤＳＯまたはＴＥＯＳを用いた本発明に係る前記方法により、図８に示されているように、前記したと同様に、突起部を構成するダミー３３′が形成された前記ゲート酸化膜３２上にダミー３３′の高さにほぼ一致する厚さ寸法である３０００Åの厚さ寸法まで、絶縁膜層２０が成長される。
この絶縁膜層２０は、前記したとおり、突起部であるダミー３３′上には堆積しないことから、この選択的成長により、絶縁膜層２０およびダミー３３′により、平坦面が規定される。
【００６４】
その後、前記フォトレジスト材料から成るダミー３３′は、前記した例におけると同様な発煙硝酸、有機剥離剤あるいは酸素プラズマ等を用いて除去される。このフォトレジスト材料の除去によって形成される凹所には、例えばＬＰＣＶＤ法を用いて、ゲート３３（図９参照）のためのポリシリコンのような導電性材料が充填され、例えばＣＭＰにより絶縁膜層２０上に堆積する不要な前記導電性材料が除去される。
【００６５】
その後、前記層間絶縁膜２２のゲート３３を取り巻く部分と、ゲート酸化膜３２のゲート３３から露出する不要な部分とが除去され、これによりＭＯＳトランジスタのためのゲート３３が形成される。
【００６６】
この絶縁膜層２０上の前記した不要な導電性材料を除去することに代えて、絶縁膜層２０に堆積する前記導電性材料に、フォトリソエッチング技術によるパターニングを施すことにより、絶縁膜層２０上の前記導電性材料で配線パターンを形成することができる。
【００６７】
本発明に係る前記方法をゲートの形成に適用することにより、フォトレジスト材料からなるダミー３３′を埋め込む絶縁膜層２０は、真空紫外線光の照射により、室温環境下で成長させることができることから、前記ダミーが高温下に晒されることはなく、このダミー３３′の加熱による溶融あるいは焦げを防止することができることから、高精度でゲートを形成することができる。
【００６８】
また、前記したと同様に、ダミー３３′を埋め込む絶縁膜層２０により良好な平坦面が得られることから、この絶縁膜層２０にエッチングバックのような格別な平坦化処理が不要になることから、工程の簡素化を図ることが可能となる。
【００６９】
図９は、本発明に係る前記方法をＭＯＳトランジスタのゲート形成に引き続くコンタクトホールの形成プロセスに適用した例を示す。
【００７０】
図８に沿って説明したゲート３３の形成後、図９に示されているように、例えばイオン注入法による前記半導体基板１８への不純物注入により、ゲート３３の両側にソース・ドレイン領域３４が形成される。
【００７１】
ソース・ドレイン領域３４の形成後、該各領域には、これから立ち上がるコンタクト部のためのダミー２８′が前記したと同様なリソグラフィ技術を用いて有機成分を含む感光性のフォトレジスト材料で形成される。このコンタクト部のためのダミー２８′は、例えば５０００Åの高さ寸法を有し、０．５μｍの直径を有する。
【００７２】
各ソース・ドレイン領域３４上にダミー２８′を形成した後、前記したように、前記ＨＭＤＳＯまたはＴＥＯＳを用いた本発明に係る前記方法により、図９に示されているように、突起部を構成するダミー２８′が形成された前記半導体基板１８上にダミー２８′の高さにほぼ一致する厚さ寸法まで、絶縁膜層２０が成長される。
この絶縁膜層２０は、前記したとおり、突起部であるダミー２８′上には堆積しないことから、この選択的成長により、絶縁膜層２０およびダミー２８′により、平坦面が規定される。
【００７３】
その後、前記フォトレジスト材料から成るダミー２８′は、前記した例におけると同様に、除去され、このフォトレジスト材料の除去によって形成される凹所には、例えばＬＰＣＶＤ法を用いて、コンタクト部のためのポリシリコン、Ａｌ−Ｓｉ−Ｃｕ合金あるいは銅のような導電性材料が充填され、例えばＣＭＰにより絶縁膜層２０上に堆積する不要な前記導電性材料が除去されることにより、各ソース・ドレイン領域３４に至るコンタクト部が形成される。
【００７４】
その後、前記層間絶縁膜２２上に堆積する前記導電性材料の不要な部分が除去されるが、前記したとおり、絶縁膜層２０に堆積する前記導電性材料にパターニングを施すことにより、絶縁膜層２０上の前記導電性材料で配線パターンを形成することができる。
【００７５】
本発明に係る前記方法をコンタクトホールの形成に適用することにより、フォトレジスト材料からなるダミー２８′を埋め込む絶縁膜層２０は、真空紫外線光の照射により、室温環境下で成長させることができることから、前記ダミーが高温下に晒されることはなく、このダミー２８′の加熱によるそれ自体の溶融あるいは焦げを防止することができることから、高精度でコンタクトホールを形成することができる。
【００７６】
また、ダミー２８′を埋め込む絶縁膜層２０は、前記したと同様な良好な平坦性を示すことから、この絶縁膜をダミー２８′の高さ位置まで適正に成長させることにより、良好な平坦面が得られる。従って、この絶縁膜層２０にエッチングバックのような格別な平坦化処理が不要になることから、工程の簡素化を図ることが可能となる。
【００７７】
図１０は、本発明をＤＲＡＭのようなメモリセルのキャパシタの形成プロセスに適用した例を示す。
図１０に示すように、前記半導体基板１８には、フィールド酸化膜３１により規定された活性領域が形成され、該活性領域には、前記したと同様なゲート３３が形成され、その後、ソース・ドレイン領域３４が形成される。これらゲート３３およびソース・ドレイン領域３４を備えるＭＯＳトランジスタの形成後、該トランジスタをスイッチング素子とするキャパシタが形成される。
【００７８】
このキャパシタの形成に先立ち、図１０に示されているように、一方のソース・ドレイン領域３４上に、該領域から立ち上がるコンタクト部のためのダミー３５ａ′が、前記したと同様なリソグラフィ技術を用いて、有機成分を含む感光性のフォトレジスト材料で形成される。このコンタクト部のためのダミー３５ａ′は、例えば５０００Åの高さ寸法を有し、０．１８μｍの直径を有する。
【００７９】
このダミー３５ａ′の形成後、前記ＨＭＤＳＯまたはＴＥＯＳを用いた本発明に係る前記方法により、前記したと同様に、突起部であるダミー３５ａ′の高さにほぼ一致する厚さ寸法まで、絶縁膜層２０ａが成長される。
絶縁膜層２０ａは、前記したとおり、突起部であるダミー３５ａ′上には堆積しないことから、この選択的成長により、絶縁膜層２０ａおよびダミー３５ａ′により、平坦面が規定される。
【００８０】
続いて、ダミー３５ａ′上には、該ダミーの直径のほぼ２倍の値を有する例えば０．３μｍの直径を有し、また例えば２０００Åの高さ寸法を有する増径部からなるダミー３５ｂ′が、有機成分を含む感光性のフォトレジスト材料へのリソグラフィ技術により形成される。
【００８１】
ダミー３５ａ′の上面は、ダミー３５ｂ′の形成に先立ち、該ダミーの上面に付着するシリカ膜の除去のために、フッ素系プラズマあるいは希フッ酸を用いてダミー３５ｂ′の上面を浄化することが望ましい。
【００８２】
コンタクト部を規定するダミー３５ａ′および増径部を規定するダミー３５ｂ′の形成後、該増径部を埋め込むべく、再び、本発明に係る前記方法により、前記したと同様に、絶縁膜層２０ａ上には、ダミー３５ｂ′の高さにほぼ一致する厚さ寸法まで、新たな絶縁膜層２０ｂが堆積される。
【００８３】
さらに、前記したと同様な工程により、ダミー３５ａ′とほぼ同一の直径を有し約２０００Åの高さ寸法を有す減径部を規定するフォトレジスト材料からなるダミー３５ｃ′が増径部であるダミー３５ａ′上に形成される。
【００８４】
これら増径部を規定するダミー３５ｂ′、３５ｄ′および３５ｆ′と、減径部を規定するダミー３５ｃ′および３５ｅ′とが、前記したと同様な工程の繰り返しにより、交互に形成され、またそれに応じて、順次、絶縁膜層２０ａ上に、各増径部３５ｂ′、３５ｄ′、３５ｆおよび減径部３５ｃ′、３５ｅ′を埋設する新たな絶縁膜層２０ｂ、２０ｃ、２０ｄ、２０ｅおよび２０ｆが堆積される。
【００８５】
それぞれが前記フォトレジスト材料からなる前記ダミー３５ａ′〜３５ｆ′を埋設する絶縁膜層２０ａ〜２０ｆの形成後、フォトレジスト材料から成るダミー３５ａ′〜３５ｆ′は、前記した例におけると同様な発煙硝酸、有機剥離剤あるいは酸素プラズマ等を用いて除去される。このフォトレジスト材料の除去によって形成される凹所には、前記した例におけると同様に、例えばＬＰＣＶＤ法を用いて、前記したと同様な導電性材料が充填され、例えばＣＭＰにより絶縁膜層２０ｆ上に堆積する不要な前記導電性材料が除去される。
【００８６】
その後、前記絶縁膜層２０ｂ、２０ｃ、２０ｄおよび２０ｅが例えば希フッ酸を用いて除去され、これにより、前記ダミー３５ｂ′、３５ｃ′、３５ｄ′、３５ｅ′および３５ｆ′に対応する多数のフィン部を備える導電性材料から成る一方の電極が露出する。この露出する電極の表面には、例えばＬＰＣＶＤ法より、例えば１００Åの厚さ寸法を有するシリコン窒化膜のような高誘電体膜が形成され、さらに、該高誘電体膜を覆うように、例えばＬＰＣＶＤ法により、ポリシリコンから成る他方の電極が形成される。
【００８７】
本発明に係る前記方法を前記したようなメモリセルの電極の形成に適用することにより、フォトレジスト材料からなる前記ダミー３５ａ′〜３５ｆ′を埋め込む絶縁膜層２０ａ〜２０ｆは、真空紫外線光の照射により、室温環境下で成長させることができることから、前記ダミーが高温下に晒されることはなく、このダミー３５ａ′〜３５ｆ′の加熱によるそれ自体の溶融あるいは焦げを防止することができることから、前記ダミー３５ａ′〜３５ｆ′に対応して、キャパシタの前記一方の電極を高精度で形成することができる。
【００８８】
また、前記したと同様に、前記ダミー３５ａ′〜３５ｆ′を順次埋め込む絶縁膜層２０ａ〜２０ｆにより良好な平坦性が得られることから、これら各絶縁膜層２０ａ〜２０ｆへのエッチングバックのような格別な平坦化処理が不要になることから、工程の簡素化を図ることが可能となる。
【００８９】
【発明の効果】
本発明によれば、前記したように、減圧ＣＶＤ装置の反応室内の半導体基板上に真空紫外光を照射した状態で、前記反応室内に原料ガスとして、ＨＭＤＳＯ（ヘキサメチルジシロキサン）を供給しかつ添加ガスとして酸素を供給することにより、層間絶縁膜として有利な低誘電率を示す良質な絶縁膜層を形成することができる。
【００９０】
また、前記した成長条件では、前記半導体基板上に、たとえば前記フォトレジスト材料または導電性材料で突起部を予め形成しておくことにより、この突起部を除く領域である凹所領域に前記絶縁膜層を選択的に成長させることができることから、本発明の前記方法は、半導体装置の層間絶縁膜、ゲート、ダマシン配線、メモリキャパシタの電極等、半導体装置の種々の製造工程に適用することができる。
【００９１】
さらに、前記凹所領域への選択的な成長については、原料ガスとして、前記ＨＭＤＳＯに代えて、ＴＥＯＳ（テトラエトキシオルソシリケイト）を用いても、前記凹所領域を良好な平坦特性を示す絶縁膜層で埋設することができ、これにより、前記ＨＭＤＳＯを用いた場合におけると同様に、良質でありかつ平坦化特性に優れた絶縁膜層を形成することができる。
【図面の簡単な説明】
【図１】本発明に係る製造方法を実施するＣＶＤ装置を概略的に示す断面図である。
【図２】原料ガスとしてＨＭＤＳＯを用いて形成された本発明に係る絶縁膜層についてのＦＴＩＲ分析結果（１）を示すグラフである。
【図３】本発明に係る製造方法を層間絶縁膜の形成に適用した例を示す工程図である。
【図４】原料ガスとしてＴＥＯＳを用いて形成された本発明に係る絶縁膜層についてのＦＴＩＲ分析結果（２）を示すグラフである。
【図５】本発明に係る製造方法を配線のためのダマシンプロセスに適用した例を示す工程図である。
【図６】本発明に係る製造方法を二層配線のためのデュアルダマシンプロセスに適用した例を示す工程図（その１）である。
【図７】本発明に係る製造方法を二層配線のためのデュアルダマシンプロセスに適用した例を示す工程図（その２）である。
【図８】本発明に係る製造方法をＦＥＴのゲートの形成プロセスに適用した例を示す断面図である。
【図９】本発明に係る製造方法をＦＥＴのコンタクトホールの形成プロセスに適用した例を示す断面図である。
【図１０】本発明に係る製造方法をメモリセルのキャパシタ電極の形成プロセスに適用した例を示す断面図である。
【符号の説明】
１０ 減圧ＣＶＤ装置
１１ 反応室
１７ 真空紫外光源
１８ 半導体基板[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a manufacturing method suitable for manufacturing a semiconductor device such as a MOSFET, and in particular, manufacturing an insulating film layer applicable to formation of an interlayer insulating film, wiring by a damascene method, a gate of an FET or an electrode of a memory capacitor. Regarding the method.
[0002]
[Prior art]
One technique for increasing the degree of integration of a semiconductor device composed of an assembly of semiconductor elements such as MOSFETs collectively formed on a semiconductor substrate is a multilayer wiring structure. A technique for forming an insulating film layer having excellent flatness for embedding a semiconductor element on a semiconductor substrate is extremely important in realizing this multilayer wiring structure by a photolithography etching method.
[0003]
The inventors of the present application were formed on a semiconductor substrate as shown in pages 84 and 85 of the proceedings at the IEICE General Conference held in Japan on March 31, 2000. A method of forming an insulating film layer on the insulating film by using a low pressure CVD method was proposed.
[0004]
According to this method for forming an insulating film layer, TEOS is supplied as a source gas and oxygen gas is supplied as an additive gas to a reaction chamber of a low-pressure CVD apparatus in which a semiconductor substrate on which the insulating film layer is to be grown is disposed. A good insulating film layer can be formed by growing the insulating film layer in a state in which vacuum ultraviolet light is irradiated on the insulating film of the semiconductor substrate.
[0005]
[Problems to be solved by the invention]
It is an object of the present invention to provide a novel method that is suitable and useful for manufacturing a semiconductor device, including a novel method capable of forming a higher-quality insulating film layer.
Another object of the present invention is to provide a novel method capable of forming an insulating film layer having excellent planarization characteristics by suitably filling a recess defined by a protrusion on a semiconductor substrate. is there.
Furthermore, another object of the present invention is to provide a novel method for manufacturing a semiconductor device, which is suitable for application to formation of an interlayer insulating film, wiring by damascene method, gate of FET or electrode of memory capacitor, and the like. There is.
[0006]
[Means for Solving the Problems]
The present invention forms an insulating film layer in a selected region on a semiconductor substrate by using a low pressure CVD method. Process In a method for manufacturing a semiconductor device containing hexamethyldisiloxane ((CH Three ) Three SiOSi (CH Three ) Three ).
[0007]
That is, in the method for manufacturing a semiconductor device according to the present invention, an insulating film layer is formed in a selected region on a semiconductor substrate by using a low pressure CVD method. Process A method of manufacturing a semiconductor device comprising: forming the insulating film layer Process Supplying a hexamethyldisiloxane as a source gas and oxygen as an additive gas to a reaction chamber of a low-pressure CVD apparatus in which the semiconductor substrate on which the insulating film layer is to be grown is disposed, and on the semiconductor substrate The insulating film layer is grown while being irradiated with vacuum ultraviolet light.
[0008]
According to the manufacturing method of the present invention, a high-quality insulating film layer having a low dielectric constant, which is a desirable characteristic as an interlayer insulating film, is selectively grown, for example, so as to embed a protrusion formed on the substrate. Can be made.
[0009]
The protrusion can be formed of a photoresist material or a conductive material containing an organic component, and the insulating film is formed in a region on the semiconductor substrate excluding the protrusion, that is, a recess defined by the protrusion. The layer can be grown selectively.
[0010]
The manufacturing method can be used for forming a conductive portion such as a wiring or a gate. For example, in the formation of wiring by the damascene method, a conductive portion made of a conductive material is formed on the semiconductor substrate, and the CVD method is used for a region excluding the conductive portion in the semiconductor substrate on which the conductive portion is formed. The insulating film layer is grown to a position substantially the same as the conductive portion, and then an insulating material is newly deposited to cover the insulating film layer and the surface of the conductive portion exposed from the insulating film layer. Can do.
[0011]
This new insulating material can be deposited, for example, by using the CVD apparatus and supplying hexamethyldisiloxane to the reaction chamber under irradiation of the vacuum ultraviolet light while the supply of oxygen is cut off. . Alternatively, the above-described new insulating material can be deposited using various conventional deposition methods.
[0012]
In the formation of a conductive portion such as a gate, a protrusion having a shape corresponding to a desired gate can be formed on the insulating film formed on the semiconductor substrate with a photoresist material containing an organic component. The insulating film layer is grown to a position substantially the same as the conductive portion using the CVD method in a region excluding the protrusion in the insulating film of the semiconductor substrate on which the protrusion is formed, and then The protrusions made of the photoresist material are removed. By removing the protrusions, the recesses defined by the insulating film layer are filled with a conductive material for the conductive part, whereby a conductive part such as a gate can be formed. In the formation of the gate, the insulating film is a gate oxide film.
[0013]
The method according to the present invention can be applied to a dual damascene method for multilayer wiring.
That is, a conductive portion which is a lower layer wiring made of a conductive material is formed on the semiconductor substrate, a pillar portion made of the photoresist material is formed on the conductive portion, and the semiconductor substrate on which the pillar portion is formed is formed. An insulating film layer is grown in a region excluding the column portion up to almost the same height as the column portion using the CVD method. Thereafter, a protrusion made of the photoresist material is formed for the upper layer wiring extending from the top surface of the pillar portion to the insulating film layer, and in a region exposed from the protrusion on the insulating film layer, The insulating film layer is newly grown up to almost the same height position as the protrusion using the CVD method.
Thereafter, the protrusions and the pillars made of the photoresist material are removed, and the recesses defined by the two insulating film layers are embedded with a conductive material by removing the protrusions and the pillars, thereby allowing the damascene A multilayer wiring using the method can be realized relatively easily.
[0014]
The method according to the present invention can be applied to the manufacture of a field effect transistor, and can be applied, for example, to the formation of a conductive portion extending to the source / drain.
[0015]
The method according to the present invention can be applied to the manufacture of a capacitor of each memory cell of a DRAM (Dynamic Random Access Memory), for example, and can be applied to the formation of one electrode of the capacitor, for example. Can do.
[0016]
When the insulating film layer is selectively formed in the recess defined by the protrusion on the semiconductor substrate by using the low pressure CVD method, tetraethoxy orthosilicate (Si ( OC 2 H Five ) Four ), The insulating film layer can be selectively and satisfactorily grown on the semiconductor substrate in the recess defined by the protrusion formed by the photoresist material or the conductive material containing an organic component. It has been newly found that it can be done.
[0017]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, the present invention will be described in detail with reference to the illustrated embodiments.
<Concrete example>
FIG. 1 schematically shows a low pressure CVD apparatus for carrying out the manufacturing method according to the present invention. The low pressure CVD apparatus 10 is used for forming an insulating film layer such as a silicon oxide film in a manufacturing process of a semiconductor device such as a MOS transistor.
[0018]
As shown in FIG. 1, the low-pressure CVD apparatus 10 has a cylindrical housing 12 for defining the reaction chamber 11 as a whole, and one end of the housing 12 for maintaining the inside of the reaction chamber 11 in a reduced pressure state. A negative pressure source 14 such as a vacuum pump connected via a pipe 13, a susceptor 16 holding a semiconductor wafer 15 made of silicon, for example, in the reaction chamber 11, and a vacuum ultraviolet light source such as a Xe excimer lamp, for example. 17. As the vacuum ultraviolet light source 17, a light source that emits ultraviolet light in a so-called vacuum ultraviolet region having a wavelength shorter than about 200 nm can be appropriately selected.
[0019]
The semiconductor wafer 15 is held on the susceptor 16 with the silicon oxide film 15a formed on the surface thereof facing upward, and the temperature of the semiconductor wafer 15 is between room temperature and 350 ° C. by adjusting the temperature with the susceptor. Can be adjusted.
The vacuum ultraviolet light source 17 is supported by the housing 12 such that a quartz window 17a serving as an irradiation window on which a synthetic quartz plate having a thickness of 20 mm is mounted is positioned above the semiconductor wafer 15, and the quartz window Through 17a, vacuum ultraviolet light is irradiated toward the silicon oxide film 15a of the semiconductor wafer 15.
[0020]
In the manufacturing method according to the present invention, hexamethyldisiloxane ((CH) is used as a source gas supplied into the reaction chamber 11 to grow an insulating film layer on the silicon oxide film 15a of the semiconductor wafer 15. Three ) Three SiOSi (CH Three ) Three : Hereinafter, simply referred to as HMDSO. ) And oxygen (O 2 ) Is used.
[0021]
With the distance between the semiconductor wafer 15 held at room temperature on the susceptor 16 and the quartz window 17a of the vacuum ultraviolet light source 17 kept at, for example, about 15 mm, the illuminance of the vacuum ultraviolet light is 10 mW / s directly below the quartz window 17a. cm 2 Thus, the semiconductor wafer 15 is irradiated with vacuum ultraviolet rays. Under this environment, the HMDSO is supplied into the reaction chamber 11 at, for example, 50 sccm and the oxygen at the same flow rate as that of HMDSO. At this time, the reaction pressure in the reaction chamber 11 was 600 mTorr.
In order to prevent fogging of the quartz window due to growth of an insulating film layer to be described later on the quartz window 17a, it is desirable to heat the quartz window 17a at a temperature exceeding the temperature of the vacuum ultraviolet ray source.
[0022]
By operating the low-pressure CVD apparatus 10 for about 10 minutes under the above-described conditions, an insulating film layer mainly composed of about 5000 kg of silicon dioxide was grown on the silicon oxide film 15a of the semiconductor wafer 15.
[0023]
FIG. 2 is a graph showing the results of analyzing the components of the insulating film layer using Fourier transform infrared spectroscopy.
The horizontal axis of the graph represents the reciprocal of the wavelength of infrared light irradiated on the insulating film layer as a sample, that is, the wave number (cm -1 The vertical axis represents the absorbance (arbitrary unit).
According to the Fourier transform infrared spectroscopy, when the wavelength of the infrared light irradiated on the sample is continuously shifted, the infrared light of each wavelength corresponding to the irradiated material is absorbed with a high absorption rate. Is done. Therefore, the component of the substance can be known by obtaining the wave number at which the absorptance increases rapidly.
[0024]
According to the analysis result shown in FIG. 2, in addition to silicon dioxide as a main component, as shown in the graph, Si 2 O, SiOH and SiCH Three Is formed. All of these exhibit electrical insulation, and in particular, SiCH Three Is an organic substance and exhibits a lower dielectric constant than silicon dioxide, which is the main component, and thus provides excellent electrical characteristics as an interlayer insulating film of a semiconductor device.
Moreover, since the insulating film layer formed by the method according to the present invention is excellent in flatness, it is advantageous for a photolithography etching technique on the insulating film layer, and is applied to various manufacturing processes of a semiconductor device. be able to.
[0025]
FIG. 3 shows an example in which the manufacturing method according to the present invention is used for manufacturing an interlayer insulating film of a semiconductor device.
In the manufacturing process of a semiconductor device such as a MOS transistor, for example, a plurality of wirings 19 are formed on, for example, a silicon semiconductor substrate 18 as shown in FIG. Circuit elements (not shown) such as MOS transistors are formed on the semiconductor substrate 18. For these circuit elements on the semiconductor substrate 18, the wiring 19 is formed of a silicon oxide film on the semiconductor substrate 18. For example, it is formed on the insulating film 18a having a thickness of 5000 mm.
[0026]
As is well known in the art, the wiring 19 is made of a metal material such as tungsten or Al—Si—Cu alloy, and each wiring 19 has a height dimension of 0.5 μm and a width of 0.3 μm, for example. Each wiring 19 extends in parallel to each other at an interval of, for example, 0.5 μm in the width direction.
[0027]
The semiconductor substrate 18 on which the wiring 19 is formed is disposed on the susceptor 16 of the low-pressure CVD apparatus 10 shown in FIG. 1 so that the wiring 19 faces upward, and the above-described insulation is performed under the same growth conditions as described above. By growing the film layer, as shown in FIG. 3B, in the region exposed from the wiring 19 on the insulating film 18a, silicon dioxide as a main component is SiCH. Three Insulating film layer 20 similar to that shown in the graph of FIG.
[0028]
Since the insulating film layer 20 is intensively deposited in the recesses 21 defined between the wirings except for the wiring 19 that forms the protrusions on the insulating film 18a, the insulating film layer 20 is formed on the insulating film 18a. Grow selectively. The insulating film layer 20 grows for about 10 minutes until the top surface of the insulating film layer 20 coincides with that of the wiring 19 as shown in FIG.
[0029]
Since the insulating film layer 20 exhibits extremely high flat characteristics, a flat surface is defined by the wiring 19 and the insulating film layer 20 filling between the wirings. Therefore, a new insulating material (e.g., a thickness of 3000 mm) is simply applied to the insulating film layer 20 without performing the etching back process for obtaining the flat surface by chemical mechanical polishing (CMP) or plasma dry etching process. By depositing 22), as shown in FIG. 3C, the interlayer insulating film 22 having a flat surface so as to cover the wiring 19 as a protrusion and the insulating film layer 20 buried between the wiring 19 is covered. Can be formed.
[0030]
In order to deposit a new insulating material (22), the supply of oxygen can be stopped under the irradiation of the vacuum ultraviolet light in the low-pressure CVD apparatus 10, and only the HMDSO can be supplied. An interlayer insulating film 22 can be formed.
Alternatively, for the formation of the interlayer insulating film 22, conventionally well-known plasma enhanced CVD (PECVD), low pressure CVD (LPCVD), or atmospheric pressure CVD (APCVD) can be used as appropriate. .
[0031]
When the distance between the protrusions 19 was in the range of 0.3 to 0.7 μm, a good filling effect of the recess 21 by the insulating film layer 20 was recognized.
[0032]
As described above, according to the method of the present invention, the recess 21 defined by the protrusion 19 formed on the insulating film 18 a of the semiconductor substrate 18 is appropriately filled with the insulating film layer 20. As a result, the flat interlayer insulating film 22 can be grown without the need for an etching back process, so that the manufacturing process of the semiconductor device can be simplified and the production cost can be reduced.
[0033]
The phenomenon in which the inside of the recess 21 defined by the protrusion 19 formed on the insulating film 18a of the semiconductor substrate 18 can be appropriately filled with the same insulating film layer as described above is shown in FIG. In the method using the low pressure CVD apparatus 10, tetraethoxy orthosilicate (Si (OC 2 H Five ) Four : Hereinafter, simply referred to as TEOS. ) Was confirmed to occur even when using.
[0034]
In the manufacturing method using this TEOS as a raw material gas for the low pressure CVD apparatus 10 provided with the vacuum ultraviolet light source 17, the reaction chamber has the TEOS of 50 sccm, for example, and the oxygen has the same flow rate as that of TEOS. 11 is supplied. The reaction pressure in the reaction chamber 11 at this time was 600 mTorr as in HMDSO. Further, the illuminance of the vacuum ultraviolet light from the vacuum ultraviolet light source 17 is 10 mW / cm just below the quartz window 17a. 2 Met.
[0035]
In this example using TEOS, the distance between the semiconductor wafer 15 held on the susceptor 16 and the quartz window 17a of the vacuum ultraviolet light source 17 is kept at about 100 mm, and the temperature just below the quartz window 17a is kept at 200.degree. As a result, the quartz window 17a is heated.
[0036]
Under the growth conditions using TEOS, the insulating film 18a is formed within the recess 21 defined by the protrusion 19 on the insulating film 18a of the semiconductor substrate 18 similar to that shown in FIG. In addition, an insulating film layer mainly composed of silicon dioxide having a thickness of about 5000 mm was intensively deposited.
By the selective growth of the insulating film layer, a flat surface defined by the insulating film layer 20 filled between the protrusion 19 and the recess 21 is formed as shown in FIG. By forming the same interlayer insulating film 22 as described above on the flat surface, the flat interlayer insulating film 22 could be formed without etching back.
[0037]
FIG. 4 is a graph similar to FIG. 2 showing the analysis results of the components of the insulating film layer 20 formed by the method using TEOS as the source gas.
According to the graph shown in FIG. 4, silicon dioxide (Si 2 In addition to O), organic SiOCH exhibiting a lower dielectric constant than this 2 Therefore, the insulating film layer 20 according to the present invention formed using TEOS as a raw material gas provides excellent electrical characteristics as an interlayer insulating film of a semiconductor device. In addition, the insulating film layer 20 according to the present invention formed using TEOS as a source gas has excellent flatness and the above-described selective growth as in the insulating film layer 20 according to the present invention formed using HMDSO as a source gas. Due to the characteristics, the recess 21 defined by the protrusion 19 can be appropriately embedded.
[0038]
The method using HMDSO and TEOS can be used for various semiconductor manufacturing processes using the selective growth characteristics described above.
[0039]
FIG. 5 shows an example in which the method according to the present invention is used in a damascene process.
As shown in FIG. 5A, an insulating film 18a is formed on the semiconductor substrate 18, and the insulating film 18a is formed on the insulating film, for example, from a photoresist material containing an organic component. A plurality of dummy 19 'is formed. Each dummy 19 ′ has a width dimension of 0.5 μm and a height dimension of 0.5 μm, for example, and extends parallel to each other with an interval of 0.1 μm, for example.
[0040]
In order to form this dummy 19 ', a photosensitive photoresist material having a photosensitivity is applied on the insulating film 18a to a substantially uniform thickness as in the conventional photoresist pattern formation. The photoresist layer formed by applying the photoresist material is selectively exposed using a desired photomask, and then developed. A dummy 19 'having a desired shape is formed by a lithography technique including selective exposure and development processing on a photoresist material using the photomask. As the photoresist for the dummy 19 ', either a positive type or a negative type can be selected as necessary.
[0041]
Prior to applying the photoresist material on the insulating film 18a, a hole 23 having a diameter of, for example, 0.3 μm for a contact hole can be formed in the insulating film 18a as needed. Photolitho etching technique can be used to form the hole 23 in the insulating film 18a. Since the photoresist material is applied onto the insulating film 18a so as to fill the hole 23, a contact portion 19a 'reaching the semiconductor substrate 18 through the hole 23 is formed on the dummy 19'. The
[0042]
After the formation of the dummy 19 ′, the dummy 19 ′ is formed so as to fill the space between the dummy 19 ′ constituting the protrusion as shown in FIG. 5B by the method according to the present invention using the HMDSO or TEOS. The insulating film layer 20 is grown up to a thickness dimension substantially corresponding to the height dimension.
As described above, the insulating film layer 20 is concentrated in the recesses between the protrusions and does not deposit on the dummy 19 ′. Therefore, by this selective growth, the insulating film layer 20 is formed by the insulating film layer 20 and the dummy 19 ′. As shown in FIG. 5B, a flat surface is defined.
[0043]
Thereafter, the photoresist material is removed using fuming nitric acid, an organic stripper, oxygen plasma, or the like. By removing the photoresist material, as shown in FIG. 5C, the dummy 19 ′ is removed from the semiconductor substrate 18 together with the contact portion 19a ′, and by removing these, the insulating film layer 20 is removed. The space 24 corresponding to the dummy 19 'and the contact portion 19a' is defined.
[0044]
After removal of the photoresist material, the void 24 is filled with a conductive material 25 such as copper, for example, by plating using a copper sulfate solution. The conductive material 25 fills the void 24 including a portion corresponding to the contact portion 19a ′, and has a thickness of about 7000 mm on the insulating film layer 20 as shown in FIG. 5 (d). It is deposited with the size.
[0045]
After the conductive material 25 is deposited, unnecessary conductive material 25 on the insulating film layer 20 is removed by, for example, a CMP method, and the surface of the insulating film layer 20 is exposed to be embedded in the insulating film layer 20. The wiring 19 is formed.
[0046]
An interlayer insulating film 22 similar to that described above is formed on the insulating film layer 20 to cover the wiring 19, and an upper layer wiring is provided on the interlayer insulating film 22 as necessary.
[0047]
According to the method of the present invention, the insulating film layer 20 embedded between the dummy 19 'made of a photoresist material can be grown in a room temperature environment by irradiation with vacuum ultraviolet light. Since the dummy 19 'can be prevented from being melted or burnt by heating, the damascene wiring can be realized with high accuracy.
[0048]
Further, since the insulating film layer 20 is deposited between the dummy 19 'with high flatness, the insulating film layer 20 can be satisfactorily flattened without performing a flattening process such as etching back on the insulating film layer 20. A surface is obtained. Therefore, it is not necessary to perform a special flattening process such as etching back on the insulating film layer 20, so that the process can be simplified.
[0049]
FIG. 6 shows an example in which the method according to the present invention is applied to a dual damascene process.
As shown in FIG. 6A, an insulating film 18a having a thickness of, eg, 5000 mm is formed on the semiconductor substrate 18, and a thickness of, for example, 3000 mm is formed on the insulating film. Wiring 19 similar to that described with reference to FIG. 3 is formed. The wiring 19 is connected to a desired portion of the semiconductor substrate 18 through a contact hole 27a formed in the insulating film 18a as necessary.
[0050]
As shown in FIG. 6B, a desired portion of each wiring 19 is subjected to selective exposure and development processing using a photomask on a photoresist material similar to that in the damascene process described with reference to FIG. In addition, a column portion 28 'made of a photoresist material is formed. Each column portion 28 'made of a photoresist material, that is, a dummy 28' has a height dimension of 5000 mm, for example, and has a reverse taper shape that tapers from the upper end to the lower end.
[0051]
After the formation of the dummy 28 ′, the method according to the present invention using the HMDSO or TEOS is used to connect the dummy 28 ′ constituting the protrusion and the wiring 19 as described with reference to FIG. In order to fill, the insulating film layer 20 is grown up to a thickness dimension substantially coinciding with the height position of the dummy 28 'in the same manner as described above.
[0052]
As described above, the insulating film layer 20 is intensively deposited in the recesses between the protrusions and does not deposit on the dummy 28 '. Therefore, by this selective growth, the insulating film layer 20 and the dummy 28' are deposited. Thus, a flat surface is defined as shown in FIG.
[0053]
Further, on the insulating film layer 20, a photoresist material extending on the dummy 28 ′ and parallel to the wiring 19 as shown in FIG. 6D is formed by the same lithography technique as described above. A projection 29, that is, a dummy 29 'for the upper wiring is formed. The dummy 29 'has a thickness dimension of, for example, 5000 mm. Before the dummy 29 'is formed, it is desirable to purify the upper surface of the dummy 28' using fluorine-based plasma or dilute hydrofluoric acid in order to remove the silica film adhering to the upper surface of the dummy 28 '.
[0054]
After the formation of the dummy 29 'for the upper wiring, the insulating film is formed to fill the space between the dummy 29' on the insulating film layer 20 by the method according to the present invention, as shown in FIG. An insulating film layer 30 similar to the layer 20 is grown.
[0055]
The new insulating film layer 30 is grown until it substantially coincides with the upper surface of the dummy 29 'that is the column portion, and then the dummy 28' and the dummy 29 are formed by the same method as described with reference to FIG. 7 is removed, as shown in FIG. 7B, the through-holes opened in the wiring 19 and the grooves for the upper wiring are defined in the insulating film layers 20 and 30 as shown in FIG. A void 31 is defined.
[0056]
After removing the dummy 28 'and the dummy 29' made of a photoresist material, the void 31 is filled with a conductive material 32 such as copper by the plating method using the copper sulfate solution described above. The conductive material 32 fills the void 31 including a portion corresponding to the pillar portion 29a ′, and has a thickness of about 7000 mm on the insulating film layer 30 as shown in FIG. 7C. It is deposited with the size.
[0057]
After the conductive material 32 is deposited, unnecessary conductive material 25 on the insulating film layer 30 is removed by, for example, CMP, and the surface of the insulating film layer 30 is exposed. Thus, a double wiring structure having an upper layer wiring 29 formed of the conductive material 25 and a contact portion 28 for connecting the upper layer wiring to the lower layer wiring 19 under the insulating film layer 30 and the insulating film layer 20 is a damascene. Formed by law.
[0058]
An interlayer insulating film 22 similar to that described above is formed on the insulating film layer 30 so as to cover the double wiring structure.
[0059]
According to the method of the present invention, the insulating film layers 20 and 30 filling the space between the dummy materials 28 'and 29' made of a photoresist material can be grown in a room temperature environment by irradiation with vacuum ultraviolet light. The dummy is not exposed to a high temperature, and the dummy 28 'and 29' can be prevented from being melted or burnt by heating, so that dual damascene wiring with high accuracy can be realized.
[0060]
Further, since the insulating film layers 20 and 30 are deposited between the dummy 28 'and 29' with high flatness, these insulating film layers 20 and 30 are not subjected to a treatment such as etching back, so that these insulating films 20 and 30 are insulated. A good flat surface is obtained by the film. Accordingly, a planarization process such as etching back to the insulating film layers 20 and 30 is not necessary, and the process can be simplified.
[0061]
FIG. 8 shows an example in which the method according to the present invention is applied to a gate forming process of a MOS transistor which is one of FETs (field effect transistors).
As shown in FIG. 8, a field oxide film 31 is formed on the semiconductor substrate 18 by, for example, a well-known LOCOS method. In the active region partitioned by the field oxide film 31 of the semiconductor substrate 18, a gate oxide film 32 made of silicon dioxide is formed by, eg, thermal oxidation.
[0062]
On the gate oxide film 32, a dummy 33 'for the gate is formed of a photosensitive photoresist material containing an organic component by using the same lithography technique as described above. The dummy 33 'for this gate has a thickness dimension of, for example, 3000 mm and a width dimension of 0.18 μm.
[0063]
After forming a dummy 33 ′ on each field oxide film 31, as shown in FIG. 8, a protrusion is formed by the method according to the present invention using the HMDSO or TEOS as described above. The insulating film layer 20 is grown on the gate oxide film 32 on which the dummy 33 'is formed to a thickness dimension of 3000 mm, which is a thickness dimension substantially corresponding to the height of the dummy 33'.
As described above, since the insulating film layer 20 is not deposited on the dummy 33 ′ that is the protrusion, a flat surface is defined by the insulating film layer 20 and the dummy 33 ′ by this selective growth.
[0064]
Thereafter, the dummy 33 'made of the photoresist material is removed using fuming nitric acid, an organic stripping agent, oxygen plasma or the like as in the above example. The recess formed by the removal of the photoresist material is filled with a conductive material such as polysilicon for the gate 33 (see FIG. 9) using, for example, the LPCVD method. Unnecessary conductive material deposited on 20 is removed.
[0065]
Thereafter, the portion surrounding the gate 33 of the interlayer insulating film 22 and the unnecessary portion exposed from the gate 33 of the gate oxide film 32 are removed, thereby forming the gate 33 for the MOS transistor.
[0066]
Instead of removing the above-described unnecessary conductive material on the insulating film layer 20, the conductive material deposited on the insulating film layer 20 is subjected to patterning by a photolithographic etching technique, so that A wiring pattern can be formed of the conductive material.
[0067]
By applying the method according to the present invention to the formation of the gate, the insulating film layer 20 embedding the dummy 33 ′ made of a photoresist material can be grown in a room temperature environment by irradiation with vacuum ultraviolet light. The dummy is not exposed to a high temperature, and the dummy 33 'can be prevented from being melted or burnt by heating, so that the gate can be formed with high accuracy.
[0068]
Further, as described above, since a good flat surface can be obtained by the insulating film layer 20 in which the dummy 33 ′ is embedded, a special flattening process such as etching back is not required for the insulating film layer 20. It is possible to simplify the process.
[0069]
FIG. 9 shows an example in which the method according to the present invention is applied to a contact hole formation process subsequent to the formation of a gate of a MOS transistor.
[0070]
After the formation of the gate 33 described with reference to FIG. 8, as shown in FIG. 9, source / drain regions 34 are formed on both sides of the gate 33 by, for example, impurity implantation into the semiconductor substrate 18 by ion implantation. Is done.
[0071]
After the formation of the source / drain regions 34, a dummy 28 'for a contact portion that will rise from now on is formed with a photosensitive photoresist material containing an organic component using the same lithography technique as described above. . The dummy 28 'for this contact part has a height dimension of, for example, 5000 mm and a diameter of 0.5 μm.
[0072]
After forming the dummy 28 'on each source / drain region 34, as described above, as shown in FIG. 9, the protrusion is formed by the method according to the present invention using the HMDSO or TEOS. An insulating film layer 20 is grown on the semiconductor substrate 18 on which the dummy 28 'is formed to a thickness that substantially matches the height of the dummy 28'.
As described above, the insulating film layer 20 is not deposited on the dummy 28 ′, which is a protrusion, and therefore, by this selective growth, a flat surface is defined by the insulating film layer 20 and the dummy 28 ′.
[0073]
Thereafter, the dummy 28 'made of the photoresist material is removed in the same manner as in the above-described example, and the recess formed by the removal of the photoresist material is used for the contact portion by using, for example, LPCVD. The conductive material such as polysilicon, Al-Si-Cu alloy or copper is filled, and the unnecessary conductive material deposited on the insulating film layer 20 is removed by CMP, for example. A contact portion reaching the region 34 is formed.
[0074]
Thereafter, unnecessary portions of the conductive material deposited on the interlayer insulating film 22 are removed. As described above, the conductive material deposited on the insulating film layer 20 is patterned to form an insulating film layer. A wiring pattern can be formed with the conductive material on the substrate 20.
[0075]
By applying the method according to the present invention to the formation of contact holes, the insulating film layer 20 embedding the dummy 28 'made of a photoresist material can be grown in a room temperature environment by irradiation with vacuum ultraviolet light. The dummy is not exposed to high temperatures, and the dummy 28 'can be prevented from being melted or burnt by heating, so that a contact hole can be formed with high accuracy.
[0076]
In addition, since the insulating film layer 20 in which the dummy 28 'is embedded exhibits the same flatness as described above, a good flat surface can be obtained by properly growing this insulating film up to the height of the dummy 28'. Is obtained. Therefore, since the insulating film layer 20 does not need a special planarization process such as etching back, the process can be simplified.
[0077]
FIG. 10 shows an example in which the present invention is applied to a process for forming a capacitor of a memory cell such as a DRAM.
As shown in FIG. 10, an active region defined by a field oxide film 31 is formed in the semiconductor substrate 18, and a gate 33 similar to that described above is formed in the active region. Region 34 is formed. After the formation of the MOS transistor including the gate 33 and the source / drain region 34, a capacitor using the transistor as a switching element is formed.
[0078]
Prior to the formation of this capacitor, as shown in FIG. 10, a dummy 35a ′ for a contact portion rising from one source / drain region 34 is formed using the same lithography technique as described above. And a photosensitive photoresist material containing an organic component. The dummy 35a 'for the contact portion has a height dimension of, for example, 5000 mm and a diameter of 0.18 μm.
[0079]
After the formation of the dummy 35a ', the insulating film is formed by the method according to the present invention using the HMDSO or TEOS until the thickness is substantially equal to the height of the dummy 35a' that is the projection, as described above. Layer 20a is grown.
As described above, since the insulating film layer 20a is not deposited on the dummy 35a 'that is the protrusion, this selective growth defines a flat surface by the insulating film layer 20a and the dummy 35a'.
[0080]
Subsequently, on the dummy 35a ', there is a dummy 35b' composed of a diameter-increased portion having a diameter of, for example, 0.3 .mu.m having a value almost twice the diameter of the dummy and having a height of 2000 mm, for example. , By a lithography technique to a photosensitive photoresist material containing an organic component.
[0081]
Prior to the formation of the dummy 35b ', the upper surface of the dummy 35a' can be purified using fluorine plasma or dilute hydrofluoric acid to remove the silica film adhering to the upper surface of the dummy 35b '. desirable.
[0082]
After the formation of the dummy 35a ′ for defining the contact portion and the dummy 35b ′ for defining the increased diameter portion, the insulating film layer 20a is again formed by the method according to the present invention to embed the increased diameter portion in the same manner as described above. On top of this, a new insulating film layer 20b is deposited up to a thickness dimension substantially matching the height of the dummy 35b '.
[0083]
Further, by the same process as described above, a dummy 35c ′ made of a photoresist material that defines a reduced diameter portion having a diameter almost the same as that of the dummy 35a ′ and having a height of about 2000 mm is the increased diameter portion. It is formed on the dummy 35a '.
[0084]
The dummy 35b ', 35d' and 35f 'for defining the increased diameter portion and the dummy 35c' and 35e 'for defining the reduced diameter portion are alternately formed by repeating the same process as described above. Accordingly, new insulating film layers 20b, 20c, 20d, 20e, and 20f are embedded on the insulating film layer 20a in order to embed each of the increased diameter portions 35b ', 35d', 35f and the reduced diameter portions 35c ', 35e'. Is deposited.
[0085]
After the formation of the insulating film layers 20a to 20f for burying the dummy 35a 'to 35f', each of which is made of the photoresist material, the dummy 35a 'to 35f' made of the photoresist material is a fuming nitric acid similar to the above example. It is removed using an organic stripping agent or oxygen plasma. The recess formed by removing the photoresist material is filled with the same conductive material as described above using, for example, the LPCVD method, as in the above example, and is formed on the insulating film layer 20f by CMP, for example. The unnecessary conductive material deposited on the substrate is removed.
[0086]
Thereafter, the insulating film layers 20b, 20c, 20d and 20e are removed using, for example, dilute hydrofluoric acid, so that a large number of fin portions corresponding to the dummy 35b ', 35c', 35d ', 35e' and 35f 'are obtained. One electrode made of a conductive material comprising A high dielectric film such as a silicon nitride film having a thickness of, for example, 100 mm is formed on the surface of the exposed electrode by, for example, LPCVD, and further, for example, LPCVD so as to cover the high dielectric film. The other electrode made of polysilicon is formed by the method.
[0087]
By applying the method according to the present invention to the formation of the electrode of the memory cell as described above, the insulating film layers 20a to 20f embedded with the dummy 35a 'to 35f' made of a photoresist material are irradiated with vacuum ultraviolet light. Therefore, the dummy is not exposed to a high temperature and can be prevented from melting or scorching due to heating of the dummy 35a ′ to 35f ′. Corresponding to the dummy 35a 'to 35f', the one electrode of the capacitor can be formed with high accuracy.
[0088]
Further, as described above, the insulating film layers 20a to 20f that sequentially fill the dummy 35a 'to 35f' can obtain good flatness, and therefore, such as etching back to these insulating film layers 20a to 20f. Since no special planarization process is required, the process can be simplified.
[0089]
【The invention's effect】
According to the present invention, as described above, HMDSO (hexamethyldisiloxane) is supplied as a source gas into the reaction chamber in a state in which vacuum ultraviolet light is irradiated onto the semiconductor substrate in the reaction chamber of the low pressure CVD apparatus; By supplying oxygen as the additive gas, a high-quality insulating film layer exhibiting a low dielectric constant that is advantageous as an interlayer insulating film can be formed.
[0090]
Further, under the above-described growth conditions, a projection is formed in advance on the semiconductor substrate with, for example, the photoresist material or the conductive material, so that the insulating film is formed in a recess region that is a region excluding the projection. Since the layer can be selectively grown, the method of the present invention can be applied to various manufacturing processes of a semiconductor device such as an interlayer insulating film of a semiconductor device, a gate, a damascene wiring, and an electrode of a memory capacitor. .
[0091]
Furthermore, for the selective growth to the recess region, an insulating film showing good flat characteristics in the recess region even when TEOS (tetraethoxyorthosilicate) is used as the source gas instead of the HMDSO. As in the case where the HMDSO is used, an insulating film layer having high quality and excellent planarization characteristics can be formed.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view schematically showing a CVD apparatus for performing a manufacturing method according to the present invention.
FIG. 2 is a graph showing an FTIR analysis result (1) for an insulating film layer according to the present invention formed using HMDSO as a source gas.
FIG. 3 is a process diagram showing an example in which the manufacturing method according to the present invention is applied to the formation of an interlayer insulating film.
FIG. 4 is a graph showing a FTIR analysis result (2) for an insulating film layer according to the present invention formed using TEOS as a source gas.
FIG. 5 is a process diagram showing an example in which the manufacturing method according to the present invention is applied to a damascene process for wiring.
FIG. 6 is a process diagram (part 1) showing an example in which the manufacturing method according to the present invention is applied to a dual damascene process for two-layer wiring;
FIG. 7 is a process diagram (part 2) showing an example in which the manufacturing method according to the present invention is applied to a dual damascene process for two-layer wiring;
FIG. 8 is a cross-sectional view showing an example in which the manufacturing method according to the present invention is applied to an FET gate formation process.
FIG. 9 is a cross-sectional view showing an example in which the manufacturing method according to the present invention is applied to a process for forming a contact hole of an FET.
FIG. 10 is a cross-sectional view showing an example in which the manufacturing method according to the present invention is applied to a process for forming a capacitor electrode of a memory cell.
[Explanation of symbols]
10 Low pressure CVD equipment
11 reaction chamber
17 Vacuum ultraviolet light source
18 Semiconductor substrate

Claims (8)

半導体基板の選択された領域に減圧ＣＶＤ法を用いて絶縁膜を形成する工程を含む半導体装置の製造方法であって、
前記絶縁膜層の形成工程は、前記絶縁膜層を成長させるべき前記半導体基板が配置された減圧ＣＶＤ装置の反応室に、原料ガスとして、ヘキサメチルジシロキサン（(CH3)3SiOSi(CH3)3）を供給しかつ添加ガスとして酸素を供給し、前記半導体基板に真空紫外光を照射した状態で前記絶縁膜層を成長させることを特徴とする、半導体装置の製造方法。A method of manufacturing a semiconductor device, including a step of forming an insulating film using a low pressure CVD method in a selected region of a semiconductor substrate,
In the step of forming the insulating film layer, hexamethyldisiloxane ((CH 3 ) 3 SiOSi (CH 3 ) is used as a source gas in a reaction chamber of a low pressure CVD apparatus in which the semiconductor substrate on which the insulating film layer is to be grown is disposed. 3 ) A method for manufacturing a semiconductor device, characterized in that the insulating film layer is grown in a state where oxygen is supplied as an additive gas and the semiconductor substrate is irradiated with vacuum ultraviolet light. 請求項１記載の方法であって、前記半導体基板上には、有機成分を含むフォトレジスト材料または導電性材料により、突起部が形成されており、前記半導体基板上の前記突起部を除く領域に前記絶縁膜層が選択的に成長することを特徴とする、半導体装置の製造方法。  The method according to claim 1, wherein a protrusion is formed on the semiconductor substrate by a photoresist material or a conductive material containing an organic component, and in a region excluding the protrusion on the semiconductor substrate. A method of manufacturing a semiconductor device, wherein the insulating film layer is selectively grown. 請求項１記載の方法であって、前記半導体基板上に導電性材料からなる導電部を形成すること、該導電部が形成された前記半導体基板上の前記導電部を除く領域に、前記ＣＶＤ法を用いて前記導電部とほぼ同一の高さ位置まで前記絶縁膜層を成長させること、前記絶縁膜層および該絶縁膜層から露出する前記導電部の表面を覆うべく、絶縁材料を堆積させることを特徴とする、半導体装置の製造方法。  The method according to claim 1, wherein a conductive portion made of a conductive material is formed on the semiconductor substrate, and the CVD method is applied to a region excluding the conductive portion on the semiconductor substrate on which the conductive portion is formed. The insulating film layer is grown to a level substantially the same as that of the conductive portion using an insulating material, and an insulating material is deposited so as to cover the insulating film layer and the surface of the conductive portion exposed from the insulating film layer. A method for manufacturing a semiconductor device. 請求項１記載の方法であって、前記半導体基板に絶縁膜を形成し、該絶縁膜上に有機成分を含むフォトレジスト材料からなる突起部を形成すること、該突起部が形成された前記半導体基板における前記突起部を除く領域に、前記ＣＶＤ法を用いて前記突起部とほぼ同一の高さ位置まで前記絶縁膜層を成長させること、前記フォトレジスト材料からなる前記突起部を除去すること、該突起部の除去により前記絶縁膜層により規定される凹所内を導電部のための導電性材料で埋め込むことを特徴とする、半導体装置の製造方法。  2. The method according to claim 1, wherein an insulating film is formed on the semiconductor substrate, a protrusion made of a photoresist material containing an organic component is formed on the insulating film, and the semiconductor on which the protrusion is formed. Growing the insulating film layer up to substantially the same height as the protrusion using the CVD method in a region excluding the protrusion on the substrate; removing the protrusion made of the photoresist material; A method of manufacturing a semiconductor device, wherein the recess defined by the insulating film layer is filled with a conductive material for a conductive portion by removing the protrusion. 請求項１記載の方法であって、前記半導体基板上に導電性材料からなる導電部を形成すること、該導電部上にフォトレジスト材料からなる柱部を形成すること、該柱部が形成された前記半導体基板上における前記柱部を除く領域に、前記ＣＶＤ法を用いて前記柱部とほぼ同一の高さ位置まで絶縁膜層を成長させること、前記柱部の頂面から前記絶縁膜層上に伸びる前記フォトレジスト材料からなる突起部を形成すること、前記絶縁膜層上の前記突起部から露出する領域に、前記ＣＶＤ法を用いて前記突起部とほぼ同一の高さ位置まで新たに前記絶縁膜層を成長させること、前記フォトレジスト材料からなる前記突起部および前記柱部を除去すること、前記突起部および前記柱部の除去により前記両絶縁膜層により定義される凹所内を導電性材料で埋め込むことを特徴とする、半導体装置の製造方法。The method according to claim 1, wherein a conductive portion made of a conductive material is formed on the semiconductor substrate, a pillar portion made of a photoresist material is formed on the conductive portion, and the pillar portion is formed. In addition, an insulating film layer is grown on the semiconductor substrate except for the pillar portion by using the CVD method up to a height position substantially equal to the pillar portion, and the insulating film layer is formed from the top surface of the pillar portion. Forming a protrusion made of the photoresist material extending upward, and newly exposing the protrusion on the insulating film layer to a position substantially the same as the protrusion using the CVD method; Growing the insulating film layer, removing the protrusion and the pillar made of the photoresist material, and removing the protrusion and the pillar to conduct the inside of the recess defined by the both insulating film layers. Material And wherein the embedding in, a method of manufacturing a semiconductor device. 請求項４記載の方法であって、前記絶縁膜はゲート酸化膜であり、前記導電部はゲートであることを特徴とする、半導体装置の製造方法。 5. The method of manufacturing a semiconductor device according to claim 4 , wherein the insulating film is a gate oxide film, and the conductive portion is a gate. 請求項３記載の方法であって、前記導電部は電界効果型トランジスタのソース・ドレインに至る導電部であることを特徴とする、半導体装置の製造方法。4. The method of manufacturing a semiconductor device according to claim 3 , wherein the conductive portion is a conductive portion reaching a source / drain of a field effect transistor. 請求項４記載の方法であって、前記導電部はメモリセルのキャパシタを構成する一方の電極であることを特徴とする、半導体装置の製造方法。5. The method of manufacturing a semiconductor device according to claim 4, wherein the conductive portion is one electrode constituting a capacitor of a memory cell.
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