WO2017208923A1 - Organic thin film transistor and image display device - Google Patents
Organic thin film transistor and image display device Download PDFInfo
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- WO2017208923A1 WO2017208923A1 PCT/JP2017/019327 JP2017019327W WO2017208923A1 WO 2017208923 A1 WO2017208923 A1 WO 2017208923A1 JP 2017019327 W JP2017019327 W JP 2017019327W WO 2017208923 A1 WO2017208923 A1 WO 2017208923A1
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- insulating layer
- thin film
- electrode
- film transistor
- organic thin
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Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
- H10K10/40—Organic transistors
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
- G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
- G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
- H10K10/40—Organic transistors
- H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
Definitions
- the present invention relates to an organic thin film transistor and an image display device.
- Thin film transistors are widely used in active matrix display devices and sensors such as liquid crystal display devices (LCD), organic electroluminescence (EL) display devices, and electronic paper display devices.
- LCD liquid crystal display devices
- EL organic electroluminescence
- semiconductor materials used for thin film transistors those using amorphous silicon, polycrystalline silicon, oxide semiconductors, and the like have become mainstream, and thin film transistors using these semiconductor materials are formed using a vacuum film formation method.
- patterning is performed by a photolithography method or the like.
- organic thin-film transistors using organic materials as semiconductor layers have attracted attention.
- devices such as semiconductor materials, conductive materials and insulating materials can be formed on plastic substrates at low temperatures by using wet film formation methods such as coating and printing techniques, and at low cost. Since there is a possibility of device manufacturing and the printing method performs film formation and patterning processes at the same time, the material utilization efficiency is high compared to the vacuum film formation process using the conventional photolithography process, and development and etching are performed. Since no process is required, it is also expected to have a low environmental impact.
- the area of the thin film transistor portion becomes large, and it becomes difficult to produce a high-definition thin film transistor pattern.
- the area of the thin film transistor portion is increased, the area of the capacitor electrode that functions as an auxiliary capacitor for driving an active matrix image display device using a thin film transistor is limited, so that it is difficult to obtain a sufficient capacity. It becomes.
- a capacitor installed in a thin film transistor plays a role of assisting voltage holding at the time of writing of each pixel, and if the capacity is insufficient, the voltage holding ratio at the selection time decreases. Measures such as increasing the writing voltage or increasing the number of writings are required, and as a result, the writing time and power consumption of the image display device are increased.
- An object of the present invention is to provide an organic thin film transistor and an image display device which can maintain a voltage holding ratio and can be stably driven.
- One aspect of the present invention for solving the above problems includes at least a gate electrode, a capacitor electrode, a first insulating layer formed so as to cover at least the gate electrode, and at least a capacitor electrode on an insulating substrate.
- An organic thin film transistor having a second insulating layer formed so as to cover a part, a source electrode, a drain electrode, and a semiconductor layer containing an organic semiconductor material, wherein the thickness of the second insulating layer is This is an organic thin film transistor formed thinner than the thickness of one insulating film.
- At least a gate electrode, a capacitor electrode, a first insulating layer formed to cover at least the gate electrode, and at least a part of the capacitor electrode are formed on an insulating substrate.
- the first insulating layer may be formed by stacking two or more insulating materials.
- the second insulating layer may be formed by stacking two or more insulating materials.
- the second insulating layer is composed of multiple layers, a part of the layer may be formed of the same material and composition as the first insulating layer.
- a first insulation formed on an insulating substrate so as to cover at least a source electrode, a drain electrode, a semiconductor layer containing an organic semiconductor material, and the source electrode and the semiconductor layer.
- An organic thin film transistor having a layer, a second insulating layer formed so as to cover at least a part of the drain electrode, a gate electrode, and a capacitor electrode, wherein the second insulating layer has a film thickness of It is an organic thin film transistor characterized by being thinner than the thickness of one insulating layer.
- the dielectric constant of the second insulating layer may be larger than the dielectric constant of the first insulating layer.
- the first insulating layer may be formed by stacking two or more insulating materials.
- the second insulating layer may be formed by stacking two or more insulating materials.
- Another aspect of the present invention is an image display device using the above-described organic thin film transistor.
- the present invention in an organic thin film transistor manufactured using a printing method, even when a sufficient capacitor electrode area cannot be secured, the voltage holding ratio is maintained and stabilized by securing the capacitance of the capacitor.
- the present invention it is possible to provide an organic thin film transistor and an image display device that exhibit device characteristics that can be driven.
- FIG. 1 is a schematic cross-sectional view of an organic thin film transistor according to the first embodiment of the present invention.
- FIG. 2 is a schematic cross-sectional view of an organic thin film transistor according to the second embodiment of the present invention.
- FIG. 3 is a schematic cross-sectional view of an organic thin film transistor according to the third embodiment of the present invention.
- FIG. 4 is a schematic cross-sectional view of an organic thin film transistor according to the fourth embodiment of the present invention.
- FIG. 5 is a schematic cross-sectional view of an organic thin film transistor according to the fifth embodiment of the present invention.
- FIG. 6 is a schematic cross-sectional view of an organic thin film transistor according to a sixth embodiment of the present invention.
- FIG. 1 is a schematic cross-sectional view of an organic thin film transistor according to the first embodiment of the present invention.
- FIG. 2 is a schematic cross-sectional view of an organic thin film transistor according to the second embodiment of the present invention.
- FIG. 3 is a schematic cross-sectional view of
- FIG. 7 is a schematic cross-sectional view of an organic thin film transistor according to a seventh embodiment of the present invention.
- FIG. 8 is a schematic cross-sectional view of an organic thin film transistor according to an eighth embodiment of the present invention.
- FIG. 9 is a schematic cross-sectional view of an organic thin film transistor according to a ninth embodiment of the present invention.
- FIG. 10 is a schematic cross-sectional view of an organic thin film transistor according to Comparative Example 1.
- FIG. 11 is a schematic cross-sectional view of an organic thin film transistor according to Comparative Example 2.
- FIG. 12 is a schematic cross-sectional view of an organic thin film transistor according to Comparative Example 3.
- FIG. 1 is a schematic cross-sectional view showing an organic thin film transistor 100 according to a first embodiment of the present invention.
- the organic thin film transistor 100 includes a gate electrode 2 and a capacitor electrode 3 formed on an insulating substrate 1, a first insulating layer 4 formed so as to cover at least the gate electrode 2, and at least one capacitor electrode 3. At least a second insulating layer 5 formed so as to cover the portion, a source electrode 6 and a drain electrode 7, and a semiconductor layer 8 made of an organic semiconductor material. A protective layer 9 for protecting the semiconductor layer 8 is also preferably used.
- an image display device can be obtained.
- the structure of the counter electrode and the second substrate can be appropriately changed depending on the type of display element used.
- the substrate 1 is prepared.
- the material of the substrate polycarbonate, polyethylene sulfide, polyethersulfone, polyethylene terephthalate, polyethylene naphthalate, cycloolefin polymer, triacetyl cellulose, polyvinyl fluoride film, ethylene-tetrafluoroethylene copolymer resin, weather resistant polyethylene terephthalate, Weatherable polypropylene, glass fiber reinforced acrylic resin film, glass fiber reinforced polycarbonate, polyimide, fluorine resin, cyclic polyolefin resin, glass, quartz glass, and the like can be used, but are not limited thereto. These may be used alone, but can also be used as a composite substrate 1 in which two or more kinds are laminated.
- a transparent gas barrier layer (not shown) can be formed to improve the durability of the organic thin film transistor 100.
- the gas barrier layer include aluminum oxide (Al 2 O 3 ), silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide (SiC), and diamond-like carbon (DLC). It is not limited to. These gas barrier layers can also be used by laminating two or more layers. The gas barrier layer may be formed only on one side of the substrate 1 using an organic film, or may be formed on both sides.
- the gas barrier layer can be formed using a vacuum deposition method, an ion plating method, a sputtering method, a laser ablation method, a plasma CVD (Chemical Vapor Deposition) method, a hot wire CVD method, a sol-gel method, and the like. It is not limited to these.
- an adhesion layer can be provided in order to improve the adhesion between the gate electrode 2 and the capacitor electrode 3 formed on the substrate 1 and the substrate 1, or surface treatment or the like may be performed on the surface of the substrate 1.
- the gate electrode 2 and the capacitor electrode 3 are formed on the substrate 1.
- the gate electrode 2, the capacitor electrode 3, the source electrode 6, and the drain electrode 7 do not need to be clearly separated from each other in the electrode portion and the wiring portion, and are hereinafter referred to as electrodes as components of each organic thin film transistor.
- the gate electrode 2 and the capacitor electrode 3 include aluminum (Al), copper (Cu), molybdenum (Mo), silver (Ag), chromium (Cr), titanium (Ti), gold (Au), platinum (Pt), Metal materials such as tungsten (W) and manganese (Mn), and conductive materials such as indium oxide (InO), tin oxide (SnO), zinc oxide (ZnO), indium tin oxide (ITO), and indium zinc oxide (IZO) Although a metal oxide material can be used, it is not limited to these. These materials may be used as a single layer, or may be used as a laminate or an alloy.
- the gate electrode 2 and the capacitor electrode 3 can be formed by vacuum film-forming methods such as vacuum deposition and sputtering, sol-gel methods using precursors of conductive materials, methods using nanoparticles, and the like.
- a method of forming an ink and forming it by a wet film forming method such as screen printing, letterpress printing, or an ink jet method can be used, but the method is not limited to these, and a known general method can be used.
- Patterning can be performed by, for example, protecting a pattern forming portion with a resist or the like using a photolithography method and removing an unnecessary portion by etching, or patterning directly using a printing method or the like. Also, the method is not limited to these methods, and a known general patterning method can be used.
- a first insulating layer 4 is formed so as to cover at least the gate electrode 2.
- the first insulating layer 4 includes oxide-based insulating materials such as silicon oxide (SiOx), aluminum oxide (AlOx), tantalum oxide (TaOx), yttrium oxide (YOx), zirconium oxide (ZrOx), and hafnium oxide (HfOx).
- oxide-based insulating materials such as silicon oxide (SiOx), aluminum oxide (AlOx), tantalum oxide (TaOx), yttrium oxide (YOx), zirconium oxide (ZrOx), and hafnium oxide (HfOx).
- Materials organic insulating materials such as silicon nitride (SiNx), silicon oxynitride (SiON), polyacrylates such as polymethyl methacrylate (PMMA), polyvinyl alcohol (PVA), polyvinylphenol (PVP), and self-assembled films
- PMMA polymethyl methacrylate
- PVA polyvinyl alcohol
- PVP polyvinylphenol
- the first insulating layer 4 When a self-assembled film is used for the first insulating layer 4, it is possible to control the dielectric constant and insulation of the insulating layer by using a multilayer film structure in which different self-assembled materials are laminated. Furthermore, it is also possible to improve insulation by making a self-assembled multilayer film into a repeated structure. It is also possible to improve the performance of the organic thin film transistor 100 by selecting the functional group on the surface according to the type of the semiconductor layer 8 formed on the surface of the first insulating layer 4 and controlling the surface energy. .
- the first insulating layer 4 desirably has a resistivity of 10 11 ⁇ cm or more, more preferably 10 14 ⁇ cm or more, in order to suppress leakage current in the organic thin film transistor 100 and the image display device 200.
- the second insulating layer 5 is formed on the capacitor electrode 3.
- the second insulating layer 5 is formed so as to cover at least a part of the capacitor electrode 3, and forms a capacitor structure by the drain electrode 7 formed so as to overlap the capacitor electrode 3 on the second insulating layer 5. Thus, it functions as a capacitor of an image display device using the organic thin film transistor 100.
- the formation of the first insulating layer 4 and the second insulating layer 5 is not limited to this order, and the first insulating layer 4 may be formed after the second insulating layer 5 is formed.
- the second insulating layer 5 includes oxide-based insulating materials such as silicon oxide (SiOx), aluminum oxide (AlOx), tantalum oxide (TaOx), yttrium oxide (YOx), zirconium oxide (ZrOx), and hafnium oxide (HfOx).
- oxide-based insulating materials such as silicon oxide (SiOx), aluminum oxide (AlOx), tantalum oxide (TaOx), yttrium oxide (YOx), zirconium oxide (ZrOx), and hafnium oxide (HfOx).
- Materials organic insulating materials such as silicon nitride (SiNx), silicon oxynitride (SiON), polyacrylates such as polymethyl methacrylate (PMMA), polyvinyl alcohol (PVA), polyvinylphenol (PVP), and self-assembled films
- PMMA polymethyl methacrylate
- PVA polyvinyl alcohol
- PVP polyvinylphenol
- the second insulating layer 5 When a self-assembled film is used for the second insulating layer 5, it is possible to control the dielectric constant and insulation of the insulating layer by adopting a multilayer film structure in which different self-assembled materials are laminated. Furthermore, it is also possible to improve insulation by making a self-assembled multilayer film into a repeated structure.
- the second insulating layer 5 desirably has a resistivity of 10 11 ⁇ cm or more, more preferably 10 14 ⁇ cm or more, in order to suppress leakage current in the organic thin film transistor 100 and the image display device.
- the second insulating layer 5 forms a capacitor structure by insulating the capacitor electrode 3 and the drain electrode 7 in the organic thin film transistor 100.
- the film thickness of the second insulating layer 5 is the first insulating thickness in order to secure the capacitance of the capacitor. It is preferable to make it thinner than the layer 4.
- the second insulating layer 5 is formed to be thinner than the first insulating layer 4, thereby increasing the capacitance of the capacitor while keeping the leakage current in the first insulating layer 4 low. Is possible.
- the second insulating layer 5 may use the same material and composition as the first insulating layer 4, or may use different materials and can be formed in various combinations without being limited thereto. It is.
- the relative dielectric constant of the first insulating layer 4 is preferably 2 or more and 5 or less.
- the relative dielectric constant of the second insulating layer 5 is 3 or more, preferably 5 or more, and more preferably 20 or more, but is not limited thereto.
- the first insulating layer 4 and the second insulating layer 5 are formed using a vacuum film-forming method such as a vacuum deposition method or a sputtering method, a sol-gel method using a metal complex or the like as a precursor, or nanoparticles.
- a vacuum film-forming method such as a vacuum deposition method or a sputtering method, a sol-gel method using a metal complex or the like as a precursor, or nanoparticles.
- a method of forming by a wet coating method such as a slit coating method, a spin coating method, screen printing, letterpress printing, or an ink jet method can be used, but the method is not limited to these, and a known general method can be used. .
- the source electrode 6 and the drain electrode 7 are formed on the first insulating layer 4 and the second insulating layer 5.
- the source electrode 6 and the drain electrode 7 can be formed by the same material and method as the gate electrode 2 and the capacitor electrode 3 described above.
- the source electrode 6 and the drain electrode 7 may have a bottom contact structure in which the source electrode 6 and the drain electrode 7 are formed before the semiconductor layer 8, or the source electrode 6 and the drain electrode 7 may be formed after the semiconductor layer 8 is formed.
- a top contact structure may be formed.
- the source electrode 6 and the drain electrode 7 can be subjected to a surface treatment or the like in order to reduce contact resistance in electrical connection with the semiconductor layer 8.
- a semiconductor layer 8 is formed on the first insulating layer 4, the source electrode 6 and the drain electrode 7.
- low molecular semiconductors such as pentacene and derivatives thereof, and polymer organic semiconductor materials such as polythiophene, polyallylamine, fluorenebithiophene copolymers, and derivatives thereof can be used. It is not limited to these.
- the semiconductor layer 8 can be formed by a wet film forming method such as letterpress printing, screen printing, ink jet method, or nozzle printing using a solution in which an organic semiconductor material is dissolved or dispersed as ink, but is not limited thereto. Instead, it is also possible to use known general methods.
- the organic thin film transistor 100 can be suitably provided with a protective layer 9 for protecting the semiconductor layer 8 from external influences.
- the protective layer 9 is preferably formed so as to cover at least the channel region of the semiconductor layer 8.
- Examples of the material of the protective layer 9 include inorganic materials such as silicon oxide, aluminum oxide, tantalum oxide, yttrium oxide, hafnium oxide, hafnium aluminate, zirconium oxide, and titanium oxide, or polyacrylates such as PMMA (polymethyl methacrylate), Examples thereof include, but are not limited to, insulating materials such as PVA (polyvinyl alcohol), PVP (polyvinylphenol), and fluorine resins.
- inorganic materials such as silicon oxide, aluminum oxide, tantalum oxide, yttrium oxide, hafnium oxide, hafnium aluminate, zirconium oxide, and titanium oxide
- polyacrylates such as PMMA (polymethyl methacrylate)
- Examples thereof include, but are not limited to, insulating materials such as PVA (polyvinyl alcohol), PVP (polyvinylphenol), and fluorine resins.
- the resistivity is 10 11 ⁇ cm or more, more preferably 10 14 ⁇ cm or more.
- the protective layer 9 is formed by any one of an inkjet method, a relief printing method, a planographic printing method, an intaglio printing method, and a screen printing method using a solution in which the protective layer material or its precursor is dissolved or dispersed. .
- These protective layers 9 may be used as a single layer or may be used by laminating two or more layers. Further, the composition may be inclined in the growth direction.
- an interlayer insulating film 10 In an image display device using the organic thin film transistor 100, an interlayer insulating film 10, a pixel electrode 11, a display element (not shown), a counter electrode (not shown), and a counter substrate (not shown) are preferably provided.
- the interlayer insulating film 10 is formed mainly for the purpose of preventing a source-drain leak through the pixel electrode 11 by insulating the source electrode 6 and the pixel electrode 11.
- Examples of the material for the interlayer insulating film 10 include inorganic materials such as silicon oxide, aluminum oxide, tantalum oxide, yttrium oxide, hafnium oxide, hafnium aluminate, zirconium oxide, and titanium oxide, or polyacrylates such as PMMA (polymethyl methacrylate). Insulating materials such as PVA (polyvinyl alcohol), PVP (polyvinylphenol), and fluorine-based resins are included, but are not limited thereto.
- inorganic materials such as silicon oxide, aluminum oxide, tantalum oxide, yttrium oxide, hafnium oxide, hafnium aluminate, zirconium oxide, and titanium oxide
- polyacrylates such as PMMA (polymethyl methacrylate).
- Insulating materials such as PVA (polyvinyl alcohol), PVP (polyvinylphenol), and fluorine-based resins are included, but are not limited thereto.
- the resistivity is 10 11 ⁇ cm or more, more preferably 10 14 ⁇ cm or more.
- the interlayer insulating film 10 is formed by any one of an inkjet method, a relief printing method, a planographic printing method, an intaglio printing method, and a screen printing method using a solution in which a protective layer material or a precursor thereof is dissolved or dispersed.
- the These interlayer insulating films 10 may be used as a single layer or may be used by stacking two or more layers. Further, the composition may be inclined in the growth direction.
- the pixel electrode 11 is formed for the purpose of improving the aperture ratio of the image display device.
- the pixel electrode 11 includes aluminum (Al), copper (Cu), molybdenum (Mo), silver (Ag), chromium (Cr), titanium (Ti), gold (Au), platinum (Pt), tungsten (W), Metal materials such as manganese (Mn) and conductive metal oxide materials such as indium oxide (InO), tin oxide (SnO), zinc oxide (ZnO), indium tin oxide (ITO), and indium zinc oxide (IZO) Although it can be used, it is not limited to these. These materials may be used as a single layer, or may be used as a laminate or an alloy.
- the pixel electrode 11 can be formed by vacuum film-forming methods such as vacuum deposition and sputtering, sol-gel methods using a precursor of a conductive material, a method using nanoparticles, screen printing by converting them into ink, A method of forming by a wet film forming method such as letterpress printing or an ink jet method can be used, but the method is not limited to these, and a known general method can be used. Patterning can be performed by, for example, protecting a pattern forming portion with a resist or the like using a photolithography method and removing an unnecessary portion by etching, or patterning directly using a printing method or the like. Also, the method is not limited to these methods, and a known general patterning method can be used.
- liquid crystal electrophoretic particles, microcapsules containing electrophoretic particles, organic electroluminescence, or the like can be used.
- the image display apparatus it is possible to use these known general display elements without being limited to either a reflection type or a transmission type. Further, depending on the display element to be used, it is possible to use a configuration in which a plurality of organic thin film transistors 100 are installed in one pixel.
- the display element may be formed on the counter substrate on which the counter electrode is formed, and then combined with the organic thin film transistor 100 formed up to the pixel electrode 11 to form an image display device. After the display element is formed on the pixel electrode 11, the counter electrode, an image display device may be formed by laminating a counter substrate, and the process can be selected in accordance with a display element to be used.
- FIG. 2 is a schematic cross-sectional view showing an organic thin film transistor 110 according to a second embodiment of the present invention.
- the difference between the organic thin film transistor 100 and the organic thin film transistor 110 is a region where the second insulating layer 5 is formed.
- the second insulating layer 5 is laminated so as to cover the capacitor electrode 3 and the gate electrode 2 simultaneously.
- the first insulating layer 4 is laminated so as to cover the gate electrode 2 from above the second insulating layer 5.
- the film thickness of the second insulating layer 5 can be reduced as compared with the first insulating layer 4. It is possible to increase the capacitance of the capacitor while keeping the leakage current in the insulating layer 4 low.
- FIG. 3 is a schematic sectional view showing an organic thin film transistor 120 according to the third embodiment of the present invention.
- the difference between the organic thin film transistor 100 and the organic thin film transistor 120 is the film thickness of the second insulating layer 5 and the material used for the second insulating layer 5.
- the second insulating layer 5 is formed so as to cover the capacitor electrode 3, and the film thickness thereof is the same as that of the first insulating layer 4.
- the second insulating layer 5 is formed of a material having a higher dielectric constant than that of the first insulating layer 4.
- the leakage current in the first insulating layer 4 can be kept low even if both films have the same thickness.
- the capacitance of the capacitor can be increased.
- FIG. 4 is a schematic cross-sectional view showing an organic thin film transistor 130 according to the fourth embodiment of the present invention.
- the organic thin film transistor 130 includes a gate electrode 2 and a capacitor electrode 3 formed on an insulating substrate 1, a first insulating layer 4 formed so as to cover at least the gate electrode 2, and at least one capacitor electrode 3. At least a second insulating layer 5 formed so as to cover the portion, a source electrode 6 and a drain electrode 7, and a semiconductor layer 8 containing an organic semiconductor material. A protective layer 9 for protecting the semiconductor layer 8 is also preferably used.
- the organic thin film transistor 130 with the interlayer insulating film 10, the pixel electrode 11, a display element (not shown), a counter electrode (not shown), and a second substrate (not shown), an image display device can be obtained.
- the structures of the counter electrode and the second substrate can be appropriately changed depending on the type of display element used.
- the substrate 1 is prepared.
- the material of the substrate polycarbonate, polyethylene sulfide, polyethersulfone, polyethylene terephthalate, polyethylene naphthalate, cycloolefin polymer, triacetyl cellulose, polyvinyl fluoride film, ethylene-tetrafluoroethylene copolymer resin, weather resistant polyethylene terephthalate, Weatherable polypropylene, glass fiber reinforced acrylic resin film, glass fiber reinforced polycarbonate, polyimide, fluorine resin, cyclic polyolefin resin, glass, quartz glass, and the like can be used, but are not limited thereto. These may be used alone, but can also be used as a composite substrate 1 in which two or more kinds are laminated.
- a transparent gas barrier layer (not shown) can be formed in order to improve the durability of the organic thin film transistor 130.
- the gas barrier layer include aluminum oxide (Al 2 O 3 ), silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide (SiC), diamond-like carbon (DLC), and the like. However, it is not limited to these. These gas barrier layers can be used by laminating two or more layers. The gas barrier layer may be formed only on one side of the substrate 1 using an organic film, or may be formed on both sides.
- the gas barrier layer can be formed using a vacuum deposition method, an ion plating method, a sputtering method, a laser ablation method, a plasma CVD (Chemical Vapor Deposition) method, a hot wire CVD method, a sol-gel method, etc. It is not limited to these.
- an adhesion layer can be provided in order to improve the adhesion between the gate electrode 2 and the capacitor electrode 3 formed on the substrate 1 and the substrate 1, or the surface of the substrate 1 may be subjected to a surface treatment or the like. .
- the gate electrode 2 and the capacitor electrode 3 are formed on the substrate 1.
- the gate electrode 2, the capacitor electrode 3, the source electrode 6, and the drain electrode 7 do not need to be clearly separated from each other in the electrode portion and the wiring portion, and are hereinafter referred to as electrodes as components of each organic thin film transistor. .
- the gate electrode 2 and the capacitor electrode 3 include aluminum (Al), copper (Cu), molybdenum (Mo), silver (Ag), chromium (Cr), titanium (Ti), gold (Au), platinum (Pt), Metal materials such as tungsten (W) and manganese (Mn), and conductive materials such as indium oxide (InO), tin oxide (SnO), zinc oxide (ZnO), indium tin oxide (ITO), and indium zinc oxide (IZO) Although a metal oxide material can be used, it is not limited to these. These materials may be used as a single layer, or may be used as a laminate or an alloy.
- the gate electrode 2 and the capacitor electrode 3 can be formed by vacuum film-forming methods such as vacuum deposition and sputtering, sol-gel methods using precursors of conductive materials, methods using nanoparticles, and the like.
- a method of forming an ink and forming it by a wet film forming method such as screen printing, letterpress printing, or an ink jet method can be used, but the method is not limited to these, and a known general method can be used.
- Patterning can be performed by, for example, protecting a pattern forming portion with a resist or the like using a photolithography method and removing an unnecessary portion by etching, or patterning directly using a printing method or the like. Also, the method is not limited to these methods, and a known general patterning method can be used.
- a first insulating layer 4 is formed so as to cover at least the gate electrode 2.
- the first insulating layer 4 includes oxide-based insulating materials such as silicon oxide (SiOx), aluminum oxide (AlOx), tantalum oxide (TaOx), yttrium oxide (YOx), zirconium oxide (ZrOx), and hafnium oxide (HfOx).
- oxide-based insulating materials such as silicon oxide (SiOx), aluminum oxide (AlOx), tantalum oxide (TaOx), yttrium oxide (YOx), zirconium oxide (ZrOx), and hafnium oxide (HfOx).
- Materials organic insulating materials such as silicon nitride (SiNx), silicon oxynitride (SiON), polyacrylates such as polymethyl methacrylate (PMMA), polyvinyl alcohol (PVA), polyvinylphenol (PVP), and self-assembled films
- PMMA polymethyl methacrylate
- PVA polyvinyl alcohol
- PVP polyvinylphenol
- the first insulating layer 4 When a self-assembled film is used for the first insulating layer 4, it is possible to control the dielectric constant and insulation of the insulating layer by using a multilayer film structure in which different self-assembled materials are laminated. Furthermore, it is also possible to improve insulation by making a self-assembled multilayer film into a repeated structure. It is also possible to improve the performance of the organic thin film transistor 130 by selecting the surface functional group according to the type of the semiconductor layer 8 formed on the surface of the first insulating layer 4 and controlling the surface energy. is there.
- the first insulating layer 4 desirably has a resistivity of 10 11 ⁇ cm or more, more preferably 10 14 ⁇ cm or more, in order to suppress leakage current in the organic thin film transistor 130 and the image display device.
- the second insulating layer 5 is formed on the capacitor electrode 3.
- the second insulating layer 5 is formed so as to cover at least a part of the capacitor electrode 3, and forms a capacitor structure by the drain electrode 7 formed so as to overlap the capacitor electrode 3 on the second insulating layer 5. Thus, it functions as a voltage holding capacitor of an image display device using the organic thin film transistor 130.
- the formation of the first insulating layer 4 and the second insulating layer 5 is not limited to this order, and the first insulating layer 4 may be formed after the second insulating layer 5 is formed.
- the second insulating layer 5 includes oxide-based insulating materials such as silicon oxide (SiOx), aluminum oxide (AlOx), tantalum oxide (TaOx), yttrium oxide (YOx), zirconium oxide (ZrOx), and hafnium oxide (HfOx).
- oxide-based insulating materials such as silicon oxide (SiOx), aluminum oxide (AlOx), tantalum oxide (TaOx), yttrium oxide (YOx), zirconium oxide (ZrOx), and hafnium oxide (HfOx).
- Materials organic insulating materials such as silicon nitride (SiNx), silicon oxynitride (SiON), polyacrylates such as polymethyl methacrylate (PMMA), polyvinyl alcohol (PVA), polyvinylphenol (PVP), and self-assembled films
- PMMA polymethyl methacrylate
- PVA polyvinyl alcohol
- PVP polyvinylphenol
- the second insulating layer 5 When a self-assembled film is used for the second insulating layer 5, it is possible to control the dielectric constant and insulation of the insulating layer by adopting a multilayer film structure in which different self-assembled materials are laminated. Furthermore, it is also possible to improve insulation by making a self-assembled multilayer film into a repeated structure.
- the second insulating layer 5 desirably has a resistivity of 10 11 ⁇ cm or more, more preferably 10 14 ⁇ cm or more, in order to suppress leakage current in the organic thin film transistor 130 and the image display device.
- the second insulating layer 5 forms a capacitor structure by insulating the capacitor electrode 3 and the drain electrode 7 in the organic thin film transistor 130, and in order to secure the capacitance of the capacitor, the dielectric constant thereof is changed to the first insulating layer. It is preferable to make it larger than that of the layer 4.
- the capacitance of the capacitor can be increased by making the dielectric constant of the second insulating layer 5 larger than the dielectric constant of the first insulating layer 4.
- the relative dielectric constant of the first insulating layer 4 is preferably 2 or more and 5 or less.
- the relative dielectric constant of the second insulating layer 5 is 3 or more, preferably 5 or more, and more preferably 20 or more, but is not limited thereto.
- the same material and composition as the first insulating layer 4 may be used for a part of the second insulating layer 5, or all different materials may be used. Without being limited thereto, various combinations can be formed.
- the thickness of the second insulating layer 5 thinner than that of the first insulating layer 4, it is possible to further increase the capacitance of the capacitor while keeping the gate leakage current in the first insulating layer 4 low. Become.
- the first insulating layer 4 and the second insulating layer 5 are formed using a vacuum film-forming method such as a vacuum deposition method or a sputtering method, a sol-gel method using a metal complex or the like as a precursor, or nanoparticles.
- a vacuum film-forming method such as a vacuum deposition method or a sputtering method, a sol-gel method using a metal complex or the like as a precursor, or nanoparticles.
- a method of forming by a wet coating method such as a slit coating method, a spin coating method, screen printing, letterpress printing, or an ink jet method can be used, but the method is not limited to these, and a known general method can be used. .
- the source electrode 6 and the drain electrode 7 are formed on the first insulating layer 4 and the second insulating layer 5.
- the source electrode 6 and the drain electrode 7 can be formed by the same material and method as the gate electrode 2 and the capacitor electrode 3 described above.
- the source electrode 6 and the drain electrode 7 may have a bottom contact structure in which the source electrode 6 and the drain electrode 7 are formed before the semiconductor layer 8, or the source electrode 6 and the drain electrode 7 may be formed after the semiconductor layer 8 is formed.
- a top contact structure may be formed.
- the source electrode 6 and the drain electrode 7 can be subjected to a surface treatment or the like in order to reduce contact resistance in electrical connection with the semiconductor layer 8.
- a semiconductor layer 8 is formed on the first insulating layer 4, the source electrode 6 and the drain electrode 7.
- low molecular semiconductors such as pentacene and derivatives thereof, and polymer organic semiconductor materials such as polythiophene, polyallylamine, fluorenebithiophene copolymers, and derivatives thereof can be used. It is not limited to.
- the semiconductor layer 8 can be formed by a wet film forming method such as letterpress printing, screen printing, ink jet method, or nozzle printing using a solution in which an organic semiconductor material is dissolved or dispersed as ink, but is not limited thereto. Instead, it is also possible to use known general methods.
- the organic thin film transistor 130 can be suitably provided with a protective layer 9 for protecting the semiconductor layer 8 from external influences.
- the protective layer 9 is preferably formed so as to cover at least the channel region of the semiconductor layer 8.
- Examples of the material of the protective layer 9 include inorganic materials such as silicon oxide, aluminum oxide, tantalum oxide, yttrium oxide, hafnium oxide, hafnium aluminate, zirconium oxide, and titanium oxide, or polyacrylates such as PMMA (polymethyl methacrylate), Organic insulating materials such as PVA (polyvinyl alcohol), PVP (polyvinylphenol), and fluorine-based resin are exemplified, but the invention is not limited thereto.
- inorganic materials such as silicon oxide, aluminum oxide, tantalum oxide, yttrium oxide, hafnium oxide, hafnium aluminate, zirconium oxide, and titanium oxide
- polyacrylates such as PMMA (polymethyl methacrylate)
- Organic insulating materials such as PVA (polyvinyl alcohol), PVP (polyvinylphenol), and fluorine-based resin are exemplified, but the invention is not limited thereto.
- the resistivity is 10 11 ⁇ cm or more, more preferably 10 14 ⁇ cm or more.
- the protective layer 9 is formed by any one of an inkjet method, a relief printing method, a planographic printing method, an intaglio printing method, and a screen printing method using a solution in which the protective layer material or its precursor is dissolved or dispersed. .
- These protective layers 9 may be used as a single layer, or two or more layers may be laminated. Further, the composition may be inclined in the growth direction.
- the interlayer insulating film 10 In an image display device using the organic thin film transistor 130, the interlayer insulating film 10, the pixel electrode 11, a display element (not shown), a counter electrode (not shown), and a counter substrate (not shown) are preferably provided.
- the interlayer insulating film 10 is formed mainly for the purpose of preventing a source-drain leak through the pixel electrode 11 by insulating the source electrode 6 and the pixel electrode 11.
- Examples of the material for the interlayer insulating film 10 include inorganic materials such as silicon oxide, aluminum oxide, tantalum oxide, yttrium oxide, hafnium oxide, hafnium aluminate, zirconium oxide, and titanium oxide, or polyacrylates such as PMMA (polymethyl methacrylate). Insulating materials such as PVA (polyvinyl alcohol), PVP (polyvinylphenol), and fluorine-based resin are not limited thereto.
- the resistivity is 10 11 ⁇ cm or more, more preferably 10 14 ⁇ cm or more.
- the interlayer insulating film 10 is formed by any one of an inkjet method, a relief printing method, a planographic printing method, an intaglio printing method, and a screen printing method using a solution in which a protective layer material or a precursor thereof is dissolved or dispersed.
- the These interlayer insulating films 10 may be used as a single layer or may be used by stacking two or more layers. Further, the composition may be inclined in the growth direction.
- the pixel electrode 11 is formed for the purpose of improving the aperture ratio of the image display device.
- the pixel electrode 11 includes aluminum (Al), copper (Cu), molybdenum (Mo), silver (Ag), chromium (Cr), titanium (Ti), gold (Au), platinum (Pt), tungsten (W), Metal materials such as manganese (Mn) and conductive metal oxide materials such as indium oxide (InO), tin oxide (SnO), zinc oxide (ZnO), indium tin oxide (ITO), and indium zinc oxide (IZO) Although it can be used, it is not limited to these. These materials may be used as a single layer, or may be used as a laminate or an alloy.
- the pixel electrode 11 can be formed by vacuum film-forming methods such as vacuum deposition and sputtering, sol-gel methods using a precursor of a conductive material, a method using nanoparticles, screen printing by converting them into ink, A method of forming by a wet film forming method such as letterpress printing or an ink jet method can be used, but the method is not limited to these, and a known general method can be used. Patterning can be performed by, for example, protecting a pattern forming portion with a resist or the like using a photolithography method and removing an unnecessary portion by etching, or patterning directly using a printing method or the like. Also, the method is not limited to these methods, and a known general patterning method can be used.
- liquid crystal electrophoretic particles, microcapsules containing electrophoretic particles, organic electroluminescence, or the like
- the image display apparatus it is possible to use these known general display elements without being limited to either a reflection type or a transmission type. Further, depending on the display element to be used, a configuration in which a plurality of organic thin film transistors 130 are installed in one pixel can be used.
- the display element may be formed on the counter substrate on which the counter electrode is formed, and then combined with the organic thin film transistor 130 formed up to the pixel electrode 11 to form an image display device, or after being formed on the pixel electrode 11, the counter electrode
- the counter substrate may be stacked to form an image display device, and the process can be selected in accordance with the display element to be used.
- FIG. 5 is a schematic cross-sectional view showing an organic thin film transistor 140 according to the fifth embodiment of the present invention.
- the difference between the organic thin film transistor 130 and the organic thin film transistor 140 is a region where the second insulating layer 5 is formed. As shown in FIG. 5, the second insulating layer 5 is laminated so as to cover the capacitor electrode 3 and the gate electrode 2 simultaneously. The first insulating layer 4 is laminated so as to cover the gate electrode 2 from above the second insulating layer 5.
- the amount of charge accumulated in the channel portion of the thin film transistor is increased without changing the surface property of the first insulating layer 4. Therefore, it is possible to increase not only the capacitor capacity but also the ON current of the thin film transistor.
- FIG. 6 is a schematic cross-sectional view showing an organic thin film transistor 150 according to the sixth embodiment of the present invention.
- the difference between the organic thin film transistor 130 and the organic thin film transistor 150 is a region where the first insulating layer 4 is formed.
- the first insulating layer 4 is formed so as to cover the gate electrode 2 and the capacitor electrode 3 simultaneously.
- the second insulating layer 5 is laminated so as to cover the capacitor electrode 3 from above the first insulating layer 4.
- the second insulating layer 5 is formed of a material having a higher dielectric constant than that of the first insulating layer 4.
- FIG. 7 is a schematic cross-sectional view showing an organic thin film transistor 160 according to a seventh embodiment of the present invention.
- the organic thin film transistor 160 is formed so as to cover the source electrode 6 and the drain electrode 7 formed on the insulating substrate 1, the semiconductor layer 8 containing an organic semiconductor material, and the source electrode 6 and the semiconductor layer 8. At least an insulating layer 4, a second insulating layer 5 formed so as to cover at least a part of the drain electrode 7, a gate electrode 2, and a capacitor electrode 3 are provided.
- the organic thin film transistor 160 with the interlayer insulating film 10, the pixel electrode 11, a display element (not shown), a counter electrode (not shown), and a second substrate (not shown), an image display device can be obtained.
- the structures of the counter electrode and the second substrate can be appropriately changed depending on the type of display element used.
- the substrate 1 is prepared.
- the material of the substrate polycarbonate, polyethylene sulfide, polyethersulfone, polyethylene terephthalate, polyethylene naphthalate, cycloolefin polymer, triacetyl cellulose, polyvinyl fluoride film, ethylene-tetrafluoroethylene copolymer resin, weather resistant polyethylene terephthalate, Weatherable polypropylene, glass fiber reinforced acrylic resin film, glass fiber reinforced polycarbonate, polyimide, fluorine resin, cyclic polyolefin resin, glass, quartz glass, and the like can be used, but are not limited thereto. These may be used alone, but can also be used as a composite substrate 1 in which two or more kinds are laminated.
- a transparent gas barrier layer (not shown) can be formed in order to improve the durability of the organic thin film transistor 160.
- the gas barrier layer include aluminum oxide (Al 2 O 3 ), silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide (SiC), diamond-like carbon (DLC), and the like. However, it is not limited to these. These gas barrier layers can be used by laminating two or more layers. The gas barrier layer may be formed only on one side of the substrate 1 using an organic film, or may be formed on both sides.
- the gas barrier layer can be formed using a vacuum deposition method, an ion plating method, a sputtering method, a laser ablation method, a plasma CVD (Chemical Vapor Deposition) method, a hot wire CVD method, a sol-gel method, etc. It is not limited to these.
- an adhesion layer can be provided to improve the adhesion of the source electrode 6, the drain electrode 7, and the semiconductor layer 8 formed on the substrate 1 to the substrate 1, and a surface treatment or the like is performed on the surface of the substrate 1. May be applied.
- the source electrode 6 and the drain electrode 7 are formed on the substrate 1.
- the source electrode 6, drain electrode 7, gate electrode 2, and capacitor electrode 3 do not need to be clearly separated from each other in the electrode portion and the wiring portion, and are hereinafter referred to as electrodes as components of each organic thin film transistor. .
- the source electrode 6 and the drain electrode 7 include aluminum (Al), copper (Cu), molybdenum (Mo), silver (Ag), chromium (Cr), titanium (Ti), gold (Au), platinum (Pt), Metal materials such as tungsten (W) and manganese (Mn), and conductive materials such as indium oxide (InO), tin oxide (SnO), zinc oxide (ZnO), indium tin oxide (ITO), and indium zinc oxide (IZO) Although a metal oxide material can be used, it is not limited to these. These materials may be used as a single layer, or may be used as a laminate or an alloy.
- the source electrode 6 and the drain electrode 7 can be formed by vacuum film-forming methods such as vacuum deposition and sputtering, sol-gel methods using precursors of conductive materials, methods using nanoparticles, and the like.
- a method of forming an ink and forming it by a wet film forming method such as screen printing, letterpress printing, or an ink jet method can be used, but the method is not limited to these, and a known general method can be used.
- Patterning can be performed by, for example, protecting a pattern forming portion with a resist or the like using a photolithography method and removing an unnecessary portion by etching, or patterning directly using a printing method or the like. Also, the method is not limited to these methods, and a known general patterning method can be used.
- the source electrode 6 and the drain electrode 7 may have a bottom contact structure in which the source electrode 6 and the drain electrode 7 are formed before the semiconductor layer 8, or the source electrode 6 and the drain electrode 7 may be formed after the semiconductor layer 8 is formed.
- a top contact structure may be formed.
- the source electrode 6 and the drain electrode 7 can be subjected to a surface treatment or the like in order to reduce the contact resistance in electrical connection with the semiconductor layer 8.
- a semiconductor layer 8 is formed on the insulating substrate 1, the source electrode 6, and the drain electrode 7.
- low molecular semiconductors such as pentacene and derivatives thereof, and polymer organic semiconductor materials such as polythiophene, polyallylamine, fluorenebithiophene copolymers, and derivatives thereof can be used. It is not limited to these.
- the semiconductor layer 8 can be formed by a wet film forming method such as letterpress printing, screen printing, ink jet method, or nozzle printing using a solution in which an organic semiconductor material is dissolved or dispersed as ink, but is not limited thereto. Instead, it is also possible to use known general methods.
- the first insulating layer 4 is formed so as to cover at least the source electrode 6 and the semiconductor layer 8.
- the first insulating layer 4 includes oxide-based insulating materials such as silicon oxide (SiOx), aluminum oxide (AlOx), tantalum oxide (TaOx), yttrium oxide (YOx), zirconium oxide (ZrOx), and hafnium oxide (HfOx).
- oxide-based insulating materials such as silicon oxide (SiOx), aluminum oxide (AlOx), tantalum oxide (TaOx), yttrium oxide (YOx), zirconium oxide (ZrOx), and hafnium oxide (HfOx).
- silicon nitride (SiNx), silicon oxynitride (SiON), polyacrylates such as polymethyl methacrylate (PMMA), organic insulating materials such as polyvinyl alcohol (PVA), polyvinylphenol (PVP), etc. may be used. However, it is not limited to these. These may be a single layer or a laminate of two or more layers, may be an inorganic-organ
- the first insulating layer 4 desirably has a resistivity of 10 11 ⁇ cm or more, more preferably 10 14 ⁇ cm or more, in order to suppress leakage current in the organic thin film transistor 160 and the image display device.
- the second insulating layer 5 is formed on the drain electrode 7.
- the second insulating layer 5 is formed so as to cover at least a part of the drain electrode 7, and a capacitor structure is formed by the capacitor electrode 3 formed so as to overlap the drain electrode 7 on the second insulating layer 5.
- it functions as a capacitor of an image display device using the organic thin film transistor 160.
- the formation of the first insulating layer 4 and the second insulating layer 5 is not limited to this order, and the first insulating layer 4 may be formed after the second insulating layer 5 is formed.
- the second insulating layer 5 includes oxide-based insulating materials such as silicon oxide (SiOx), aluminum oxide (AlOx), tantalum oxide (TaOx), yttrium oxide (YOx), zirconium oxide (ZrOx), and hafnium oxide (HfOx).
- oxide-based insulating materials such as silicon oxide (SiOx), aluminum oxide (AlOx), tantalum oxide (TaOx), yttrium oxide (YOx), zirconium oxide (ZrOx), and hafnium oxide (HfOx).
- Materials organic insulating materials such as silicon nitride (SiNx), silicon oxynitride (SiON), polyacrylates such as polymethyl methacrylate (PMMA), polyvinyl alcohol (PVA), polyvinylphenol (PVP), and self-assembled films
- PMMA polymethyl methacrylate
- PVA polyvinyl alcohol
- PVP polyvinylphenol
- the second insulating layer 5 When a self-assembled film is used for the second insulating layer 5, it is possible to control the dielectric constant and insulation of the insulating layer by adopting a multilayer film structure in which different self-assembled materials are laminated. Furthermore, it is also possible to improve insulation by making a self-assembled multilayer film into a repeated structure.
- the second insulating layer 5 desirably has a resistivity of 10 11 ⁇ cm or more, more preferably 10 14 ⁇ cm or more, in order to suppress leakage current in the organic thin film transistor 160 and the image display device.
- the second insulating layer 5 forms a capacitor structure by insulating the drain electrode 7 and the capacitor electrode 3 in the organic thin film transistor 160.
- the film thickness of the second insulating layer 5 is the first insulating thickness in order to secure the capacitance of the capacitor. It is preferable to make it thinner than the layer 4.
- the second insulating layer 5 is formed to be thinner than the first insulating layer 4, so that the leakage current in the transistor portion where the first insulating layer 4 is formed can be kept low while the capacitance of the capacitor is reduced. The electric capacity can be increased.
- the second insulating layer 5 may use the same material and composition as the first insulating layer 4, or may use different materials and can be formed in various combinations without being limited thereto. It is.
- the relative dielectric constant of the first insulating layer 4 is preferably 2 or more and 5 or less.
- the relative dielectric constant of the second insulating layer 5 is 3 or more, preferably 5 or more, and more preferably 20 or more, but is not limited thereto.
- the first insulating layer 4 and the second insulating layer 5 are formed using a vacuum film-forming method such as a vacuum deposition method or a sputtering method, a sol-gel method using a metal complex or the like as a precursor, or nanoparticles.
- a vacuum film-forming method such as a vacuum deposition method or a sputtering method, a sol-gel method using a metal complex or the like as a precursor, or nanoparticles.
- a method of forming by a wet coating method such as a slit coating method, a spin coating method, screen printing, letterpress printing, or an ink jet method can be used, but the method is not limited to these, and a known general method can be used. .
- the gate electrode 2 and the capacitor electrode 3 are formed on the first insulating layer 4 and the second insulating layer 5.
- the gate electrode 2 and the capacitor electrode 3 can be formed by the same material and method as the source electrode 6 and the drain electrode 7 described above.
- the interlayer insulating film 10 In an image display device using the organic thin film transistor 160, the interlayer insulating film 10, the pixel electrode 11, a display element (not shown), a counter electrode (not shown), and a counter substrate (not shown) are preferably provided.
- the interlayer insulating film 10 mainly prevents gate-drain and capacitor-drain leakage through the pixel electrode 9 by insulating the gate electrode 2 and capacitor electrode 3 from the pixel electrode 9. It is formed.
- Examples of the material for the interlayer insulating film 10 include inorganic materials such as silicon oxide, aluminum oxide, tantalum oxide, yttrium oxide, hafnium oxide, hafnium aluminate, zirconium oxide, and titanium oxide, or polyacrylates such as PMMA (polymethyl methacrylate). Insulating materials such as PVA (polyvinyl alcohol), PVP (polyvinylphenol), and fluorine-based resin are not limited thereto.
- the resistivity is 10 11 ⁇ cm or more, more preferably 10 14 ⁇ cm or more.
- the interlayer insulating film 10 is formed by any one of an inkjet method, a relief printing method, a planographic printing method, an intaglio printing method, and a screen printing method using a solution in which a protective layer material or a precursor thereof is dissolved or dispersed.
- the These interlayer insulating films 9 may be used as a single layer or may be used by stacking two or more layers. Further, the composition may be inclined in the growth direction.
- the pixel electrode 11 is formed for the purpose of improving the aperture ratio of the image display device.
- the pixel electrode 11 includes aluminum (Al), copper (Cu), molybdenum (Mo), silver (Ag), chromium (Cr), titanium (Ti), gold (Au), platinum (Pt), tungsten (W), Metal materials such as manganese (Mn) and conductive metal oxide materials such as indium oxide (InO), tin oxide (SnO), zinc oxide (ZnO), indium tin oxide (ITO), and indium zinc oxide (IZO) Although it can be used, it is not limited to these. These materials may be used as a single layer, or may be used as a laminate or an alloy.
- the pixel electrode 11 can be formed by vacuum film-forming methods such as vacuum deposition and sputtering, sol-gel methods using a precursor of a conductive material, a method using nanoparticles, screen printing by converting them into ink, A method of forming by a wet film forming method such as letterpress printing or an ink jet method can be used, but the method is not limited to these, and a known general method can be used. Patterning can be performed by, for example, protecting a pattern forming portion with a resist or the like using a photolithography method and removing an unnecessary portion by etching, or patterning directly using a printing method or the like. Also, the method is not limited to these methods, and a known general patterning method can be used.
- liquid crystal electrophoretic particles, microcapsules containing electrophoretic particles, organic electroluminescence, or the like can be used.
- the image display apparatus it is possible to use these known general display elements without being limited to either a reflection type or a transmission type. Further, depending on the display element to be used, it is possible to use a configuration in which a plurality of organic thin film transistors 160 are installed in one pixel.
- the display element may be formed on the counter substrate on which the counter electrode is formed, and then combined with the organic thin film transistor 160 formed up to the pixel electrode 11 to form an image display device. After the display element is formed on the pixel electrode 11, the counter electrode The counter substrate may be stacked to form an image display device, and the process can be selected in accordance with the display element to be used.
- FIG. 8 is a schematic sectional view showing an organic thin film transistor 170 according to the eighth embodiment of the present invention.
- the difference between the organic thin film transistor 160 and the organic thin film transistor 170 is a region where the second insulating layer 5 is formed.
- the first insulating layer 4 is laminated so as to cover the semiconductor layer 8.
- the second insulating layer 5 is laminated on the first insulating layer 4 so as to cover the source electrode 6, the semiconductor layer 8, and a part of the drain electrode 7.
- the thickness of the capacitor portion formed by the drain electrode 7 and the capacitor electrode 3 can be reduced in the transistor portion where the semiconductor layer 8 is formed. Since it can be made thinner than the film thickness, it is possible to increase the capacitance of the capacitor while keeping the leakage current of the transistor portion low.
- FIG. 9 is a schematic cross-sectional view showing an organic thin film transistor 180 according to a ninth embodiment of the present invention.
- the difference between the organic thin film transistor 160 and the organic thin film transistor 180 is the thickness of the first insulating layer 4 and the second insulating layer 5 and the material used for the second insulating layer 5.
- the second insulating layer 5 is formed so as to cover a part of the drain electrode 7, and the film thickness thereof is thinner than that of the first insulating layer 4.
- the second insulating layer 5 is formed of a material having a higher dielectric constant than that of the first insulating layer 4.
- the capacitance of the capacitor can be further increased.
- Example 1 an organic thin film transistor 100 shown in FIG. 1
- Non-alkali glass with a thickness of 0.7 mm was used as the substrate 1.
- Molybdenum (Mo) was formed into a film thickness of 400 nm on the glass substrate 1 using DC magnetron sputtering, and was patterned into a desired shape by a photolithography method to obtain a gate electrode 2 and a capacitor electrode 3.
- a photosensitive acrylic resin is applied to the substrate on which the gate electrode 2 and the capacitor electrode 3 are formed by a slit coat method, exposed and developed, patterned into a desired shape, baked at 200 ° C., and the second insulating layer 5 Formed. Thereafter, the first insulating layer 4 was formed in the same manner as the second insulating layer 5.
- the film thickness of the first insulating layer 4 was 1 ⁇ m
- the film thickness of the second insulating layer 5 was 0.5 ⁇ m.
- the relative permittivity of the photosensitive acrylic resin is 3.4.
- a solution in which silver nanoparticles were dispersed was used as an ink, and was patterned into a desired shape using an ink jet method, and baked at 150 ° C. for 1 hour to form a source electrode 6 and a drain electrode 7.
- Example 2 an organic thin film transistor 110 shown in FIG.
- Non-alkali glass with a thickness of 0.7 mm was used as the substrate 1.
- Mo was formed into a film having a thickness of 400 nm by using DC magnetron sputtering, and patterned into a desired shape by a photolithography method to form the gate electrode 2 and the capacitor electrode 3.
- Aluminum oxide (Al 2 O 3 ) was formed to a thickness of 50 nm on the substrate 1 on which the gate electrode 2 and the capacitor electrode 3 were formed using an atomic layer deposition (ALD) method. Thereafter, a photosensitive acrylic resin is applied by a slit coating method, patterned by a photolithography method, and baked at 200 ° C., so that a region to be the first insulating layer 4 has a laminated structure of aluminum oxide and a photosensitive acrylic resin. The region to be the second insulating layer 5 was formed to be a layer made only of aluminum oxide. The film thickness of the photosensitive acrylic resin is 1 ⁇ m. Note that an unnecessary aluminum oxide layer such as an electrode extraction portion was removed by using a photolithography method and a dry etching method. The relative dielectric constant of aluminum oxide is 9.3, and the relative dielectric constant of the photosensitive acrylic resin is 3.4.
- the ink in which the silver nanoparticles were dispersed was patterned into a desired shape using an ink jet method, and baked at 150 ° C. for 1 hour to form the source electrode 6 and the drain electrode 7.
- Example 3 an organic thin film transistor 120 shown in FIG.
- Non-alkali glass with a thickness of 0.7 mm was used as the substrate 1.
- Mo was formed into a film having a thickness of 400 nm by using DC magnetron sputtering, and patterned into a desired shape by a photolithography method to form the gate electrode 2 and the capacitor electrode 3.
- a photosensitive polystyrene resin was applied to the substrate 1 on which the gate electrode 2 and the capacitor electrode 3 were formed by a slit coating method, patterned by a photolithography method, and baked at 200 ° C. to form a first insulating layer 4.
- a photosensitive acrylic resin having a different dielectric constant from that of Examples 1 and 2 was applied and patterned by photolithography to form a second insulating layer 5.
- the film thicknesses of the first insulating layer 4 and the second insulating layer 5 are both 1 ⁇ m.
- the relative dielectric constant of the first insulating layer 4 is 2.5, and the relative dielectric constant of the second insulating layer is 4.2.
- the ink in which the silver nanoparticles were dispersed was patterned into a desired shape using an ink jet method, and baked at 150 ° C. for 1 hour to form the source electrode 6 and the drain electrode 7.
- Example 4 an organic thin film transistor 130 shown in FIG.
- Non-alkali glass with a thickness of 0.7 mm was used as the substrate 1.
- Molybdenum (Mo) was formed into a film thickness of 400 nm on the glass substrate 1 using DC magnetron sputtering, and patterned into a desired shape by a photolithography method to form the gate electrode 2 and the capacitor electrode 3.
- a photosensitive silicone resin is applied to the substrate 1 on which the gate electrode 2 and the capacitor electrode 3 are formed by a slit coating method, exposed and developed, patterned into a desired shape, and baked at 200 ° C. to form a first insulating layer 4 was formed. Thereafter, the second insulating layer 5 was formed in the same manner as the first insulating layer 4.
- the film thicknesses of the first insulating layer 4 and the second insulating layer 5 were both 1 ⁇ m.
- the relative dielectric constant of the first insulating layer 4 is 2.5
- the relative dielectric constant of the second insulating layer 5 is 4.2.
- a solution in which silver nanoparticles were dispersed was used as an ink, and was patterned into a desired shape using an ink jet method, and baked at 180 ° C. for 1 hour to form a source electrode 6 and a drain electrode 7.
- Example 5 an organic thin film transistor 140 shown in FIG.
- Non-alkali glass with a thickness of 0.7 mm was used as the substrate 1.
- Mo was formed into a film having a thickness of 400 nm by using DC magnetron sputtering, and patterned into a desired shape by a photolithography method to form the gate electrode 2 and the capacitor electrode 3.
- Aluminum oxide (Al 2 O 3 ) was formed to a thickness of 100 nm on the substrate 1 on which the gate electrode 2 and the capacitor electrode 3 were formed by using an atomic layer deposition method (ALD method). Thereafter, a photosensitive silicone resin is applied by a slit coating method, patterned by a photolithography method, and baked at 200 ° C., so that a region to be the first insulating layer 4 has a laminated structure of aluminum oxide and a photosensitive acrylic resin. The region to be the second insulating layer 5 on the capacitor electrode 3 was formed to be a layer made only of aluminum oxide. The film thickness of the photosensitive acrylic resin is 1 ⁇ m. Note that an unnecessary aluminum oxide layer such as an electrode extraction portion was removed by using a photolithography method and a dry etching method. The relative dielectric constant of aluminum oxide is 9.3, and the relative dielectric constant of photosensitive silicone resin is 2.5.
- the ink in which the silver nanoparticles were dispersed was patterned into a desired shape using an ink jet method, and baked at 180 ° C. for 1 hour to form the source electrode 6 and the drain electrode 7.
- Example 6 an organic thin film transistor 150 shown in FIG.
- Non-alkali glass with a thickness of 0.7 mm was used as the substrate 1.
- Mo was formed into a film having a thickness of 400 nm by using DC magnetron sputtering, and patterned into a desired shape by a photolithography method to form the gate electrode 2 and the capacitor electrode 3.
- a photosensitive silicone resin was applied to the substrate 1 on which the gate electrode 2 and the capacitor electrode 3 were formed by a slit coating method, patterned by a photolithography method, and baked at 200 ° C. to form a first insulating layer 4.
- the film thickness of the first insulating layer 4 was 1 ⁇ m on the gate electrode 2 and 0.5 ⁇ m on the capacitor electrode 3.
- a photosensitive acrylic resin was applied and patterned by photolithography to form the second insulating layer 5 with a thickness of 0.5 ⁇ m.
- the relative dielectric constant of the first insulating layer 4 is 2.5
- the relative dielectric constant of the second insulating layer 5 is 4.2.
- the ink in which the silver nanoparticles were dispersed was patterned into a desired shape using an ink jet method, and baked at 180 ° C. for 1 hour to form the source electrode 6 and the drain electrode 7.
- Example 7 an organic thin film transistor 160 shown in FIG.
- Non-alkali glass with a thickness of 0.7 mm was used as the substrate 1.
- a solution in which silver (Ag) nanoparticles are dispersed on a glass substrate 1 is used as an ink, and is patterned into a desired shape using an ink-jet method, followed by baking at 150 ° C. for 1 hour, and the source electrode 6 and the drain electrode 7 are formed. Formed.
- a mesitylene solution in which poly (3-hexylthiophene) as an organic semiconductor material is dissolved at a concentration of 0.1% by weight is patterned on the substrate 1 on which the source electrode 6 and the drain electrode 7 are formed, thereby forming a semiconductor layer 8. did.
- the second insulating layer 5 was formed so as to be thinner than the first insulating layer 4.
- the film thickness of the first insulating layer 4 was 1 ⁇ m
- the film thickness of the second insulating layer 5 was 0.5 ⁇ m.
- the relative dielectric constant of the resin used is 2.0.
- Example 8 an organic thin film transistor 170 shown in FIG.
- Non-alkali glass with a thickness of 0.7 mm was used as the substrate 1.
- a solution in which silver (Ag) nanoparticles are dispersed on a glass substrate 1 is used as an ink, and is patterned into a desired shape using an ink-jet method, followed by baking at 150 ° C. for 1 hour, and the source electrode 6 and the drain electrode 7 are formed. Formed.
- a mesitylene solution in which poly (3-hexylthiophene) as an organic semiconductor material is dissolved at a concentration of 0.1% by weight is patterned on the substrate 1 on which the source electrode 6 and the drain electrode 7 are formed, thereby forming a semiconductor layer 8. did.
- a fluororesin was applied with a film thickness of 1 ⁇ m by an inkjet method so as to cover a part of the semiconductor layer 8, the source electrode 6, and the drain electrode 7, thereby forming the first insulating layer 4.
- aluminum oxide Al 2 O 3
- ALD method atomic layer volume method
- the ink in which the silver nanoparticles were dispersed was patterned into a desired shape using an ink jet method, and baked at 150 ° C. for 1 hour to form the gate electrode 2 and the capacitor electrode 3.
- Example 9 an organic thin film transistor 180 shown in FIG.
- Non-alkali glass with a thickness of 0.7 mm was used as the substrate 1.
- a solution in which silver (Ag) nanoparticles are dispersed on a glass substrate 1 is used as an ink, and is patterned into a desired shape using an ink-jet method, followed by baking at 150 ° C. for 1 hour, and the source electrode 6 and the drain electrode 7 are formed. Formed.
- the second insulating layer 5 was formed by removing using a dry etching method.
- the relative dielectric constant of the second insulating layer 5 is 9.3.
- a mesitylene solution in which poly (3-hexylthiophene) as an organic semiconductor material is dissolved at a concentration of 0.1% by weight as an organic semiconductor material so as to cover a part of the source electrode 6, the drain electrode 7, and the substrate 1 is formed by an inkjet method.
- the semiconductor layer 8 was formed by patterning.
- the relative dielectric constant of the first insulating layer 4 is 2.0.
- the ink in which the silver nanoparticles were dispersed was patterned into a desired shape using an ink jet method, and baked at 150 ° C. for 1 hour to form the gate electrode 2 and the capacitor electrode 3.
- Comparative Example 1 As Comparative Example 1, an organic thin film transistor 200 shown in FIG.
- Non-alkali glass with a thickness of 0.7 mm was used as the substrate 1.
- Mo was formed into a film having a thickness of 400 nm by using DC magnetron sputtering, and patterned into a desired shape by a photolithography method to form the gate electrode 2 and the capacitor electrode 3.
- a photosensitive acrylic resin having a dielectric constant different from that of Examples 1 to 3 is applied to the substrate 1 on which the gate electrode 2 and the capacitor electrode 3 are formed by a slit coating method, patterned by a photolithography method, and baked at 200 ° C. Only the first insulating layer 4 was formed on the gate electrode 2 and the capacitor electrode 3.
- the film thickness of the first insulating layer 4 is 1 ⁇ m, and the relative dielectric constant is 3.3.
- the ink in which the silver nanoparticles were dispersed was patterned into a desired shape using an ink jet method, and baked at 150 ° C. for 1 hour to form the source electrode 6 and the drain electrode 7.
- Comparative Example 2 As Comparative Example 2, an organic thin film transistor 210 shown in FIG.
- Non-alkali glass with a thickness of 0.7 mm was used as the substrate 1.
- Mo was formed into a film having a thickness of 400 nm by using DC magnetron sputtering, and patterned into a desired shape by a photolithography method to form the gate electrode 2 and the capacitor electrode 3.
- Photosensitive silicone resin is applied to the substrate 1 on which the gate electrode 2 and the capacitor electrode 3 are formed by slit coating, patterned by photolithography, and baked at 200 ° C. Only one insulating layer 4 was formed.
- the film thickness of the first insulating layer 4 is 1 ⁇ m and the relative dielectric constant is 2.5.
- the ink in which the silver nanoparticles were dispersed was patterned into a desired shape using an ink jet method, and baked at 180 ° C. for 1 hour to form the source electrode 6 and the drain electrode 7.
- Comparative Example 3 As Comparative Example 3, an organic thin film transistor 220 shown in FIG.
- Non-alkali glass with a thickness of 0.7 mm was used as the substrate 1.
- a solution in which silver (Ag) nanoparticles are dispersed on a glass substrate 1 is used as an ink, and is patterned into a desired shape using an ink-jet method, followed by baking at 150 ° C. for 1 hour, and the source electrode 6 and the drain electrode 7 are formed. Formed.
- a mesitylene solution in which poly (3-hexylthiophene) as an organic semiconductor material is dissolved at a concentration of 0.1% by weight is patterned on the substrate 1 on which the source electrode 6 and the drain electrode 7 are formed, thereby forming a semiconductor layer 8. did.
- a fluororesin was applied with a film thickness of 1 ⁇ m by a slit coating method so as to cover the semiconductor layer 8, the source electrode 6, and the drain electrode 7, thereby forming the first insulating layer 4.
- the relative dielectric constant of the first insulating layer 4 is 2.0.
- the ink in which the silver nanoparticles were dispersed was patterned into a desired shape using an ink jet method, and baked at 150 ° C. for 1 hour to form the gate electrode 2 and the capacitor electrode 3.
- Example 1 the capacitance of the capacitor could be doubled compared to the organic thin film transistor 200 by making the thickness of the second insulating layer 5 about half that of the first insulating layer 4.
- Example 2 by using a film having a high dielectric constant for the second insulating layer 5, the capacitance of the capacitor could be significantly increased as compared with the organic thin film transistor 200.
- Example 3 the capacitance of the capacitor is increased as compared with the organic thin film transistor 200 by selecting the second insulating layer 5 having a relative dielectric constant higher than that of the first insulating layer 4. I was able to.
- by increasing the capacitance of the capacitor it is possible to improve the holding ratio of the writing voltage of the image display device and to drive the image display device stably.
- Example 4 the capacitance of the capacitor could be 1.6 times that of the organic thin film transistor 210 by using the second insulating layer 5 having a dielectric constant larger than that of the first insulating layer 4. .
- Example 5 by using a film having a high dielectric constant for the second insulating layer 5, the capacitance of the capacitor could be significantly increased by about 75 times compared to the organic thin film transistor 210.
- Example 6 by selecting a material having a relative dielectric constant of the second insulating layer 5 higher than that of the first insulating layer 4, the capacitance of the capacitor is about 1 compared with that of the organic thin film transistor 210. It was possible to increase it 6 times. In any of the embodiments, by increasing the capacitance of the capacitor, it is possible to improve the holding ratio of the writing voltage of the image display device and to drive the image display device stably.
- Example 7 the capacitance of the capacitor could be doubled compared to the organic thin film transistor 220 by making the film thickness of the second insulating layer 5 about half that of the first insulating layer 4.
- Example 8 by using a film having a high dielectric constant for the second insulating layer 5, the capacitance of the capacitor could be significantly increased as compared with the organic thin film transistor 220.
- Example 9 the capacitance of the capacitor is increased as compared with the organic thin film transistor 220 by selecting the second insulating layer 5 having a higher relative dielectric constant than that of the first insulating layer 4. I was able to.
- by increasing the capacitance of the capacitor it is possible to improve the holding ratio of the writing voltage of the image display device and to drive the image display device stably.
- the dielectric constant of the second insulating layer 5 formed between the capacitor electrode 3 and the drain electrode 7 is increased, so that the leakage current in the thin film transistor can be suppressed and the capacitor can be kept low.
- the capacity can be increased.
- the present invention can be suitably used for an image display device and various sensors.
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Abstract
Provided are: an organic thin film transistor which is produced with use of a printing method, and which is able to be stably driven by ensuring the capacitance of a capacitor and thereby maintaining the voltage holding ratio even in cases where a sufficient capacitor electrode area is not able to be ensured; and an image display device.
This organic thin film transistor has, on an insulating substrate, at least a gate electrode, a capacitor electrode, a first insulating layer that is formed so as to cover at least the gate electrode, a second insulating layer that is formed so as to cover at least a part of the capacitor electrode, a source electrode, a drain electrode and a semiconductor layer that contains an organic semiconductor material. This organic thin film transistor is configured such that the film thickness of the second insulating layer is thinner than the film thickness of the first insulating layer.
Description
本発明は、有機薄膜トランジスタおよび画像表示装置に関するものである。
The present invention relates to an organic thin film transistor and an image display device.
薄膜トランジスタは液晶表示装置(LCD)、有機エレクトロルミネッセンス(EL)表示装置、電子ペーパー表示装置などの、アクティブマトリクス方式の表示装置やセンサーなどに広く使用されている。
Thin film transistors are widely used in active matrix display devices and sensors such as liquid crystal display devices (LCD), organic electroluminescence (EL) display devices, and electronic paper display devices.
薄膜トランジスタに用いられる半導体材料としては、非晶質シリコンや多結晶シリコンあるいは酸化物半導体などを用いたものが主流となっており、これらの半導体材料を用いた薄膜トランジスタは、真空成膜法を用いて成膜した後にフォトリソグラフィ法などによりパターニングを行い製造されることが一般的である。
As semiconductor materials used for thin film transistors, those using amorphous silicon, polycrystalline silicon, oxide semiconductors, and the like have become mainstream, and thin film transistors using these semiconductor materials are formed using a vacuum film formation method. In general, after film formation, patterning is performed by a photolithography method or the like.
近年、半導体層として有機材料を用いた有機薄膜トランジスタが注目を集めている。有機薄膜トランジスタにおいては、半導体材料、導電性材料および絶縁性材料などの溶液を塗布・印刷技術などのウェット成膜法を用いることにより、低温でのプラスチック基板上へのデバイス形成、および低コストでのデバイス製造の可能性があることや、印刷法は成膜とパターニングの工程を同時に行うことから、従来のフォトリソグラフィプロセスを用いる真空成膜プロセスと比較して、材料利用効率が高く、現像、エッチング工程を必要としないことから、環境負荷が少ないという点でも期待されている。
In recent years, organic thin-film transistors using organic materials as semiconductor layers have attracted attention. In organic thin-film transistors, devices such as semiconductor materials, conductive materials and insulating materials can be formed on plastic substrates at low temperatures by using wet film formation methods such as coating and printing techniques, and at low cost. Since there is a possibility of device manufacturing and the printing method performs film formation and patterning processes at the same time, the material utilization efficiency is high compared to the vacuum film formation process using the conventional photolithography process, and development and etching are performed. Since no process is required, it is also expected to have a low environmental impact.
有機薄膜トランジスタの印刷法による形成においては、薄膜トランジスタの各層の特徴に合わせて様々な印刷方法が用いられるが、従来のフォトリソグラフィプロセスと比較してアライメント精度やパターニング精度の面で劣るため、トランジスタの製造歩留まりを考慮して、薄膜トランジスタの各層の寸法に余裕を持たせて設計することが好ましい。
In the formation of organic thin-film transistors by printing methods, various printing methods are used according to the characteristics of each layer of the thin-film transistors. However, since they are inferior in alignment accuracy and patterning accuracy compared to conventional photolithography processes, transistor manufacturing In consideration of the yield, it is preferable to design with a margin in the dimensions of each layer of the thin film transistor.
しかしながら、寸法に余裕を持たせて設計すると、薄膜トランジスタ部の面積が大きくなるため、高精細の薄膜トランジスタパターンを作製することが困難となる。また、薄膜トランジスタ部の面積が大きくなることにより、薄膜トランジスタを用いたアクティブマトリクス方式の画像表示装置などの駆動の補助容量として機能するキャパシタ電極の面積が制限されるため、十分な容量を得ることが困難となる。
However, if the design is made with a sufficient size, the area of the thin film transistor portion becomes large, and it becomes difficult to produce a high-definition thin film transistor pattern. In addition, since the area of the thin film transistor portion is increased, the area of the capacitor electrode that functions as an auxiliary capacitor for driving an active matrix image display device using a thin film transistor is limited, so that it is difficult to obtain a sufficient capacity. It becomes.
アクティブマトリクス方式の画像表示装置において、薄膜トランジスタに設置されるキャパシタは、各画素の書込み時において、電圧保持を補助する役割を担っており、容量が不足すると選択時間における電圧保持率が低下するため、書込み電圧を高くする、もしくは書込み回数を多くするなどの対策が必要となり、結果的に、画像表示装置の書込み時間の増加や消費電力の増大を招くこととなる。
In an active matrix image display device, a capacitor installed in a thin film transistor plays a role of assisting voltage holding at the time of writing of each pixel, and if the capacity is insufficient, the voltage holding ratio at the selection time decreases. Measures such as increasing the writing voltage or increasing the number of writings are required, and as a result, the writing time and power consumption of the image display device are increased.
本発明は、以上の点を鑑みなされたものであり、印刷法を用いて製造された有機薄膜トランジスタにおいて、十分なキャパシタ電極面積が確保できない場合においても、キャパシタの静電容量を確保することで、電圧保持率を維持し、安定的に駆動可能な有機薄膜トランジスタおよび画像表示装置を提供することを目的とする。
The present invention has been made in view of the above points, and in an organic thin film transistor manufactured using a printing method, even when a sufficient capacitor electrode area cannot be ensured, by securing the capacitance of the capacitor, An object of the present invention is to provide an organic thin film transistor and an image display device which can maintain a voltage holding ratio and can be stably driven.
The present invention has been made in view of the above points, and in an organic thin film transistor manufactured using a printing method, even when a sufficient capacitor electrode area cannot be ensured, by securing the capacitance of the capacitor, An object of the present invention is to provide an organic thin film transistor and an image display device which can maintain a voltage holding ratio and can be stably driven.
上記課題を解決するための本発明の一局面は、絶縁性の基板上に少なくともゲート電極と、キャパシタ電極と、少なくともゲート電極を覆うように形成された第一の絶縁層と、少なくともキャパシタ電極の一部を覆うように形成された第二の絶縁層と、ソース電極と、ドレイン電極と、有機半導体材料を含む半導体層を有する有機薄膜トランジスタであって、第二の絶縁層の膜厚が、第一の絶縁膜の膜厚よりも薄く形成されている、有機薄膜トランジスタである。
One aspect of the present invention for solving the above problems includes at least a gate electrode, a capacitor electrode, a first insulating layer formed so as to cover at least the gate electrode, and at least a capacitor electrode on an insulating substrate. An organic thin film transistor having a second insulating layer formed so as to cover a part, a source electrode, a drain electrode, and a semiconductor layer containing an organic semiconductor material, wherein the thickness of the second insulating layer is This is an organic thin film transistor formed thinner than the thickness of one insulating film.
また、本発明の他の局面は、絶縁性の基板上に少なくともゲート電極と、キャパシタ電極と、少なくとも前記ゲート電極を覆うように形成された第一の絶縁層と、少なくともキャパシタ電極の一部を覆うように形成された第二の絶縁層と、ソース電極と、ドレイン電極と、有機半導体材料を含む半導体層を有する有機薄膜トランジスタであって、第二の絶縁層の誘電率が第一の絶縁層の誘電率よりも大きい、有機薄膜トランジスタである。
In another aspect of the present invention, at least a gate electrode, a capacitor electrode, a first insulating layer formed to cover at least the gate electrode, and at least a part of the capacitor electrode are formed on an insulating substrate. An organic thin film transistor having a second insulating layer formed to cover, a source electrode, a drain electrode, and a semiconductor layer containing an organic semiconductor material, wherein the dielectric constant of the second insulating layer is the first insulating layer It is an organic thin film transistor having a dielectric constant greater than
また、第一の絶縁層は絶縁材料を2層以上積層して形成してもよい。
The first insulating layer may be formed by stacking two or more insulating materials.
また、第二の絶縁層は絶縁材料を2層以上積層して形成してもよい。
The second insulating layer may be formed by stacking two or more insulating materials.
また、第二の絶縁層が多層からなっていれば、その層の一部を第一の絶縁層と同じ材料および組成で形成してもよい。
If the second insulating layer is composed of multiple layers, a part of the layer may be formed of the same material and composition as the first insulating layer.
また、本発明の他の局面は、絶縁性の基板上に少なくともソース電極と、ドレイン電極と、有機半導体材料を含む半導体層と、ソース電極および半導体層を覆うように形成された第一の絶縁層と、少なくともドレイン電極の一部を覆うように形成された第二の絶縁層と、ゲート電極と、キャパシタ電極と、を有する有機薄膜トランジスタであって、第二の絶縁層の膜厚が、第一の絶縁層の膜厚よりも薄いことを特徴とする、有機薄膜トランジスタである。
According to another aspect of the present invention, there is provided a first insulation formed on an insulating substrate so as to cover at least a source electrode, a drain electrode, a semiconductor layer containing an organic semiconductor material, and the source electrode and the semiconductor layer. An organic thin film transistor having a layer, a second insulating layer formed so as to cover at least a part of the drain electrode, a gate electrode, and a capacitor electrode, wherein the second insulating layer has a film thickness of It is an organic thin film transistor characterized by being thinner than the thickness of one insulating layer.
また、第二の絶縁層の誘電率が、第一の絶縁層の誘電率よりも大きくてもよい。
Further, the dielectric constant of the second insulating layer may be larger than the dielectric constant of the first insulating layer.
また、第一の絶縁層は、絶縁材料を2層以上積層して形成してもよい。
Further, the first insulating layer may be formed by stacking two or more insulating materials.
また、第二の絶縁層は、絶縁材料を2層以上積層して形成してもよい。
The second insulating layer may be formed by stacking two or more insulating materials.
また、本発明の他の局面は、上述の有機薄膜トランジスタを用いた画像表示装置である。
Further, another aspect of the present invention is an image display device using the above-described organic thin film transistor.
本発明によれば、印刷法を用いて製造された有機薄膜トランジスタにおいて、十分なキャパシタ電極面積が確保できない場合においても、キャパシタの静電容量を確保することで、電圧保持率を維持し、安定して駆動可能な素子特性を示す有機薄膜トランジスタおよび画像表示装置を提供することが可能となる。
According to the present invention, in an organic thin film transistor manufactured using a printing method, even when a sufficient capacitor electrode area cannot be secured, the voltage holding ratio is maintained and stabilized by securing the capacitance of the capacitor. Thus, it is possible to provide an organic thin film transistor and an image display device that exhibit device characteristics that can be driven.
以下、本発明の実施の形態を、図面を参照しつつ、説明する。なお各実施の形態において、同一または対応する構成要素については同一の符号を付け、実施の形態の間において重複する説明は省略する。
Hereinafter, embodiments of the present invention will be described with reference to the drawings. In each embodiment, the same or corresponding components are denoted by the same reference numerals, and redundant description among the embodiments is omitted.
(第1の実施形態)
図1は、本発明の第1の実施の形態に係る有機薄膜トランジスタ100を示す概略断面図である。 (First embodiment)
FIG. 1 is a schematic cross-sectional view showing an organicthin film transistor 100 according to a first embodiment of the present invention.
図1は、本発明の第1の実施の形態に係る有機薄膜トランジスタ100を示す概略断面図である。 (First embodiment)
FIG. 1 is a schematic cross-sectional view showing an organic
有機薄膜トランジスタ100は、絶縁性の基板1の上に形成されたゲート電極2とキャパシタ電極3と、少なくともゲート電極2を覆うように形成された第一の絶縁層4と、少なくともキャパシタ電極3の一部を覆うように形成された第二の絶縁層5と、ソース電極6とドレイン電極7と、有機半導体材料からなる半導体層8を少なくとも備えている。また半導体層8を保護するための保護層9も好適に用いられる。
The organic thin film transistor 100 includes a gate electrode 2 and a capacitor electrode 3 formed on an insulating substrate 1, a first insulating layer 4 formed so as to cover at least the gate electrode 2, and at least one capacitor electrode 3. At least a second insulating layer 5 formed so as to cover the portion, a source electrode 6 and a drain electrode 7, and a semiconductor layer 8 made of an organic semiconductor material. A protective layer 9 for protecting the semiconductor layer 8 is also preferably used.
また、有機薄膜トランジスタ100に層間絶縁膜10と、画素電極11と、図示しない表示要素と、図示しない対向電極と、図示しない第二の基板とを設けることにより、画像表示装置とすることができる。対向電極および第二の基板は使用する表示要素の種類によりその構造は適宜変更することができる。
Further, by providing the organic thin film transistor 100 with the interlayer insulating film 10, the pixel electrode 11, a display element (not shown), a counter electrode (not shown), and a second substrate (not shown), an image display device can be obtained. The structure of the counter electrode and the second substrate can be appropriately changed depending on the type of display element used.
以下、有機薄膜トランジスタ100の各構成要素について、有機薄膜トランジスタ100の製造工程に沿って説明する。
Hereinafter, each component of the organic thin film transistor 100 will be described along the manufacturing process of the organic thin film transistor 100.
初めに、基板1を準備する。基板1の材料としては、ポリカーボネート、ポリエチレンサルファイド、ポリエーテルスルホン、ポリエチレンテレフタレート、ポリエチレンナフタレート、シクロオレフィンポリマー、トリアセチルセルロース、ポリビニルフルオライドフィルム、エチレン-テトラフルオロエチレン共重合樹脂、耐候性ポリエチレンテレフタレート、耐候性ポリプロピレン、ガラス繊維強化アクリル樹脂フィルム、ガラス繊維強化ポリカーボネート、ポリイミド、フッ素系樹脂、環状ポリオレフィン系樹脂、ガラス、石英ガラスなどを使用することができるが、これらに限定されるものではない。これらは単独で使用してもよいが、2種以上を積層した複合の基板1として使用することもできる。
First, the substrate 1 is prepared. As the material of the substrate 1, polycarbonate, polyethylene sulfide, polyethersulfone, polyethylene terephthalate, polyethylene naphthalate, cycloolefin polymer, triacetyl cellulose, polyvinyl fluoride film, ethylene-tetrafluoroethylene copolymer resin, weather resistant polyethylene terephthalate, Weatherable polypropylene, glass fiber reinforced acrylic resin film, glass fiber reinforced polycarbonate, polyimide, fluorine resin, cyclic polyolefin resin, glass, quartz glass, and the like can be used, but are not limited thereto. These may be used alone, but can also be used as a composite substrate 1 in which two or more kinds are laminated.
基板1が有機物フィルムである場合は、有機薄膜トランジスタ100の耐久性を向上させるために透明のガスバリア層(図示せず)を形成することもできる。ガスバリア層としては酸化アルミニウム(Al2O3)、酸化珪素(SiO)、窒化珪素(SiN)、酸化窒化珪素(SiON)、炭化珪素(SiC)およびダイヤモンドライクカーボン(DLC)などが挙げられるがこれらに限定されるものではない。また、これらのガスバリア層は2層以上積層して使用することもできる。ガスバリア層は有機物フィルムを用いた基板1の片面だけに形成してもよいし、両面に形成しても構わない。ガスバリア層は真空蒸着法、イオンプレーティング法、スパッタリング法、レーザーアブレーション法、プラズマCVD(Chemical Vapor Deposition)法、ホットワイヤーCVD法およびゾル-ゲル法などを用いて形成することができるが本発明ではこれらに限定されるものではない。
In the case where the substrate 1 is an organic film, a transparent gas barrier layer (not shown) can be formed to improve the durability of the organic thin film transistor 100. Examples of the gas barrier layer include aluminum oxide (Al 2 O 3 ), silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide (SiC), and diamond-like carbon (DLC). It is not limited to. These gas barrier layers can also be used by laminating two or more layers. The gas barrier layer may be formed only on one side of the substrate 1 using an organic film, or may be formed on both sides. The gas barrier layer can be formed using a vacuum deposition method, an ion plating method, a sputtering method, a laser ablation method, a plasma CVD (Chemical Vapor Deposition) method, a hot wire CVD method, a sol-gel method, and the like. It is not limited to these.
また、基板1上に形成されるゲート電極2およびキャパシタ電極3の基板1との密着性を向上させるために密着層を設けることもできるし、基板1表面に表面処理などを施しても良い。
Further, an adhesion layer can be provided in order to improve the adhesion between the gate electrode 2 and the capacitor electrode 3 formed on the substrate 1 and the substrate 1, or surface treatment or the like may be performed on the surface of the substrate 1.
次に、基板1上に、ゲート電極2及びキャパシタ電極3を形成する。ゲート電極2、キャパシタ電極3、ソース電極6およびドレイン電極7は、電極部分と配線部分とが明確に分かれている必要はなく、以下では特に各有機薄膜トランジスタの構成要素として電極と呼称している。
Next, the gate electrode 2 and the capacitor electrode 3 are formed on the substrate 1. The gate electrode 2, the capacitor electrode 3, the source electrode 6, and the drain electrode 7 do not need to be clearly separated from each other in the electrode portion and the wiring portion, and are hereinafter referred to as electrodes as components of each organic thin film transistor.
ゲート電極2およびキャパシタ電極3には、アルミニウム(Al)、銅(Cu)、モリブデン(Mo)、銀(Ag)、クロム(Cr)、チタン(Ti)、金(Au)、白金(Pt)、タングステン(W)、マンガン(Mn)などの金属材料や、酸化インジウム(InO)、酸化スズ(SnO)、酸化亜鉛(ZnO)、酸化インジウムスズ(ITO)、酸化インジウム亜鉛(IZO)などの導電性金属酸化物材料を用いることができるが、これらに限定されるものではない。これらの材料は単層で用いても構わないし、積層および合金として用いても構わない。
The gate electrode 2 and the capacitor electrode 3 include aluminum (Al), copper (Cu), molybdenum (Mo), silver (Ag), chromium (Cr), titanium (Ti), gold (Au), platinum (Pt), Metal materials such as tungsten (W) and manganese (Mn), and conductive materials such as indium oxide (InO), tin oxide (SnO), zinc oxide (ZnO), indium tin oxide (ITO), and indium zinc oxide (IZO) Although a metal oxide material can be used, it is not limited to these. These materials may be used as a single layer, or may be used as a laminate or an alloy.
ゲート電極2およびキャパシタ電極3の形成には、真空蒸着法、スパッタ法などの真空成膜法や、導電性材料の前駆体などを使用するゾル-ゲル法やナノ粒子を使用する方法、それらをインク化して、スクリーン印刷、凸版印刷、インクジェット法などのウェット成膜法で形成する方法などが使用できるが、これらに限定されず、公知一般の方法を用いることができる。パターニングは、例えばフォトリソグラフィ法を用いてパターン形成部分をレジストなどにより保護し、エッチングによって不要部分を除去して行うこともできるし、印刷法などを用いて直接パターニングすることもできるが、これについてもこれらの方法に限定されず、公知一般のパターニング方法を用いることができる。
The gate electrode 2 and the capacitor electrode 3 can be formed by vacuum film-forming methods such as vacuum deposition and sputtering, sol-gel methods using precursors of conductive materials, methods using nanoparticles, and the like. A method of forming an ink and forming it by a wet film forming method such as screen printing, letterpress printing, or an ink jet method can be used, but the method is not limited to these, and a known general method can be used. Patterning can be performed by, for example, protecting a pattern forming portion with a resist or the like using a photolithography method and removing an unnecessary portion by etching, or patterning directly using a printing method or the like. Also, the method is not limited to these methods, and a known general patterning method can be used.
次に、少なくともゲート電極2を覆うように第一の絶縁層4を形成する。
Next, a first insulating layer 4 is formed so as to cover at least the gate electrode 2.
第一の絶縁層4には、酸化珪素(SiOx)、酸化アルミニウム(AlOx)、酸化タンタル(TaOx)、酸化イットリウム(YOx)、酸化ジルコニウム(ZrOx)、酸化ハフニウム(HfOx)などの酸化物系絶縁材料や窒化珪素(SiNx)、酸化窒化珪素(SiON)や、ポリメチルメタクリレート(PMMA)等のポリアクリレート、ポリビニルアルコール(PVA)、ポリビニルフェノール(PVP)などの有機系絶縁材料や、自己組織化膜等の材料を使用することができるが、これらに限定されるものではない。これらは単層または2層以上積層してもよいし、無機系-有機系のハイブリッド薄膜としても良いし、成長方向に向けて組成を傾斜したものでも構わない。
The first insulating layer 4 includes oxide-based insulating materials such as silicon oxide (SiOx), aluminum oxide (AlOx), tantalum oxide (TaOx), yttrium oxide (YOx), zirconium oxide (ZrOx), and hafnium oxide (HfOx). Materials, organic insulating materials such as silicon nitride (SiNx), silicon oxynitride (SiON), polyacrylates such as polymethyl methacrylate (PMMA), polyvinyl alcohol (PVA), polyvinylphenol (PVP), and self-assembled films However, the present invention is not limited to these materials. These may be a single layer or a laminate of two or more layers, may be an inorganic-organic hybrid thin film, or may have a composition inclined in the growth direction.
第一の絶縁層4に自己組織化膜を用いる場合は、異なる自己組織化材料を積層する多層膜構造とすることで、絶縁層の誘電率や絶縁性を制御することが可能である。さらに、自己組織化した多層膜を繰り返し構造とすることで、絶縁性を高めることも可能である。また、第一の絶縁層4表面に形成される半導体層8の種類に合わせて表面の官能基を選択し、表面エネルギーを制御することで、有機薄膜トランジスタ100の性能を向上することも可能である。
When a self-assembled film is used for the first insulating layer 4, it is possible to control the dielectric constant and insulation of the insulating layer by using a multilayer film structure in which different self-assembled materials are laminated. Furthermore, it is also possible to improve insulation by making a self-assembled multilayer film into a repeated structure. It is also possible to improve the performance of the organic thin film transistor 100 by selecting the functional group on the surface according to the type of the semiconductor layer 8 formed on the surface of the first insulating layer 4 and controlling the surface energy. .
第一の絶縁層4は、有機薄膜トランジスタ100および画像表示装置200におけるリーク電流を抑えるために、その抵抗率が1011Ωcm以上、より好ましくは1014Ωcm以上であることが望ましい。
The first insulating layer 4 desirably has a resistivity of 10 11 Ωcm or more, more preferably 10 14 Ωcm or more, in order to suppress leakage current in the organic thin film transistor 100 and the image display device 200.
次に、キャパシタ電極3上に第二の絶縁層5を形成する。第二の絶縁層5は、少なくともキャパシタ電極3の一部を覆うように形成され、第二の絶縁層5上においてキャパシタ電極3と重畳するように形成されるドレイン電極7によってキャパシタ構造を成すことで、有機薄膜トランジスタ100を用いた画像表示装置のキャパシタとして機能する。なお、第一の絶縁層4及び第二の絶縁層5の形成は、この順序に限定されず、第二の絶縁層5を形成した後に第一の絶縁層4の形成を行ってもよい。
Next, the second insulating layer 5 is formed on the capacitor electrode 3. The second insulating layer 5 is formed so as to cover at least a part of the capacitor electrode 3, and forms a capacitor structure by the drain electrode 7 formed so as to overlap the capacitor electrode 3 on the second insulating layer 5. Thus, it functions as a capacitor of an image display device using the organic thin film transistor 100. The formation of the first insulating layer 4 and the second insulating layer 5 is not limited to this order, and the first insulating layer 4 may be formed after the second insulating layer 5 is formed.
第二の絶縁層5には、酸化珪素(SiOx)、酸化アルミニウム(AlOx)、酸化タンタル(TaOx)、酸化イットリウム(YOx)、酸化ジルコニウム(ZrOx)、酸化ハフニウム(HfOx)などの酸化物系絶縁材料や窒化珪素(SiNx)、酸化窒化珪素(SiON)や、ポリメチルメタクリレート(PMMA)等のポリアクリレート、ポリビニルアルコール(PVA)、ポリビニルフェノール(PVP)などの有機系絶縁材料や、自己組織化膜等の材料を使用することができるが、これらに限定されるものではない。これらは単層または2層以上積層してもよいし、無機系-有機系のハイブリッド薄膜としても良いし、成長方向に向けて組成を傾斜したものでも構わない。
The second insulating layer 5 includes oxide-based insulating materials such as silicon oxide (SiOx), aluminum oxide (AlOx), tantalum oxide (TaOx), yttrium oxide (YOx), zirconium oxide (ZrOx), and hafnium oxide (HfOx). Materials, organic insulating materials such as silicon nitride (SiNx), silicon oxynitride (SiON), polyacrylates such as polymethyl methacrylate (PMMA), polyvinyl alcohol (PVA), polyvinylphenol (PVP), and self-assembled films However, the present invention is not limited to these materials. These may be a single layer or a laminate of two or more layers, may be an inorganic-organic hybrid thin film, or may have a composition inclined in the growth direction.
第二の絶縁層5に自己組織化膜を用いる場合は、異なる自己組織化材料を積層する多層膜構造とすることで、絶縁層の誘電率や絶縁性を制御することが可能である。さらに、自己組織化した多層膜を繰り返し構造とすることで、絶縁性を高めることも可能である。
When a self-assembled film is used for the second insulating layer 5, it is possible to control the dielectric constant and insulation of the insulating layer by adopting a multilayer film structure in which different self-assembled materials are laminated. Furthermore, it is also possible to improve insulation by making a self-assembled multilayer film into a repeated structure.
第二の絶縁層5は、有機薄膜トランジスタ100および画像表示装置におけるリーク電流を抑えるために、その抵抗率が1011Ωcm以上、より好ましくは1014Ωcm以上であることが望ましい。
The second insulating layer 5 desirably has a resistivity of 10 11 Ωcm or more, more preferably 10 14 Ωcm or more, in order to suppress leakage current in the organic thin film transistor 100 and the image display device.
第二の絶縁層5は、有機薄膜トランジスタ100において、キャパシタ電極3およびドレイン電極7を絶縁することでキャパシタ構造を形成しており、キャパシタの容量を確保するために、その膜厚は第一の絶縁層4と比較して薄くすることが好ましい。有機薄膜トランジスタ100においては、第二の絶縁層5を第一の絶縁層4よりも薄膜で形成することにより、第一の絶縁層4におけるリーク電流を低く抑えながらキャパシタの静電容量を増加させることが可能となる。
The second insulating layer 5 forms a capacitor structure by insulating the capacitor electrode 3 and the drain electrode 7 in the organic thin film transistor 100. The film thickness of the second insulating layer 5 is the first insulating thickness in order to secure the capacitance of the capacitor. It is preferable to make it thinner than the layer 4. In the organic thin film transistor 100, the second insulating layer 5 is formed to be thinner than the first insulating layer 4, thereby increasing the capacitance of the capacitor while keeping the leakage current in the first insulating layer 4 low. Is possible.
第二の絶縁層5は、第一の絶縁層4と同様の材料および組成を用いてよいし、異なる材料を用いても良くこれらに限定されることなく、様々な組合せで形成することが可能である。
The second insulating layer 5 may use the same material and composition as the first insulating layer 4, or may use different materials and can be formed in various combinations without being limited thereto. It is.
第二の絶縁層5の材料に第一の絶縁層4よりも比誘電率の高い材料を用いることにより、キャパシタの静電容量を増加させることが可能となる。第一の絶縁層4の比誘電率は2以上、5以下であることが好ましい。また、第二の絶縁層5の比誘電率は、3以上、好ましくは5以上、さらに好ましくは、20以上であることが好ましいが、これらに限定されるものではない。
By using a material having a relative dielectric constant higher than that of the first insulating layer 4 as the material of the second insulating layer 5, the capacitance of the capacitor can be increased. The relative dielectric constant of the first insulating layer 4 is preferably 2 or more and 5 or less. The relative dielectric constant of the second insulating layer 5 is 3 or more, preferably 5 or more, and more preferably 20 or more, but is not limited thereto.
第一の絶縁層4および第二の絶縁層5の形成方法は、真空蒸着法、スパッタ法などの真空成膜法や、金属錯体などを前駆体として使用するゾル-ゲル法やナノ粒子を使用する方法、スリットコート法、スピンコート方、スクリーン印刷、凸版印刷、インクジェット法などのウェット成膜法で形成する方法などが使用できるが、これらに限定されず、公知一般の方法を用いることができる。
The first insulating layer 4 and the second insulating layer 5 are formed using a vacuum film-forming method such as a vacuum deposition method or a sputtering method, a sol-gel method using a metal complex or the like as a precursor, or nanoparticles. For example, a method of forming by a wet coating method such as a slit coating method, a spin coating method, screen printing, letterpress printing, or an ink jet method can be used, but the method is not limited to these, and a known general method can be used. .
次に、第一の絶縁層4および第二の絶縁層5上に、ソース電極6およびドレイン電極7を形成する。ソース電極6およびドレイン電極7は、先に示したゲート電極2およびキャパシタ電極3と同様の材料および方法によって形成することができる。
Next, the source electrode 6 and the drain electrode 7 are formed on the first insulating layer 4 and the second insulating layer 5. The source electrode 6 and the drain electrode 7 can be formed by the same material and method as the gate electrode 2 and the capacitor electrode 3 described above.
ソース電極6およびドレイン電極7については、半導体層8よりもソース電極6およびドレイン電極7を先に形成するボトムコンタクト構造としても良いし、半導体層8の形成後に、ソース電極6およびドレイン電極7を形成するトップコンタクト構造としても良い。
The source electrode 6 and the drain electrode 7 may have a bottom contact structure in which the source electrode 6 and the drain electrode 7 are formed before the semiconductor layer 8, or the source electrode 6 and the drain electrode 7 may be formed after the semiconductor layer 8 is formed. A top contact structure may be formed.
また、ボトムコンタクト構造を適用する場合においては、ソース電極6およびドレイン電極7は、半導体層8との電気的接続における接触抵抗を低下させるために、表面処理などを行うことができる。
In the case of applying the bottom contact structure, the source electrode 6 and the drain electrode 7 can be subjected to a surface treatment or the like in order to reduce contact resistance in electrical connection with the semiconductor layer 8.
次に、第一の絶縁層4、ソース電極6およびドレイン電極7上に半導体層8を形成する。半導体層8には、ペンタセン、およびそれらの誘導体のような低分子半導体やポリチオフェン、ポリアリルアミン、フルオレンビチオフェン共重合体、およびそれらの誘導体のような高分子有機半導体材料を用いることができるが、これらに限定されるものではない。
Next, a semiconductor layer 8 is formed on the first insulating layer 4, the source electrode 6 and the drain electrode 7. For the semiconductor layer 8, low molecular semiconductors such as pentacene and derivatives thereof, and polymer organic semiconductor materials such as polythiophene, polyallylamine, fluorenebithiophene copolymers, and derivatives thereof can be used. It is not limited to these.
半導体層8は、有機半導体材料を溶解または分散させた溶液をインクとして用いる凸版印刷、スクリーン印刷、インクジェット法、ノズルプリンティングなどのウェット成膜方法で形成することができるが、これらに限定されるものではなく、公知一般の方法を使用することも可能である。
The semiconductor layer 8 can be formed by a wet film forming method such as letterpress printing, screen printing, ink jet method, or nozzle printing using a solution in which an organic semiconductor material is dissolved or dispersed as ink, but is not limited thereto. Instead, it is also possible to use known general methods.
有機薄膜トランジスタ100は、外部の影響から半導体層8を保護するための保護層9を好適に設けることができる。
The organic thin film transistor 100 can be suitably provided with a protective layer 9 for protecting the semiconductor layer 8 from external influences.
保護層9を設ける場合は、少なくとも半導体層8のチャネル領域を覆うように形成することが好ましい。
When the protective layer 9 is provided, it is preferably formed so as to cover at least the channel region of the semiconductor layer 8.
保護層9の材料としては、酸化珪素、酸化アルミニウム、酸化タンタル、酸化イットリウム、酸化ハフニウム、ハフニウムアルミネート、酸化ジルコニウム、酸化チタン等の無機材料、または、PMMA(ポリメチルメタクリレート)等のポリアクリレート、PVA(ポリビニルアルコール)、PVP(ポリビニルフェノール)、フッ素系樹脂等の絶縁材料が挙げられるがこれらに限定されるものではない。
Examples of the material of the protective layer 9 include inorganic materials such as silicon oxide, aluminum oxide, tantalum oxide, yttrium oxide, hafnium oxide, hafnium aluminate, zirconium oxide, and titanium oxide, or polyacrylates such as PMMA (polymethyl methacrylate), Examples thereof include, but are not limited to, insulating materials such as PVA (polyvinyl alcohol), PVP (polyvinylphenol), and fluorine resins.
保護層9の材料については、有機薄膜トランジスタ100のリーク電流を低く抑えるためにその抵抗率が1011Ωcm以上、より好ましくは1014Ωcm以上であることが望ましい。
About the material of the protective layer 9, in order to suppress the leakage current of the organic thin-film transistor 100 low, it is desirable that the resistivity is 10 11 Ωcm or more, more preferably 10 14 Ωcm or more.
保護層9は、保護層材料またはその前駆体を溶解または分散させた溶液を用いて、インクジェット法、凸版印刷法、平版印刷法、凹版印刷法、スクリーン印刷法のいずれかの方法によって形成される。これらの保護層9は単層として用いても構わないし、2層以上積層して用いることもできる。また成長方向に向けて組成を傾斜したものでも構わない。
The protective layer 9 is formed by any one of an inkjet method, a relief printing method, a planographic printing method, an intaglio printing method, and a screen printing method using a solution in which the protective layer material or its precursor is dissolved or dispersed. . These protective layers 9 may be used as a single layer or may be used by laminating two or more layers. Further, the composition may be inclined in the growth direction.
有機薄膜トランジスタ100を用いた画像表示装置とする際は、層間絶縁膜10、画素電極11、図示しない表示要素、図示しない対向電極、図示しない対向基板が好適に設けられる。
In an image display device using the organic thin film transistor 100, an interlayer insulating film 10, a pixel electrode 11, a display element (not shown), a counter electrode (not shown), and a counter substrate (not shown) are preferably provided.
層間絶縁膜10は、ソース電極6と画素電極11とを絶縁することで、画素電極11を介したソース-ドレイン間のリークを防止することを主な目的として形成される。
The interlayer insulating film 10 is formed mainly for the purpose of preventing a source-drain leak through the pixel electrode 11 by insulating the source electrode 6 and the pixel electrode 11.
層間絶縁膜10の材料としては、酸化珪素、酸化アルミニウム、酸化タンタル、酸化イットリウム、酸化ハフニウム、ハフニウムアルミネート、酸化ジルコニウム、酸化チタン等の無機材料、または、PMMA(ポリメチルメタクリレート)等のポリアクリレート、PVA(ポリビニルアルコール)、PVP(ポリビニルフェノール)、フッ素系樹脂等の絶縁材料が挙げられるがこれらに限定されるものではない。
Examples of the material for the interlayer insulating film 10 include inorganic materials such as silicon oxide, aluminum oxide, tantalum oxide, yttrium oxide, hafnium oxide, hafnium aluminate, zirconium oxide, and titanium oxide, or polyacrylates such as PMMA (polymethyl methacrylate). Insulating materials such as PVA (polyvinyl alcohol), PVP (polyvinylphenol), and fluorine-based resins are included, but are not limited thereto.
層間絶縁膜10の材料については、有機薄膜トランジスタ100のリーク電流を低く抑えるためにその抵抗率が1011Ωcm以上、より好ましくは1014Ωcm以上であることが望ましい。
About the material of the interlayer insulation film 10, in order to suppress the leakage current of the organic thin-film transistor 100 low, it is desirable that the resistivity is 10 11 Ωcm or more, more preferably 10 14 Ωcm or more.
層間絶縁膜10は、保護層材料またはその前駆体を溶解または分散させた溶液を用いて、インクジェット法、凸版印刷法、平版印刷法、凹版印刷法、スクリーン印刷法のいずれかの方法によって形成される。これらの層間絶縁膜10は単層として用いても構わないし、2層以上積層して用いることもできる。また成長方向に向けて組成を傾斜したものでも構わない。
The interlayer insulating film 10 is formed by any one of an inkjet method, a relief printing method, a planographic printing method, an intaglio printing method, and a screen printing method using a solution in which a protective layer material or a precursor thereof is dissolved or dispersed. The These interlayer insulating films 10 may be used as a single layer or may be used by stacking two or more layers. Further, the composition may be inclined in the growth direction.
画素電極11は画像表示装置の開口率を向上させることを目的に形成される。
The pixel electrode 11 is formed for the purpose of improving the aperture ratio of the image display device.
画素電極11は、アルミニウム(Al)、銅(Cu)、モリブデン(Mo)、銀(Ag)、クロム(Cr)、チタン(Ti)、金(Au)、白金(Pt)、タングステン(W)、マンガン(Mn)などの金属材料や、酸化インジウム(InO)、酸化スズ(SnO)、酸化亜鉛(ZnO)、酸化インジウムスズ(ITO)、酸化インジウム亜鉛(IZO)などの導電性金属酸化物材料を用いることができるが、これらに限定されるものではない。これらの材料は単層で用いても構わないし、積層および合金として用いても構わない。
The pixel electrode 11 includes aluminum (Al), copper (Cu), molybdenum (Mo), silver (Ag), chromium (Cr), titanium (Ti), gold (Au), platinum (Pt), tungsten (W), Metal materials such as manganese (Mn) and conductive metal oxide materials such as indium oxide (InO), tin oxide (SnO), zinc oxide (ZnO), indium tin oxide (ITO), and indium zinc oxide (IZO) Although it can be used, it is not limited to these. These materials may be used as a single layer, or may be used as a laminate or an alloy.
画素電極11は、真空蒸着法、スパッタ法などの真空成膜法や、導電性材料の前駆体などを使用するゾル-ゲル法やナノ粒子を使用する方法、それらをインク化して、スクリーン印刷、凸版印刷、インクジェット法などのウェット成膜法で形成する方法などが使用できるが、これらに限定されず、公知一般の方法を用いることができる。パターニングは、例えばフォトリソグラフィ法を用いてパターン形成部分をレジストなどにより保護し、エッチングによって不要部分を除去して行うこともできるし、印刷法などを用いて直接パターニングすることもできるが、これについてもこれらの方法に限定されず、公知一般のパターニング方法を用いることができる。
The pixel electrode 11 can be formed by vacuum film-forming methods such as vacuum deposition and sputtering, sol-gel methods using a precursor of a conductive material, a method using nanoparticles, screen printing by converting them into ink, A method of forming by a wet film forming method such as letterpress printing or an ink jet method can be used, but the method is not limited to these, and a known general method can be used. Patterning can be performed by, for example, protecting a pattern forming portion with a resist or the like using a photolithography method and removing an unnecessary portion by etching, or patterning directly using a printing method or the like. Also, the method is not limited to these methods, and a known general patterning method can be used.
また、画素電極11に不透明な材料を用いることにより、半導体層8への外部からの光照射を防ぐことも可能となる。
Also, by using an opaque material for the pixel electrode 11, it is possible to prevent the semiconductor layer 8 from being irradiated with light from the outside.
表示要素は、液晶、電気泳動粒子、または電気泳動粒子を含んだマイクロカプセルや有機エレクトロルミネッセンスなどが使用できる。画像表示装置においては、反射型、透過型のどちらに限定されることなく、これら公知一般の表示要素を使用することが可能である。また、使用する表示要素によっては、1画素内に有機薄膜トランジスタ100を複数設置する構成を利用することも可能である。
As the display element, liquid crystal, electrophoretic particles, microcapsules containing electrophoretic particles, organic electroluminescence, or the like can be used. In the image display apparatus, it is possible to use these known general display elements without being limited to either a reflection type or a transmission type. Further, depending on the display element to be used, it is possible to use a configuration in which a plurality of organic thin film transistors 100 are installed in one pixel.
表示要素は、対向電極を形成した対向基板上に形成した後に、画素電極11まで形成された有機薄膜トランジスタ100と合わせて、画像表示装置としても良いし、画素電極11上に形成した後に、対向電極おおび対向基板を積層して画像表示装置としても良く、使用する表示要素に合わせて、その工程を選択することが可能である。
The display element may be formed on the counter substrate on which the counter electrode is formed, and then combined with the organic thin film transistor 100 formed up to the pixel electrode 11 to form an image display device. After the display element is formed on the pixel electrode 11, the counter electrode In addition, an image display device may be formed by laminating a counter substrate, and the process can be selected in accordance with a display element to be used.
(第2の実施形態)
図2は、本発明の第2の実施の形態に係る有機薄膜トランジスタ110を示す概略断面図である。 (Second Embodiment)
FIG. 2 is a schematic cross-sectional view showing an organicthin film transistor 110 according to a second embodiment of the present invention.
図2は、本発明の第2の実施の形態に係る有機薄膜トランジスタ110を示す概略断面図である。 (Second Embodiment)
FIG. 2 is a schematic cross-sectional view showing an organic
有機薄膜トランジスタ100と有機薄膜トランジスタ110との相違点は、第二の絶縁層5の形成される領域である。図2に示すように、第二の絶縁層5は、キャパシタ電極3とゲート電極2とを同時に覆うように積層される。また、第一の絶縁層4は、第二の絶縁層5の上からゲート電極2を覆うように積層されている。
The difference between the organic thin film transistor 100 and the organic thin film transistor 110 is a region where the second insulating layer 5 is formed. As shown in FIG. 2, the second insulating layer 5 is laminated so as to cover the capacitor electrode 3 and the gate electrode 2 simultaneously. The first insulating layer 4 is laminated so as to cover the gate electrode 2 from above the second insulating layer 5.
第一の絶縁層4及び第二の絶縁層5をこのように形成することで、第二の絶縁層5の膜厚を、第一の絶縁層4と比較して薄くできるため、第一の絶縁層4におけるリーク電流を低く抑えながらキャパシタの静電容量を増加させることが可能となる。
By forming the first insulating layer 4 and the second insulating layer 5 in this way, the film thickness of the second insulating layer 5 can be reduced as compared with the first insulating layer 4. It is possible to increase the capacitance of the capacitor while keeping the leakage current in the insulating layer 4 low.
(第3の実施形態)
図3は、本発明の第3の実施の形態に係る有機薄膜トランジスタ120を示す概略断面図である。 (Third embodiment)
FIG. 3 is a schematic sectional view showing an organicthin film transistor 120 according to the third embodiment of the present invention.
図3は、本発明の第3の実施の形態に係る有機薄膜トランジスタ120を示す概略断面図である。 (Third embodiment)
FIG. 3 is a schematic sectional view showing an organic
有機薄膜トランジスタ100と有機薄膜トランジスタ120との相違点は、第二の絶縁層5の膜厚及び第二の絶縁層5に用いる材料である。図2に示すように、第二の絶縁層5は、キャパシタ電極3を覆うように形成され、その膜厚は、第一の絶縁層4と同じである。また、第二の絶縁層5は、第一の絶縁層4より誘電率の高い材料により形成されている。
The difference between the organic thin film transistor 100 and the organic thin film transistor 120 is the film thickness of the second insulating layer 5 and the material used for the second insulating layer 5. As shown in FIG. 2, the second insulating layer 5 is formed so as to cover the capacitor electrode 3, and the film thickness thereof is the same as that of the first insulating layer 4. The second insulating layer 5 is formed of a material having a higher dielectric constant than that of the first insulating layer 4.
第二の絶縁層5の材料に第一の絶縁層4よりも誘電率の高い材料を用いることにより、両者の膜厚が同じであっても、第一の絶縁層4におけるリーク電流を低く抑えながらキャパシタの静電容量を増加させることが可能となる。
By using a material having a dielectric constant higher than that of the first insulating layer 4 as the material of the second insulating layer 5, the leakage current in the first insulating layer 4 can be kept low even if both films have the same thickness. However, the capacitance of the capacitor can be increased.
(第4の実施形態)
図4は、本発明の第4の実施形態に係る有機薄膜トランジスタ130を示す概略断面図である。 (Fourth embodiment)
FIG. 4 is a schematic cross-sectional view showing an organicthin film transistor 130 according to the fourth embodiment of the present invention.
図4は、本発明の第4の実施形態に係る有機薄膜トランジスタ130を示す概略断面図である。 (Fourth embodiment)
FIG. 4 is a schematic cross-sectional view showing an organic
有機薄膜トランジスタ130は、絶縁性の基板1の上に形成されたゲート電極2とキャパシタ電極3と、少なくともゲート電極2を覆うように形成された第一の絶縁層4と、少なくともキャパシタ電極3の一部を覆うように形成された第二の絶縁層5と、ソース電極6とドレイン電極7と、有機半導体材料を含む半導体層8とを、少なくとも備えている。また、半導体層8を保護するための保護層9も好適に用いられる。
The organic thin film transistor 130 includes a gate electrode 2 and a capacitor electrode 3 formed on an insulating substrate 1, a first insulating layer 4 formed so as to cover at least the gate electrode 2, and at least one capacitor electrode 3. At least a second insulating layer 5 formed so as to cover the portion, a source electrode 6 and a drain electrode 7, and a semiconductor layer 8 containing an organic semiconductor material. A protective layer 9 for protecting the semiconductor layer 8 is also preferably used.
また、有機薄膜トランジスタ130に、層間絶縁膜10と、画素電極11と、図示しない表示要素と、図示しない対向電極と、図示しない第二の基板とを設けることにより、画像表示装置とすることができる。対向電極および第二の基板は、使用する表示要素の種類によりその構造は適宜変更することができる。
Further, by providing the organic thin film transistor 130 with the interlayer insulating film 10, the pixel electrode 11, a display element (not shown), a counter electrode (not shown), and a second substrate (not shown), an image display device can be obtained. . The structures of the counter electrode and the second substrate can be appropriately changed depending on the type of display element used.
以下、有機薄膜トランジスタ130の各構成要素について、有機薄膜トランジスタ130の製造工程に沿って説明する。
Hereinafter, each component of the organic thin film transistor 130 will be described along the manufacturing process of the organic thin film transistor 130.
初めに、基板1を準備する。基板1の材料としては、ポリカーボネート、ポリエチレンサルファイド、ポリエーテルスルホン、ポリエチレンテレフタレート、ポリエチレンナフタレート、シクロオレフィンポリマー、トリアセチルセルロース、ポリビニルフルオライドフィルム、エチレン-テトラフルオロエチレン共重合樹脂、耐候性ポリエチレンテレフタレート、耐候性ポリプロピレン、ガラス繊維強化アクリル樹脂フィルム、ガラス繊維強化ポリカーボネート、ポリイミド、フッ素系樹脂、環状ポリオレフィン系樹脂、ガラス、石英ガラスなどを使用することができるが、これらに限定されるものではない。これらは単独で使用してもよいが、2種以上を積層した複合の基板1として使用することもできる。
First, the substrate 1 is prepared. As the material of the substrate 1, polycarbonate, polyethylene sulfide, polyethersulfone, polyethylene terephthalate, polyethylene naphthalate, cycloolefin polymer, triacetyl cellulose, polyvinyl fluoride film, ethylene-tetrafluoroethylene copolymer resin, weather resistant polyethylene terephthalate, Weatherable polypropylene, glass fiber reinforced acrylic resin film, glass fiber reinforced polycarbonate, polyimide, fluorine resin, cyclic polyolefin resin, glass, quartz glass, and the like can be used, but are not limited thereto. These may be used alone, but can also be used as a composite substrate 1 in which two or more kinds are laminated.
基板1が有機物フィルムである場合は、有機薄膜トランジスタ130の耐久性を向上させるために透明のガスバリア層(図示せず)を形成することもできる。ガスバリア層としては、酸化アルミニウム(Al2O3)、酸化珪素(SiO)、窒化珪素(SiN)、酸化窒化珪素(SiON)、炭化珪素(SiC)、およびダイヤモンドライクカーボン(DLC)などが挙げられるが、これらに限定されるものではない。また、これらのガスバリア層は、2層以上積層して使用することもできる。ガスバリア層は、有機物フィルムを用いた基板1の片面だけに形成してもよいし、両面に形成しても構わない。ガスバリア層は、真空蒸着法、イオンプレーティング法、スパッタリング法、レーザーアブレーション法、プラズマCVD(Chemical Vapor Deposition)法、ホットワイヤーCVD法、およびゾル-ゲル法などを用いて形成することができるが、これらに限定されるものではない。
When the substrate 1 is an organic film, a transparent gas barrier layer (not shown) can be formed in order to improve the durability of the organic thin film transistor 130. Examples of the gas barrier layer include aluminum oxide (Al 2 O 3 ), silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide (SiC), diamond-like carbon (DLC), and the like. However, it is not limited to these. These gas barrier layers can be used by laminating two or more layers. The gas barrier layer may be formed only on one side of the substrate 1 using an organic film, or may be formed on both sides. The gas barrier layer can be formed using a vacuum deposition method, an ion plating method, a sputtering method, a laser ablation method, a plasma CVD (Chemical Vapor Deposition) method, a hot wire CVD method, a sol-gel method, etc. It is not limited to these.
また、基板1上に形成されるゲート電極2およびキャパシタ電極3の基板1との密着性を向上させるために密着層を設けることもできるし、基板1の表面に表面処理などを施しても良い。
In addition, an adhesion layer can be provided in order to improve the adhesion between the gate electrode 2 and the capacitor electrode 3 formed on the substrate 1 and the substrate 1, or the surface of the substrate 1 may be subjected to a surface treatment or the like. .
次に、基板1上に、ゲート電極2およびキャパシタ電極3を形成する。ゲート電極2、キャパシタ電極3、ソース電極6、およびドレイン電極7は、電極部分と配線部分とが明確に分かれている必要はなく、以下では特に各有機薄膜トランジスタの構成要素として電極と呼称している。
Next, the gate electrode 2 and the capacitor electrode 3 are formed on the substrate 1. The gate electrode 2, the capacitor electrode 3, the source electrode 6, and the drain electrode 7 do not need to be clearly separated from each other in the electrode portion and the wiring portion, and are hereinafter referred to as electrodes as components of each organic thin film transistor. .
ゲート電極2およびキャパシタ電極3には、アルミニウム(Al)、銅(Cu)、モリブデン(Mo)、銀(Ag)、クロム(Cr)、チタン(Ti)、金(Au)、白金(Pt)、タングステン(W)、マンガン(Mn)などの金属材料や、酸化インジウム(InO)、酸化スズ(SnO)、酸化亜鉛(ZnO)、酸化インジウムスズ(ITO)、酸化インジウム亜鉛(IZO)などの導電性金属酸化物材料を用いることができるが、これらに限定されるものではない。これらの材料は単層で用いても構わないし、積層および合金として用いても構わない。
The gate electrode 2 and the capacitor electrode 3 include aluminum (Al), copper (Cu), molybdenum (Mo), silver (Ag), chromium (Cr), titanium (Ti), gold (Au), platinum (Pt), Metal materials such as tungsten (W) and manganese (Mn), and conductive materials such as indium oxide (InO), tin oxide (SnO), zinc oxide (ZnO), indium tin oxide (ITO), and indium zinc oxide (IZO) Although a metal oxide material can be used, it is not limited to these. These materials may be used as a single layer, or may be used as a laminate or an alloy.
ゲート電極2およびキャパシタ電極3の形成には、真空蒸着法、スパッタ法などの真空成膜法や、導電性材料の前駆体などを使用するゾル-ゲル法やナノ粒子を使用する方法、それらをインク化して、スクリーン印刷、凸版印刷、インクジェット法などのウェット成膜法で形成する方法などが使用できるが、これらに限定されず、公知一般の方法を用いることができる。パターニングは、例えばフォトリソグラフィ法を用いてパターン形成部分をレジストなどにより保護し、エッチングによって不要部分を除去して行うこともできるし、印刷法などを用いて直接パターニングすることもできるが、これについてもこれらの方法に限定されず、公知一般のパターニング方法を用いることができる。
The gate electrode 2 and the capacitor electrode 3 can be formed by vacuum film-forming methods such as vacuum deposition and sputtering, sol-gel methods using precursors of conductive materials, methods using nanoparticles, and the like. A method of forming an ink and forming it by a wet film forming method such as screen printing, letterpress printing, or an ink jet method can be used, but the method is not limited to these, and a known general method can be used. Patterning can be performed by, for example, protecting a pattern forming portion with a resist or the like using a photolithography method and removing an unnecessary portion by etching, or patterning directly using a printing method or the like. Also, the method is not limited to these methods, and a known general patterning method can be used.
次に、少なくともゲート電極2を覆うように、第一の絶縁層4を形成する。
Next, a first insulating layer 4 is formed so as to cover at least the gate electrode 2.
第一の絶縁層4には、酸化珪素(SiOx)、酸化アルミニウム(AlOx)、酸化タンタル(TaOx)、酸化イットリウム(YOx)、酸化ジルコニウム(ZrOx)、酸化ハフニウム(HfOx)などの酸化物系絶縁材料や窒化珪素(SiNx)、酸化窒化珪素(SiON)や、ポリメチルメタクリレート(PMMA)等のポリアクリレート、ポリビニルアルコール(PVA)、ポリビニルフェノール(PVP)などの有機系絶縁材料や、自己組織化膜等の材料を使用することができるが、これらに限定されるものではない。これらは単層または2層以上積層してもよいし、無機系-有機系のハイブリッド薄膜としても良いし、成長方向に向けて組成を傾斜したものでも構わない。
The first insulating layer 4 includes oxide-based insulating materials such as silicon oxide (SiOx), aluminum oxide (AlOx), tantalum oxide (TaOx), yttrium oxide (YOx), zirconium oxide (ZrOx), and hafnium oxide (HfOx). Materials, organic insulating materials such as silicon nitride (SiNx), silicon oxynitride (SiON), polyacrylates such as polymethyl methacrylate (PMMA), polyvinyl alcohol (PVA), polyvinylphenol (PVP), and self-assembled films However, the present invention is not limited to these materials. These may be a single layer or a laminate of two or more layers, may be an inorganic-organic hybrid thin film, or may have a composition inclined in the growth direction.
第一の絶縁層4に自己組織化膜を用いる場合は、異なる自己組織化材料を積層する多層膜構造とすることで、絶縁層の誘電率や絶縁性を制御することが可能である。さらに、自己組織化した多層膜を繰り返し構造とすることで、絶縁性を高めることも可能である。また、第一の絶縁層4の表面に形成される半導体層8の種類に合わせて表面の官能基を選択し、表面エネルギーを制御することで、有機薄膜トランジスタ130の性能を向上することも可能である。
When a self-assembled film is used for the first insulating layer 4, it is possible to control the dielectric constant and insulation of the insulating layer by using a multilayer film structure in which different self-assembled materials are laminated. Furthermore, it is also possible to improve insulation by making a self-assembled multilayer film into a repeated structure. It is also possible to improve the performance of the organic thin film transistor 130 by selecting the surface functional group according to the type of the semiconductor layer 8 formed on the surface of the first insulating layer 4 and controlling the surface energy. is there.
第一の絶縁層4は、有機薄膜トランジスタ130および画像表示装置におけるリーク電流を抑えるために、その抵抗率が1011Ωcm以上、より好ましくは1014Ωcm以上であることが望ましい。
The first insulating layer 4 desirably has a resistivity of 10 11 Ωcm or more, more preferably 10 14 Ωcm or more, in order to suppress leakage current in the organic thin film transistor 130 and the image display device.
次に、キャパシタ電極3上に、第二の絶縁層5を形成する。第二の絶縁層5は、少なくともキャパシタ電極3の一部を覆うように形成され、第二の絶縁層5上においてキャパシタ電極3と重畳するように形成されるドレイン電極7によってキャパシタ構造を成すことで、有機薄膜トランジスタ130を用いた画像表示装置の電圧保持容量として機能する。なお、第一の絶縁層4および第二の絶縁層5の形成は、この順序に限定されず、第二の絶縁層5を形成した後に第一の絶縁層4の形成を行ってもよい。
Next, the second insulating layer 5 is formed on the capacitor electrode 3. The second insulating layer 5 is formed so as to cover at least a part of the capacitor electrode 3, and forms a capacitor structure by the drain electrode 7 formed so as to overlap the capacitor electrode 3 on the second insulating layer 5. Thus, it functions as a voltage holding capacitor of an image display device using the organic thin film transistor 130. The formation of the first insulating layer 4 and the second insulating layer 5 is not limited to this order, and the first insulating layer 4 may be formed after the second insulating layer 5 is formed.
第二の絶縁層5には、酸化珪素(SiOx)、酸化アルミニウム(AlOx)、酸化タンタル(TaOx)、酸化イットリウム(YOx)、酸化ジルコニウム(ZrOx)、酸化ハフニウム(HfOx)などの酸化物系絶縁材料や窒化珪素(SiNx)、酸化窒化珪素(SiON)や、ポリメチルメタクリレート(PMMA)等のポリアクリレート、ポリビニルアルコール(PVA)、ポリビニルフェノール(PVP)などの有機系絶縁材料や、自己組織化膜等の材料を使用することができるが、これらに限定されるものではない。これらは単層または2層以上積層してもよいし、無機系-有機系のハイブリッド薄膜としても良いし、成長方向に向けて組成を傾斜したものでも構わない。
The second insulating layer 5 includes oxide-based insulating materials such as silicon oxide (SiOx), aluminum oxide (AlOx), tantalum oxide (TaOx), yttrium oxide (YOx), zirconium oxide (ZrOx), and hafnium oxide (HfOx). Materials, organic insulating materials such as silicon nitride (SiNx), silicon oxynitride (SiON), polyacrylates such as polymethyl methacrylate (PMMA), polyvinyl alcohol (PVA), polyvinylphenol (PVP), and self-assembled films However, the present invention is not limited to these materials. These may be a single layer or a laminate of two or more layers, may be an inorganic-organic hybrid thin film, or may have a composition inclined in the growth direction.
第二の絶縁層5に自己組織化膜を用いる場合は、異なる自己組織化材料を積層する多層膜構造とすることで、絶縁層の誘電率や絶縁性を制御することが可能である。さらに、自己組織化した多層膜を繰り返し構造とすることで、絶縁性を高めることも可能である。
When a self-assembled film is used for the second insulating layer 5, it is possible to control the dielectric constant and insulation of the insulating layer by adopting a multilayer film structure in which different self-assembled materials are laminated. Furthermore, it is also possible to improve insulation by making a self-assembled multilayer film into a repeated structure.
第二の絶縁層5は、有機薄膜トランジスタ130および画像表示装置におけるリーク電流を抑えるために、その抵抗率が1011Ωcm以上、より好ましくは1014Ωcm以上であることが望ましい。
The second insulating layer 5 desirably has a resistivity of 10 11 Ωcm or more, more preferably 10 14 Ωcm or more, in order to suppress leakage current in the organic thin film transistor 130 and the image display device.
第二の絶縁層5は、有機薄膜トランジスタ130において、キャパシタ電極3およびドレイン電極7を絶縁することでキャパシタ構造を形成しており、キャパシタの容量を確保するために、その誘電率を第一の絶縁層4と比較して大きくすることが好ましい。有機薄膜トランジスタ130においては、第二の絶縁層5の誘電率を第一の絶縁層4の誘電率よりも大きくすることにより、キャパシタの静電容量を増加させることが可能となる。第一の絶縁層4の比誘電率は、2以上かつ5以下であることが好ましい。また、第二の絶縁層5の比誘電率は、3以上、好ましくは5以上、さらには20以上であることが好ましいが、これらに限定されるものではない。
The second insulating layer 5 forms a capacitor structure by insulating the capacitor electrode 3 and the drain electrode 7 in the organic thin film transistor 130, and in order to secure the capacitance of the capacitor, the dielectric constant thereof is changed to the first insulating layer. It is preferable to make it larger than that of the layer 4. In the organic thin film transistor 130, the capacitance of the capacitor can be increased by making the dielectric constant of the second insulating layer 5 larger than the dielectric constant of the first insulating layer 4. The relative dielectric constant of the first insulating layer 4 is preferably 2 or more and 5 or less. The relative dielectric constant of the second insulating layer 5 is 3 or more, preferably 5 or more, and more preferably 20 or more, but is not limited thereto.
第二の絶縁層5が多層からなる場合においては、第二の絶縁層5の一部に第一の絶縁層4と同じ材料および組成を用いてよいし、全て異なる材料を用いても良い。これらに限定されることなく、様々な組合せで形成することが可能である。
When the second insulating layer 5 is composed of multiple layers, the same material and composition as the first insulating layer 4 may be used for a part of the second insulating layer 5, or all different materials may be used. Without being limited thereto, various combinations can be formed.
第二の絶縁層5の膜厚を第一の絶縁層4よりも薄くすることにより、第一の絶縁層4におけるゲートリーク電流を低く抑えながらキャパシタの静電容量をさらに増加させることが可能となる。
By making the thickness of the second insulating layer 5 thinner than that of the first insulating layer 4, it is possible to further increase the capacitance of the capacitor while keeping the gate leakage current in the first insulating layer 4 low. Become.
第一の絶縁層4および第二の絶縁層5の形成方法は、真空蒸着法、スパッタ法などの真空成膜法や、金属錯体などを前駆体として使用するゾル-ゲル法やナノ粒子を使用する方法、スリットコート法、スピンコート方、スクリーン印刷、凸版印刷、インクジェット法などのウェット成膜法で形成する方法などが使用できるが、これらに限定されず、公知一般の方法を用いることができる。
The first insulating layer 4 and the second insulating layer 5 are formed using a vacuum film-forming method such as a vacuum deposition method or a sputtering method, a sol-gel method using a metal complex or the like as a precursor, or nanoparticles. For example, a method of forming by a wet coating method such as a slit coating method, a spin coating method, screen printing, letterpress printing, or an ink jet method can be used, but the method is not limited to these, and a known general method can be used. .
次に、第一の絶縁層4および第二の絶縁層5上に、ソース電極6およびドレイン電極7を形成する。ソース電極6およびドレイン電極7は、先に示したゲート電極2およびキャパシタ電極3と同様の材料および方法によって形成することができる。
Next, the source electrode 6 and the drain electrode 7 are formed on the first insulating layer 4 and the second insulating layer 5. The source electrode 6 and the drain electrode 7 can be formed by the same material and method as the gate electrode 2 and the capacitor electrode 3 described above.
ソース電極6およびドレイン電極7については、半導体層8よりもソース電極6およびドレイン電極7を先に形成するボトムコンタクト構造としても良いし、半導体層8の形成後に、ソース電極6およびドレイン電極7を形成するトップコンタクト構造としても良い。
The source electrode 6 and the drain electrode 7 may have a bottom contact structure in which the source electrode 6 and the drain electrode 7 are formed before the semiconductor layer 8, or the source electrode 6 and the drain electrode 7 may be formed after the semiconductor layer 8 is formed. A top contact structure may be formed.
また、ボトムコンタクト構造を適用する場合においては、ソース電極6およびドレイン電極7は、半導体層8との電気的接続における接触抵抗を低下させるために、表面処理などを行うことができる。
In the case of applying the bottom contact structure, the source electrode 6 and the drain electrode 7 can be subjected to a surface treatment or the like in order to reduce contact resistance in electrical connection with the semiconductor layer 8.
次に、第一の絶縁層4、ソース電極6およびドレイン電極7上に半導体層8を形成する。半導体層8には、ペンタセン、およびその誘導体のような低分子半導体やポリチオフェン、ポリアリルアミン、フルオレンビチオフェン共重合体、およびそれらの誘導体のような高分子有機半導体材料を用いることができるが、これらに限定されるものではない。
Next, a semiconductor layer 8 is formed on the first insulating layer 4, the source electrode 6 and the drain electrode 7. For the semiconductor layer 8, low molecular semiconductors such as pentacene and derivatives thereof, and polymer organic semiconductor materials such as polythiophene, polyallylamine, fluorenebithiophene copolymers, and derivatives thereof can be used. It is not limited to.
半導体層8は、有機半導体材料を溶解または分散させた溶液をインクとして用いる凸版印刷、スクリーン印刷、インクジェット法、ノズルプリンティングなどのウェット成膜方法で形成することができるが、これらに限定されるものではなく、公知一般の方法を使用することも可能である。
The semiconductor layer 8 can be formed by a wet film forming method such as letterpress printing, screen printing, ink jet method, or nozzle printing using a solution in which an organic semiconductor material is dissolved or dispersed as ink, but is not limited thereto. Instead, it is also possible to use known general methods.
有機薄膜トランジスタ130は、外部の影響から半導体層8を保護するための保護層9を好適に設けることができる。
The organic thin film transistor 130 can be suitably provided with a protective layer 9 for protecting the semiconductor layer 8 from external influences.
保護層9を設ける場合は、少なくとも半導体層8のチャネル領域を覆うように形成することが好ましい。
When the protective layer 9 is provided, it is preferably formed so as to cover at least the channel region of the semiconductor layer 8.
保護層9の材料としては、酸化珪素、酸化アルミニウム、酸化タンタル、酸化イットリウム、酸化ハフニウム、ハフニウムアルミネート、酸化ジルコニウム、酸化チタン等の無機材料、または、PMMA(ポリメチルメタクリレート)等のポリアクリレート、PVA(ポリビニルアルコール)、PVP(ポリビニルフェノール)、フッ素系樹脂等の有機系絶縁材料が挙げられるが、これらに限定されるものではない。
Examples of the material of the protective layer 9 include inorganic materials such as silicon oxide, aluminum oxide, tantalum oxide, yttrium oxide, hafnium oxide, hafnium aluminate, zirconium oxide, and titanium oxide, or polyacrylates such as PMMA (polymethyl methacrylate), Organic insulating materials such as PVA (polyvinyl alcohol), PVP (polyvinylphenol), and fluorine-based resin are exemplified, but the invention is not limited thereto.
保護層9の材料については、有機薄膜トランジスタ130のリーク電流を低く抑えるためにその抵抗率が1011Ωcm以上、より好ましくは1014Ωcm以上であることが望ましい。
About the material of the protective layer 9, in order to suppress the leak current of the organic thin-film transistor 130 low, it is desirable that the resistivity is 10 11 Ωcm or more, more preferably 10 14 Ωcm or more.
保護層9は、保護層材料またはその前駆体を溶解または分散させた溶液を用いて、インクジェット法、凸版印刷法、平版印刷法、凹版印刷法、スクリーン印刷法のいずれかの方法によって形成される。これらの保護層9は、単層として用いても構わないし、2層以上積層して用いることもできる。また、成長方向に向けて組成を傾斜したものでも構わない。
The protective layer 9 is formed by any one of an inkjet method, a relief printing method, a planographic printing method, an intaglio printing method, and a screen printing method using a solution in which the protective layer material or its precursor is dissolved or dispersed. . These protective layers 9 may be used as a single layer, or two or more layers may be laminated. Further, the composition may be inclined in the growth direction.
有機薄膜トランジスタ130を用いた画像表示装置とする際は、層間絶縁膜10、画素電極11、図示しない表示要素、図示しない対向電極、図示しない対向基板が好適に設けられる。
In an image display device using the organic thin film transistor 130, the interlayer insulating film 10, the pixel electrode 11, a display element (not shown), a counter electrode (not shown), and a counter substrate (not shown) are preferably provided.
層間絶縁膜10は、ソース電極6と画素電極11とを絶縁することで、画素電極11を介したソース-ドレイン間のリークを防止することを主な目的として形成される。
The interlayer insulating film 10 is formed mainly for the purpose of preventing a source-drain leak through the pixel electrode 11 by insulating the source electrode 6 and the pixel electrode 11.
層間絶縁膜10の材料としては、酸化珪素、酸化アルミニウム、酸化タンタル、酸化イットリウム、酸化ハフニウム、ハフニウムアルミネート、酸化ジルコニウム、酸化チタン等の無機材料、または、PMMA(ポリメチルメタクリレート)等のポリアクリレート、PVA(ポリビニルアルコール)、PVP(ポリビニルフェノール)、フッ素系樹脂等の絶縁材料が挙げられるが、これらに限定されるものではない。
Examples of the material for the interlayer insulating film 10 include inorganic materials such as silicon oxide, aluminum oxide, tantalum oxide, yttrium oxide, hafnium oxide, hafnium aluminate, zirconium oxide, and titanium oxide, or polyacrylates such as PMMA (polymethyl methacrylate). Insulating materials such as PVA (polyvinyl alcohol), PVP (polyvinylphenol), and fluorine-based resin are not limited thereto.
層間絶縁膜10の材料については、有機薄膜トランジスタ130のリーク電流を低く抑えるためにその抵抗率が1011Ωcm以上、より好ましくは1014Ωcm以上であることが望ましい。
About the material of the interlayer insulation film 10, in order to suppress the leakage current of the organic thin-film transistor 130 low, it is desirable that the resistivity is 10 11 Ωcm or more, more preferably 10 14 Ωcm or more.
層間絶縁膜10は、保護層材料またはその前駆体を溶解または分散させた溶液を用いて、インクジェット法、凸版印刷法、平版印刷法、凹版印刷法、スクリーン印刷法のいずれかの方法によって形成される。これらの層間絶縁膜10は、単層として用いても構わないし、2層以上積層して用いることもできる。また、成長方向に向けて組成を傾斜したものでも構わない。
The interlayer insulating film 10 is formed by any one of an inkjet method, a relief printing method, a planographic printing method, an intaglio printing method, and a screen printing method using a solution in which a protective layer material or a precursor thereof is dissolved or dispersed. The These interlayer insulating films 10 may be used as a single layer or may be used by stacking two or more layers. Further, the composition may be inclined in the growth direction.
画素電極11は、画像表示装置の開口率を向上させることを目的に形成される。
The pixel electrode 11 is formed for the purpose of improving the aperture ratio of the image display device.
画素電極11は、アルミニウム(Al)、銅(Cu)、モリブデン(Mo)、銀(Ag)、クロム(Cr)、チタン(Ti)、金(Au)、白金(Pt)、タングステン(W)、マンガン(Mn)などの金属材料や、酸化インジウム(InO)、酸化スズ(SnO)、酸化亜鉛(ZnO)、酸化インジウムスズ(ITO)、酸化インジウム亜鉛(IZO)などの導電性金属酸化物材料を用いることができるが、これらに限定されるものではない。これらの材料は単層で用いても構わないし、積層および合金として用いても構わない。
The pixel electrode 11 includes aluminum (Al), copper (Cu), molybdenum (Mo), silver (Ag), chromium (Cr), titanium (Ti), gold (Au), platinum (Pt), tungsten (W), Metal materials such as manganese (Mn) and conductive metal oxide materials such as indium oxide (InO), tin oxide (SnO), zinc oxide (ZnO), indium tin oxide (ITO), and indium zinc oxide (IZO) Although it can be used, it is not limited to these. These materials may be used as a single layer, or may be used as a laminate or an alloy.
画素電極11は、真空蒸着法、スパッタ法などの真空成膜法や、導電性材料の前駆体などを使用するゾル-ゲル法やナノ粒子を使用する方法、それらをインク化して、スクリーン印刷、凸版印刷、インクジェット法などのウェット成膜法で形成する方法などが使用できるが、これらに限定されず、公知一般の方法を用いることができる。パターニングは、例えばフォトリソグラフィ法を用いてパターン形成部分をレジストなどにより保護し、エッチングによって不要部分を除去して行うこともできるし、印刷法などを用いて直接パターニングすることもできるが、これについてもこれらの方法に限定されず、公知一般のパターニング方法を用いることができる。
The pixel electrode 11 can be formed by vacuum film-forming methods such as vacuum deposition and sputtering, sol-gel methods using a precursor of a conductive material, a method using nanoparticles, screen printing by converting them into ink, A method of forming by a wet film forming method such as letterpress printing or an ink jet method can be used, but the method is not limited to these, and a known general method can be used. Patterning can be performed by, for example, protecting a pattern forming portion with a resist or the like using a photolithography method and removing an unnecessary portion by etching, or patterning directly using a printing method or the like. Also, the method is not limited to these methods, and a known general patterning method can be used.
また、画素電極11に不透明な材料を用いることにより、半導体層8への外部からの光照射を防ぐことも可能となる。
Also, by using an opaque material for the pixel electrode 11, it is possible to prevent the semiconductor layer 8 from being irradiated with light from the outside.
表示要素は、液晶、電気泳動粒子、または電気泳動粒子を含んだマイクロカプセルや有機エレクトロルミネッセンスなどが使用できる。画像表示装置においては、反射型、透過型のどちらに限定されることなく、これら公知一般の表示要素を使用することが可能である。また、使用する表示要素によっては、1画素内に有機薄膜トランジスタ130を複数設置する構成を利用することも可能である。
As the display element, liquid crystal, electrophoretic particles, microcapsules containing electrophoretic particles, organic electroluminescence, or the like can be used. In the image display apparatus, it is possible to use these known general display elements without being limited to either a reflection type or a transmission type. Further, depending on the display element to be used, a configuration in which a plurality of organic thin film transistors 130 are installed in one pixel can be used.
表示要素は、対向電極を形成した対向基板上に形成した後に、画素電極11まで形成された有機薄膜トランジスタ130と合わせて、画像表示装置としても良いし、画素電極11上に形成した後に、対向電極および対向基板を積層して画像表示装置としても良く、使用する表示要素に合わせて、その工程を選択することが可能である。
The display element may be formed on the counter substrate on which the counter electrode is formed, and then combined with the organic thin film transistor 130 formed up to the pixel electrode 11 to form an image display device, or after being formed on the pixel electrode 11, the counter electrode The counter substrate may be stacked to form an image display device, and the process can be selected in accordance with the display element to be used.
(第5の実施形態)
図5は、本発明の第5の実施形態に係る有機薄膜トランジスタ140を示す概略断面図である。 (Fifth embodiment)
FIG. 5 is a schematic cross-sectional view showing an organicthin film transistor 140 according to the fifth embodiment of the present invention.
図5は、本発明の第5の実施形態に係る有機薄膜トランジスタ140を示す概略断面図である。 (Fifth embodiment)
FIG. 5 is a schematic cross-sectional view showing an organic
有機薄膜トランジスタ130と有機薄膜トランジスタ140との相違点は、第二の絶縁層5が形成される領域である。図5に示すように、第二の絶縁層5は、キャパシタ電極3とゲート電極2とを同時に覆うように積層される。また、第一の絶縁層4は、第二の絶縁層5の上からゲート電極2を覆うように積層されている。
The difference between the organic thin film transistor 130 and the organic thin film transistor 140 is a region where the second insulating layer 5 is formed. As shown in FIG. 5, the second insulating layer 5 is laminated so as to cover the capacitor electrode 3 and the gate electrode 2 simultaneously. The first insulating layer 4 is laminated so as to cover the gate electrode 2 from above the second insulating layer 5.
第一の絶縁層4および第二の絶縁層5をこのように形成することで、第一の絶縁層4の表面性を変化させることなく、薄膜トランジスタのチャネル部に蓄積される電荷量を増やすことが可能となるため、キャパシタ容量の増加だけでなく、薄膜トランジスタのオン電流を増加させることも可能となる。
By forming the first insulating layer 4 and the second insulating layer 5 in this way, the amount of charge accumulated in the channel portion of the thin film transistor is increased without changing the surface property of the first insulating layer 4. Therefore, it is possible to increase not only the capacitor capacity but also the ON current of the thin film transistor.
(第6の実施形態)
図6は、本発明の第6の実施形態に係る有機薄膜トランジスタ150を示す概略断面図である。 (Sixth embodiment)
FIG. 6 is a schematic cross-sectional view showing an organicthin film transistor 150 according to the sixth embodiment of the present invention.
図6は、本発明の第6の実施形態に係る有機薄膜トランジスタ150を示す概略断面図である。 (Sixth embodiment)
FIG. 6 is a schematic cross-sectional view showing an organic
有機薄膜トランジスタ130と有機薄膜トランジスタ150との相違点は、第一の絶縁層4が形成される領域である。図6に示すように、第一の絶縁層4は、ゲート電極2とキャパシタ電極3とを同時に覆うように形成される。また、第二の絶縁層5は、第一の絶縁層4の上からキャパシタ電極3を覆うように積層されている。また、第二の絶縁層5は、第一の絶縁層4より誘電率の高い材料により形成されている。
The difference between the organic thin film transistor 130 and the organic thin film transistor 150 is a region where the first insulating layer 4 is formed. As shown in FIG. 6, the first insulating layer 4 is formed so as to cover the gate electrode 2 and the capacitor electrode 3 simultaneously. The second insulating layer 5 is laminated so as to cover the capacitor electrode 3 from above the first insulating layer 4. The second insulating layer 5 is formed of a material having a higher dielectric constant than that of the first insulating layer 4.
第二の絶縁層5の材料に第一の絶縁層4よりも誘電率の高い材料を用いることにより、リーク電流を低く抑えながらキャパシタの静電容量を増加させることが可能となる。
By using a material having a dielectric constant higher than that of the first insulating layer 4 as the material of the second insulating layer 5, it is possible to increase the capacitance of the capacitor while suppressing the leakage current.
(第7の実施形態)
図7は、本発明の第7の実施形態に係る有機薄膜トランジスタ160を示す概略断面図である。 (Seventh embodiment)
FIG. 7 is a schematic cross-sectional view showing an organicthin film transistor 160 according to a seventh embodiment of the present invention.
図7は、本発明の第7の実施形態に係る有機薄膜トランジスタ160を示す概略断面図である。 (Seventh embodiment)
FIG. 7 is a schematic cross-sectional view showing an organic
有機薄膜トランジスタ160は、絶縁性の基板1の上に形成されたソース電極6とドレイン電極7と、有機半導体材料を含む半導体層8と、ソース電極6および半導体層8を覆うように形成された第一の絶縁層4と、少なくともドレイン電極7の一部を覆うように形成された第二の絶縁層5と、ゲート電極2と、キャパシタ電極3とを、少なくとも備えている。
The organic thin film transistor 160 is formed so as to cover the source electrode 6 and the drain electrode 7 formed on the insulating substrate 1, the semiconductor layer 8 containing an organic semiconductor material, and the source electrode 6 and the semiconductor layer 8. At least an insulating layer 4, a second insulating layer 5 formed so as to cover at least a part of the drain electrode 7, a gate electrode 2, and a capacitor electrode 3 are provided.
また、有機薄膜トランジスタ160に、層間絶縁膜10と、画素電極11と、図示しない表示要素と、図示しない対向電極と、図示しない第二の基板とを設けることにより、画像表示装置とすることができる。対向電極および第二の基板は、使用する表示要素の種類によりその構造は適宜変更することができる。
Further, by providing the organic thin film transistor 160 with the interlayer insulating film 10, the pixel electrode 11, a display element (not shown), a counter electrode (not shown), and a second substrate (not shown), an image display device can be obtained. . The structures of the counter electrode and the second substrate can be appropriately changed depending on the type of display element used.
以下、有機薄膜トランジスタ160の各構成要素について、有機薄膜トランジスタ160の製造工程に沿って説明する。
Hereinafter, each component of the organic thin film transistor 160 will be described along the manufacturing process of the organic thin film transistor 160.
初めに、基板1を準備する。基板1の材料としては、ポリカーボネート、ポリエチレンサルファイド、ポリエーテルスルホン、ポリエチレンテレフタレート、ポリエチレンナフタレート、シクロオレフィンポリマー、トリアセチルセルロース、ポリビニルフルオライドフィルム、エチレン-テトラフルオロエチレン共重合樹脂、耐候性ポリエチレンテレフタレート、耐候性ポリプロピレン、ガラス繊維強化アクリル樹脂フィルム、ガラス繊維強化ポリカーボネート、ポリイミド、フッ素系樹脂、環状ポリオレフィン系樹脂、ガラス、石英ガラスなどを使用することができるが、これらに限定されるものではない。これらは単独で使用してもよいが、2種以上を積層した複合の基板1として使用することもできる。
First, the substrate 1 is prepared. As the material of the substrate 1, polycarbonate, polyethylene sulfide, polyethersulfone, polyethylene terephthalate, polyethylene naphthalate, cycloolefin polymer, triacetyl cellulose, polyvinyl fluoride film, ethylene-tetrafluoroethylene copolymer resin, weather resistant polyethylene terephthalate, Weatherable polypropylene, glass fiber reinforced acrylic resin film, glass fiber reinforced polycarbonate, polyimide, fluorine resin, cyclic polyolefin resin, glass, quartz glass, and the like can be used, but are not limited thereto. These may be used alone, but can also be used as a composite substrate 1 in which two or more kinds are laminated.
基板1が有機物フィルムである場合は、有機薄膜トランジスタ160の耐久性を向上させるために透明のガスバリア層(図示せず)を形成することもできる。ガスバリア層としては、酸化アルミニウム(Al2O3)、酸化珪素(SiO)、窒化珪素(SiN)、酸化窒化珪素(SiON)、炭化珪素(SiC)、およびダイヤモンドライクカーボン(DLC)などが挙げられるが、これらに限定されるものではない。また、これらのガスバリア層は、2層以上積層して使用することもできる。ガスバリア層は、有機物フィルムを用いた基板1の片面だけに形成してもよいし、両面に形成しても構わない。ガスバリア層は、真空蒸着法、イオンプレーティング法、スパッタリング法、レーザーアブレーション法、プラズマCVD(Chemical Vapor Deposition)法、ホットワイヤーCVD法、およびゾル-ゲル法などを用いて形成することができるが、これらに限定されるものではない。
When the substrate 1 is an organic film, a transparent gas barrier layer (not shown) can be formed in order to improve the durability of the organic thin film transistor 160. Examples of the gas barrier layer include aluminum oxide (Al 2 O 3 ), silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide (SiC), diamond-like carbon (DLC), and the like. However, it is not limited to these. These gas barrier layers can be used by laminating two or more layers. The gas barrier layer may be formed only on one side of the substrate 1 using an organic film, or may be formed on both sides. The gas barrier layer can be formed using a vacuum deposition method, an ion plating method, a sputtering method, a laser ablation method, a plasma CVD (Chemical Vapor Deposition) method, a hot wire CVD method, a sol-gel method, etc. It is not limited to these.
また、基板1上に形成されるソース電極6、ドレイン電極7、および半導体層8の基板1との密着性を向上させるために密着層を設けることもできるし、基板1の表面に表面処理などを施しても良い。
In addition, an adhesion layer can be provided to improve the adhesion of the source electrode 6, the drain electrode 7, and the semiconductor layer 8 formed on the substrate 1 to the substrate 1, and a surface treatment or the like is performed on the surface of the substrate 1. May be applied.
次に、基板1上に、ソース電極6およびドレイン電極7を形成する。ソース電極6、ドレイン電極7、ゲート電極2、およびキャパシタ電極3は、電極部分と配線部分とが明確に分かれている必要はなく、以下では特に各有機薄膜トランジスタの構成要素として電極と呼称している。
Next, the source electrode 6 and the drain electrode 7 are formed on the substrate 1. The source electrode 6, drain electrode 7, gate electrode 2, and capacitor electrode 3 do not need to be clearly separated from each other in the electrode portion and the wiring portion, and are hereinafter referred to as electrodes as components of each organic thin film transistor. .
ソース電極6およびドレイン電極7には、アルミニウム(Al)、銅(Cu)、モリブデン(Mo)、銀(Ag)、クロム(Cr)、チタン(Ti)、金(Au)、白金(Pt)、タングステン(W)、マンガン(Mn)などの金属材料や、酸化インジウム(InO)、酸化スズ(SnO)、酸化亜鉛(ZnO)、酸化インジウムスズ(ITO)、酸化インジウム亜鉛(IZO)などの導電性金属酸化物材料を用いることができるが、これらに限定されるものではない。これらの材料は単層で用いても構わないし、積層および合金として用いても構わない。
The source electrode 6 and the drain electrode 7 include aluminum (Al), copper (Cu), molybdenum (Mo), silver (Ag), chromium (Cr), titanium (Ti), gold (Au), platinum (Pt), Metal materials such as tungsten (W) and manganese (Mn), and conductive materials such as indium oxide (InO), tin oxide (SnO), zinc oxide (ZnO), indium tin oxide (ITO), and indium zinc oxide (IZO) Although a metal oxide material can be used, it is not limited to these. These materials may be used as a single layer, or may be used as a laminate or an alloy.
ソース電極6およびドレイン電極7の形成には、真空蒸着法、スパッタ法などの真空成膜法や、導電性材料の前駆体などを使用するゾル-ゲル法やナノ粒子を使用する方法、それらをインク化して、スクリーン印刷、凸版印刷、インクジェット法などのウェット成膜法で形成する方法などが使用できるが、これらに限定されず、公知一般の方法を用いることができる。パターニングは、例えばフォトリソグラフィ法を用いてパターン形成部分をレジストなどにより保護し、エッチングによって不要部分を除去して行うこともできるし、印刷法などを用いて直接パターニングすることもできるが、これについてもこれらの方法に限定されず、公知一般のパターニング方法を用いることができる。
The source electrode 6 and the drain electrode 7 can be formed by vacuum film-forming methods such as vacuum deposition and sputtering, sol-gel methods using precursors of conductive materials, methods using nanoparticles, and the like. A method of forming an ink and forming it by a wet film forming method such as screen printing, letterpress printing, or an ink jet method can be used, but the method is not limited to these, and a known general method can be used. Patterning can be performed by, for example, protecting a pattern forming portion with a resist or the like using a photolithography method and removing an unnecessary portion by etching, or patterning directly using a printing method or the like. Also, the method is not limited to these methods, and a known general patterning method can be used.
ソース電極6およびドレイン電極7については、半導体層8よりもソース電極6およびドレイン電極7を先に形成するボトムコンタクト構造としても良いし、半導体層8の形成後に、ソース電極6およびドレイン電極7を形成するトップコンタクト構造としても良い。
The source electrode 6 and the drain electrode 7 may have a bottom contact structure in which the source electrode 6 and the drain electrode 7 are formed before the semiconductor layer 8, or the source electrode 6 and the drain electrode 7 may be formed after the semiconductor layer 8 is formed. A top contact structure may be formed.
また、ボトムコンタクト構造を適用する場合においては、ソース電極6およびドレイン電極7は、半導体層8との電気的接続における接触抵抗を低下させるために、表面処理などを施すことができる。
In the case of applying the bottom contact structure, the source electrode 6 and the drain electrode 7 can be subjected to a surface treatment or the like in order to reduce the contact resistance in electrical connection with the semiconductor layer 8.
次に、絶縁性の基板1、ソース電極6、およびドレイン電極7上に、半導体層8を形成する。半導体層8には、ペンタセン、およびそれらの誘導体のような低分子半導体やポリチオフェン、ポリアリルアミン、フルオレンビチオフェン共重合体、およびそれらの誘導体のような高分子有機半導体材料を用いることができるが、これらに限定されるものではない。
Next, a semiconductor layer 8 is formed on the insulating substrate 1, the source electrode 6, and the drain electrode 7. For the semiconductor layer 8, low molecular semiconductors such as pentacene and derivatives thereof, and polymer organic semiconductor materials such as polythiophene, polyallylamine, fluorenebithiophene copolymers, and derivatives thereof can be used. It is not limited to these.
半導体層8は、有機半導体材料を溶解または分散させた溶液をインクとして用いる凸版印刷、スクリーン印刷、インクジェット法、ノズルプリンティングなどのウェット成膜方法で形成することができるが、これらに限定されるものではなく、公知一般の方法を使用することも可能である。
The semiconductor layer 8 can be formed by a wet film forming method such as letterpress printing, screen printing, ink jet method, or nozzle printing using a solution in which an organic semiconductor material is dissolved or dispersed as ink, but is not limited thereto. Instead, it is also possible to use known general methods.
次に、少なくともソース電極6および半導体層8を覆うように、第一の絶縁層4を形成する。
Next, the first insulating layer 4 is formed so as to cover at least the source electrode 6 and the semiconductor layer 8.
第一の絶縁層4には、酸化珪素(SiOx)、酸化アルミニウム(AlOx)、酸化タンタル(TaOx)、酸化イットリウム(YOx)、酸化ジルコニウム(ZrOx)、酸化ハフニウム(HfOx)などの酸化物系絶縁材料や窒化珪素(SiNx)、酸化窒化珪素(SiON)や、ポリメチルメタクリレート(PMMA)等のポリアクリレート、ポリビニルアルコール(PVA)、ポリビニルフェノール(PVP)などの有機系絶縁材料などを使用することができるが、これらに限定されるものではない。これらは単層または2層以上積層してもよいし、無機系-有機系のハイブリッド薄膜としても良いし、成長方向に向けて組成を傾斜したものでも構わない。
The first insulating layer 4 includes oxide-based insulating materials such as silicon oxide (SiOx), aluminum oxide (AlOx), tantalum oxide (TaOx), yttrium oxide (YOx), zirconium oxide (ZrOx), and hafnium oxide (HfOx). Materials, silicon nitride (SiNx), silicon oxynitride (SiON), polyacrylates such as polymethyl methacrylate (PMMA), organic insulating materials such as polyvinyl alcohol (PVA), polyvinylphenol (PVP), etc. may be used. However, it is not limited to these. These may be a single layer or a laminate of two or more layers, may be an inorganic-organic hybrid thin film, or may have a composition inclined in the growth direction.
第一の絶縁層4は、有機薄膜トランジスタ160および画像表示装置におけるリーク電流を抑えるために、その抵抗率が1011Ωcm以上、より好ましくは1014Ωcm以上であることが望ましい。
The first insulating layer 4 desirably has a resistivity of 10 11 Ωcm or more, more preferably 10 14 Ωcm or more, in order to suppress leakage current in the organic thin film transistor 160 and the image display device.
次に、ドレイン電極7上に、第二の絶縁層5を形成する。第二の絶縁層5は、少なくともドレイン電極7の一部を覆うように形成され、第二の絶縁層5上においてドレイン電極7と重畳するように形成されるキャパシタ電極3によってキャパシタ構造を成すことで、有機薄膜トランジスタ160を用いた画像表示装置のキャパシタとして機能する。なお、第一の絶縁層4および第二の絶縁層5の形成は、この順序に限定されず、第二の絶縁層5を形成した後に第一の絶縁層4の形成を行ってもよい。
Next, the second insulating layer 5 is formed on the drain electrode 7. The second insulating layer 5 is formed so as to cover at least a part of the drain electrode 7, and a capacitor structure is formed by the capacitor electrode 3 formed so as to overlap the drain electrode 7 on the second insulating layer 5. Thus, it functions as a capacitor of an image display device using the organic thin film transistor 160. The formation of the first insulating layer 4 and the second insulating layer 5 is not limited to this order, and the first insulating layer 4 may be formed after the second insulating layer 5 is formed.
第二の絶縁層5には、酸化珪素(SiOx)、酸化アルミニウム(AlOx)、酸化タンタル(TaOx)、酸化イットリウム(YOx)、酸化ジルコニウム(ZrOx)、酸化ハフニウム(HfOx)などの酸化物系絶縁材料や窒化珪素(SiNx)、酸化窒化珪素(SiON)や、ポリメチルメタクリレート(PMMA)等のポリアクリレート、ポリビニルアルコール(PVA)、ポリビニルフェノール(PVP)などの有機系絶縁材料や、自己組織化膜等の材料を使用することができるが、これらに限定されるものではない。これらは単層または2層以上積層してもよいし、無機系-有機系のハイブリッド薄膜としても良いし、成長方向に向けて組成を傾斜したものでも構わない。
The second insulating layer 5 includes oxide-based insulating materials such as silicon oxide (SiOx), aluminum oxide (AlOx), tantalum oxide (TaOx), yttrium oxide (YOx), zirconium oxide (ZrOx), and hafnium oxide (HfOx). Materials, organic insulating materials such as silicon nitride (SiNx), silicon oxynitride (SiON), polyacrylates such as polymethyl methacrylate (PMMA), polyvinyl alcohol (PVA), polyvinylphenol (PVP), and self-assembled films However, the present invention is not limited to these materials. These may be a single layer or a laminate of two or more layers, may be an inorganic-organic hybrid thin film, or may have a composition inclined in the growth direction.
第二の絶縁層5に自己組織化膜を用いる場合は、異なる自己組織化材料を積層する多層膜構造とすることで、絶縁層の誘電率や絶縁性を制御することが可能である。さらに、自己組織化した多層膜を繰り返し構造とすることで、絶縁性を高めることも可能である。
When a self-assembled film is used for the second insulating layer 5, it is possible to control the dielectric constant and insulation of the insulating layer by adopting a multilayer film structure in which different self-assembled materials are laminated. Furthermore, it is also possible to improve insulation by making a self-assembled multilayer film into a repeated structure.
第二の絶縁層5は、有機薄膜トランジスタ160および画像表示装置におけるリーク電流を抑えるために、その抵抗率が1011Ωcm以上、より好ましくは1014Ωcm以上であることが望ましい。
The second insulating layer 5 desirably has a resistivity of 10 11 Ωcm or more, more preferably 10 14 Ωcm or more, in order to suppress leakage current in the organic thin film transistor 160 and the image display device.
第二の絶縁層5は、有機薄膜トランジスタ160において、ドレイン電極7およびキャパシタ電極3を絶縁することでキャパシタ構造を形成しており、キャパシタの容量を確保するために、その膜厚は第一の絶縁層4と比較して薄くすることが好ましい。有機薄膜トランジスタ160においては、第二の絶縁層5を第一の絶縁層4よりも薄膜で形成することにより、第一の絶縁層4の形成されるトランジスタ部におけるリーク電流を低く抑えながらキャパシタの静電容量を増加させることが可能となる。
The second insulating layer 5 forms a capacitor structure by insulating the drain electrode 7 and the capacitor electrode 3 in the organic thin film transistor 160. The film thickness of the second insulating layer 5 is the first insulating thickness in order to secure the capacitance of the capacitor. It is preferable to make it thinner than the layer 4. In the organic thin film transistor 160, the second insulating layer 5 is formed to be thinner than the first insulating layer 4, so that the leakage current in the transistor portion where the first insulating layer 4 is formed can be kept low while the capacitance of the capacitor is reduced. The electric capacity can be increased.
第二の絶縁層5は、第一の絶縁層4と同様の材料および組成を用いてよいし、異なる材料を用いても良くこれらに限定されることなく、様々な組合せで形成することが可能である。
The second insulating layer 5 may use the same material and composition as the first insulating layer 4, or may use different materials and can be formed in various combinations without being limited thereto. It is.
第二の絶縁層5の材料に第一の絶縁層4よりも比誘電率の高い材料を用いることにより、キャパシタの静電容量をさらに増加させることが可能となる。第一の絶縁層4の比誘電率は、2以上かつ5以下であることが好ましい。また、第二の絶縁層5の比誘電率は、3以上、好ましくは5以上、さらには20以上であることが好ましいが、これらに限定されるものではない。
By using a material having a higher dielectric constant than that of the first insulating layer 4 as the material of the second insulating layer 5, the capacitance of the capacitor can be further increased. The relative dielectric constant of the first insulating layer 4 is preferably 2 or more and 5 or less. The relative dielectric constant of the second insulating layer 5 is 3 or more, preferably 5 or more, and more preferably 20 or more, but is not limited thereto.
第一の絶縁層4および第二の絶縁層5の形成方法は、真空蒸着法、スパッタ法などの真空成膜法や、金属錯体などを前駆体として使用するゾル-ゲル法やナノ粒子を使用する方法、スリットコート法、スピンコート方、スクリーン印刷、凸版印刷、インクジェット法などのウェット成膜法で形成する方法などが使用できるが、これらに限定されず、公知一般の方法を用いることができる。
The first insulating layer 4 and the second insulating layer 5 are formed using a vacuum film-forming method such as a vacuum deposition method or a sputtering method, a sol-gel method using a metal complex or the like as a precursor, or nanoparticles. For example, a method of forming by a wet coating method such as a slit coating method, a spin coating method, screen printing, letterpress printing, or an ink jet method can be used, but the method is not limited to these, and a known general method can be used. .
次に、第一の絶縁層4および第二の絶縁層5上に、ゲート電極2およびキャパシタ電極3を形成する。ゲート電極2およびキャパシタ電極3は、先に示したソース電極6およびドレイン電極7と同様の材料および方法によって形成することができる。
Next, the gate electrode 2 and the capacitor electrode 3 are formed on the first insulating layer 4 and the second insulating layer 5. The gate electrode 2 and the capacitor electrode 3 can be formed by the same material and method as the source electrode 6 and the drain electrode 7 described above.
有機薄膜トランジスタ160を用いた画像表示装置とする際は、層間絶縁膜10、画素電極11、図示しない表示要素、図示しない対向電極、図示しない対向基板が好適に設けられる。
In an image display device using the organic thin film transistor 160, the interlayer insulating film 10, the pixel electrode 11, a display element (not shown), a counter electrode (not shown), and a counter substrate (not shown) are preferably provided.
層間絶縁膜10は、ゲート電極2およびキャパシタ電極3と画素電極9とを絶縁することで、画素電極9を介したゲート-ドレイン間およびキャパシタ-ドレイン間のリークを防止することを主な目的として形成される。
The interlayer insulating film 10 mainly prevents gate-drain and capacitor-drain leakage through the pixel electrode 9 by insulating the gate electrode 2 and capacitor electrode 3 from the pixel electrode 9. It is formed.
層間絶縁膜10の材料としては、酸化珪素、酸化アルミニウム、酸化タンタル、酸化イットリウム、酸化ハフニウム、ハフニウムアルミネート、酸化ジルコニウム、酸化チタン等の無機材料、または、PMMA(ポリメチルメタクリレート)等のポリアクリレート、PVA(ポリビニルアルコール)、PVP(ポリビニルフェノール)、フッ素系樹脂等の絶縁材料が挙げられるが、これらに限定されるものではない。
Examples of the material for the interlayer insulating film 10 include inorganic materials such as silicon oxide, aluminum oxide, tantalum oxide, yttrium oxide, hafnium oxide, hafnium aluminate, zirconium oxide, and titanium oxide, or polyacrylates such as PMMA (polymethyl methacrylate). Insulating materials such as PVA (polyvinyl alcohol), PVP (polyvinylphenol), and fluorine-based resin are not limited thereto.
層間絶縁膜10の材料については、有機薄膜トランジスタ160のリーク電流を低く抑えるためにその抵抗率が1011Ωcm以上、より好ましくは1014Ωcm以上であることが望ましい。
About the material of the interlayer insulation film 10, in order to suppress the leakage current of the organic thin-film transistor 160 low, it is desirable that the resistivity is 10 11 Ωcm or more, more preferably 10 14 Ωcm or more.
層間絶縁膜10は、保護層材料またはその前駆体を溶解または分散させた溶液を用いて、インクジェット法、凸版印刷法、平版印刷法、凹版印刷法、スクリーン印刷法のいずれかの方法によって形成される。これらの層間絶縁膜9は、単層として用いても構わないし、2層以上積層して用いることもできる。また、成長方向に向けて組成を傾斜したものでも構わない。
The interlayer insulating film 10 is formed by any one of an inkjet method, a relief printing method, a planographic printing method, an intaglio printing method, and a screen printing method using a solution in which a protective layer material or a precursor thereof is dissolved or dispersed. The These interlayer insulating films 9 may be used as a single layer or may be used by stacking two or more layers. Further, the composition may be inclined in the growth direction.
画素電極11は、画像表示装置の開口率を向上させることを目的に形成される。
The pixel electrode 11 is formed for the purpose of improving the aperture ratio of the image display device.
画素電極11は、アルミニウム(Al)、銅(Cu)、モリブデン(Mo)、銀(Ag)、クロム(Cr)、チタン(Ti)、金(Au)、白金(Pt)、タングステン(W)、マンガン(Mn)などの金属材料や、酸化インジウム(InO)、酸化スズ(SnO)、酸化亜鉛(ZnO)、酸化インジウムスズ(ITO)、酸化インジウム亜鉛(IZO)などの導電性金属酸化物材料を用いることができるが、これらに限定されるものではない。これらの材料は単層で用いても構わないし、積層および合金として用いても構わない。
The pixel electrode 11 includes aluminum (Al), copper (Cu), molybdenum (Mo), silver (Ag), chromium (Cr), titanium (Ti), gold (Au), platinum (Pt), tungsten (W), Metal materials such as manganese (Mn) and conductive metal oxide materials such as indium oxide (InO), tin oxide (SnO), zinc oxide (ZnO), indium tin oxide (ITO), and indium zinc oxide (IZO) Although it can be used, it is not limited to these. These materials may be used as a single layer, or may be used as a laminate or an alloy.
画素電極11は、真空蒸着法、スパッタ法などの真空成膜法や、導電性材料の前駆体などを使用するゾル-ゲル法やナノ粒子を使用する方法、それらをインク化して、スクリーン印刷、凸版印刷、インクジェット法などのウェット成膜法で形成する方法などが使用できるが、これらに限定されず、公知一般の方法を用いることができる。パターニングは、例えばフォトリソグラフィ法を用いてパターン形成部分をレジストなどにより保護し、エッチングによって不要部分を除去して行うこともできるし、印刷法などを用いて直接パターニングすることもできるが、これについてもこれらの方法に限定されず、公知一般のパターニング方法を用いることができる。
The pixel electrode 11 can be formed by vacuum film-forming methods such as vacuum deposition and sputtering, sol-gel methods using a precursor of a conductive material, a method using nanoparticles, screen printing by converting them into ink, A method of forming by a wet film forming method such as letterpress printing or an ink jet method can be used, but the method is not limited to these, and a known general method can be used. Patterning can be performed by, for example, protecting a pattern forming portion with a resist or the like using a photolithography method and removing an unnecessary portion by etching, or patterning directly using a printing method or the like. Also, the method is not limited to these methods, and a known general patterning method can be used.
また、画素電極11に不透明な材料を用いることにより、半導体層8への外部からの光照射を防ぐことも可能となる。
Also, by using an opaque material for the pixel electrode 11, it is possible to prevent the semiconductor layer 8 from being irradiated with light from the outside.
表示要素は、液晶、電気泳動粒子、または電気泳動粒子を含んだマイクロカプセルや有機エレクトロルミネッセンスなどが使用できる。画像表示装置においては、反射型、透過型のどちらに限定されることなく、これら公知一般の表示要素を使用することが可能である。また、使用する表示要素によっては、1画素内に有機薄膜トランジスタ160を複数設置する構成を利用することも可能である。
As the display element, liquid crystal, electrophoretic particles, microcapsules containing electrophoretic particles, organic electroluminescence, or the like can be used. In the image display apparatus, it is possible to use these known general display elements without being limited to either a reflection type or a transmission type. Further, depending on the display element to be used, it is possible to use a configuration in which a plurality of organic thin film transistors 160 are installed in one pixel.
表示要素は、対向電極を形成した対向基板上に形成した後に、画素電極11まで形成された有機薄膜トランジスタ160と合わせて、画像表示装置としても良いし、画素電極11上に形成した後に、対向電極および対向基板を積層して画像表示装置としても良く、使用する表示要素に合わせて、その工程を選択することが可能である。
The display element may be formed on the counter substrate on which the counter electrode is formed, and then combined with the organic thin film transistor 160 formed up to the pixel electrode 11 to form an image display device. After the display element is formed on the pixel electrode 11, the counter electrode The counter substrate may be stacked to form an image display device, and the process can be selected in accordance with the display element to be used.
(第8の実施形態)
図8は、本発明の第8の実施形態に係る有機薄膜トランジスタ170を示す概略断面図である。 (Eighth embodiment)
FIG. 8 is a schematic sectional view showing an organicthin film transistor 170 according to the eighth embodiment of the present invention.
図8は、本発明の第8の実施形態に係る有機薄膜トランジスタ170を示す概略断面図である。 (Eighth embodiment)
FIG. 8 is a schematic sectional view showing an organic
有機薄膜トランジスタ160と有機薄膜トランジスタ170との相違点は、第二の絶縁層5が形成される領域である。図8に示すように、第一の絶縁層4は、半導体層8を覆うように積層される。また、第二の絶縁層5は、第一の絶縁層4の上から、ソース電極6および半導体層8、さらにドレイン電極7の一部の領域を覆うように積層される。
The difference between the organic thin film transistor 160 and the organic thin film transistor 170 is a region where the second insulating layer 5 is formed. As shown in FIG. 8, the first insulating layer 4 is laminated so as to cover the semiconductor layer 8. The second insulating layer 5 is laminated on the first insulating layer 4 so as to cover the source electrode 6, the semiconductor layer 8, and a part of the drain electrode 7.
第一の絶縁層4および第二の絶縁層5をこのように形成することで、ドレイン電極7およびキャパシタ電極3により形成されるキャパシタ部分の膜厚を半導体層8の形成されているトランジスタ部の膜厚よりも薄くできるため、トランジスタ部のリーク電流を低く抑えながらキャパシタの静電容量を増加させることが可能となる。
By forming the first insulating layer 4 and the second insulating layer 5 in this way, the thickness of the capacitor portion formed by the drain electrode 7 and the capacitor electrode 3 can be reduced in the transistor portion where the semiconductor layer 8 is formed. Since it can be made thinner than the film thickness, it is possible to increase the capacitance of the capacitor while keeping the leakage current of the transistor portion low.
(第9の実施形態)
図9は、本発明の第9の実施形態に係る有機薄膜トランジスタ180を示す概略断面図である。 (Ninth embodiment)
FIG. 9 is a schematic cross-sectional view showing an organicthin film transistor 180 according to a ninth embodiment of the present invention.
図9は、本発明の第9の実施形態に係る有機薄膜トランジスタ180を示す概略断面図である。 (Ninth embodiment)
FIG. 9 is a schematic cross-sectional view showing an organic
有機薄膜トランジスタ160と有機薄膜トランジスタ180との相違点は、第一の絶縁層4と第二の絶縁層5の膜厚および第二の絶縁層5に用いる材料である。図9に示すように、第二の絶縁層5は、ドレイン電極7の一部を覆うように形成され、その膜厚は、第一の絶縁層4よりも薄く形成される。また、第二の絶縁層5は、第一の絶縁層4より誘電率の高い材料により形成されている。
The difference between the organic thin film transistor 160 and the organic thin film transistor 180 is the thickness of the first insulating layer 4 and the second insulating layer 5 and the material used for the second insulating layer 5. As shown in FIG. 9, the second insulating layer 5 is formed so as to cover a part of the drain electrode 7, and the film thickness thereof is thinner than that of the first insulating layer 4. The second insulating layer 5 is formed of a material having a higher dielectric constant than that of the first insulating layer 4.
第二の絶縁層5の材料に第一の絶縁層4よりも誘電率の高い材料を用いることにより、キャパシタの静電容量をさらに増加させることが可能となる。
By using a material having a dielectric constant higher than that of the first insulating layer 4 as the material of the second insulating layer 5, the capacitance of the capacitor can be further increased.
実施例1として、図1に示す有機薄膜トランジスタ100を作製した。
As Example 1, an organic thin film transistor 100 shown in FIG.
基板1として厚さ0.7mmの無アルカリガラスを使用した。ガラス基板1上に、DCマグネトロンスパッタを用いてモリブデン(Mo)を400nmの膜厚で成膜し、フォトリソグラフィ法により所望の形状にパターニングを行い、ゲート電極2およびキャパシタ電極3とした。
Non-alkali glass with a thickness of 0.7 mm was used as the substrate 1. Molybdenum (Mo) was formed into a film thickness of 400 nm on the glass substrate 1 using DC magnetron sputtering, and was patterned into a desired shape by a photolithography method to obtain a gate electrode 2 and a capacitor electrode 3.
ゲート電極2およびキャパシタ電極3を形成した基板に、感光性アクリル樹脂をスリットコート法で塗布し、露光、現像を行い所望の形状にパターニングし、200℃で焼成を行い、第二の絶縁層5を形成した。その後、第二の絶縁層5と同様の方法で第一の絶縁層4を形成した。第一の絶縁層4の膜厚は1μm、第二の絶縁層5の膜厚は0.5μmとした。感光性アクリル樹脂の比誘電率は3.4である。
A photosensitive acrylic resin is applied to the substrate on which the gate electrode 2 and the capacitor electrode 3 are formed by a slit coat method, exposed and developed, patterned into a desired shape, baked at 200 ° C., and the second insulating layer 5 Formed. Thereafter, the first insulating layer 4 was formed in the same manner as the second insulating layer 5. The film thickness of the first insulating layer 4 was 1 μm, and the film thickness of the second insulating layer 5 was 0.5 μm. The relative permittivity of the photosensitive acrylic resin is 3.4.
つづいて、銀ナノ粒子を分散させた溶液をインクとして、インクジェット法を用いて所望の形状にパターニングし、150℃で1時間焼成し、ソース電極6およびドレイン電極7を形成した。
Subsequently, a solution in which silver nanoparticles were dispersed was used as an ink, and was patterned into a desired shape using an ink jet method, and baked at 150 ° C. for 1 hour to form a source electrode 6 and a drain electrode 7.
その後、有機半導体材料としてポリ(3-ヘキシルチオフェン)を0.1重量%濃度で溶解させたメシチレン溶液をインクジェット法によりパターニングし、半導体層8を形成した。
Thereafter, a mesitylene solution in which poly (3-hexylthiophene) as an organic semiconductor material was dissolved at a concentration of 0.1% by weight was patterned by an ink jet method to form a semiconductor layer 8.
実施例2として、図2に示す有機薄膜トランジスタ110を作製した。
As Example 2, an organic thin film transistor 110 shown in FIG.
基板1として厚さ0.7mmの無アルカリガラスを使用した。ガラス基板1上に、DCマグネトロンスパッタを用いてMoを400nmの膜厚で成膜し、フォトリソグラフィ法により所望の形状にパターニングを行い、ゲート電極2およびキャパシタ電極3を形成した。
Non-alkali glass with a thickness of 0.7 mm was used as the substrate 1. On the glass substrate 1, Mo was formed into a film having a thickness of 400 nm by using DC magnetron sputtering, and patterned into a desired shape by a photolithography method to form the gate electrode 2 and the capacitor electrode 3.
ゲート電極2およびキャパシタ電極3を形成した基板1に、酸化アルミニウム(Al2O3)を原子層堆積(ALD)法を用いて50nmの膜厚で成膜した。その後、感光性アクリル樹脂をスリットコート法で塗布し、フォトリソグラフィ法によりパターニングを行い、200℃で焼成し、第一の絶縁層4となる領域を酸化アルミニウムと感光性アクリル樹脂との積層構造とし、第二の絶縁層5となる領域を酸化アルミニウムのみの層となるように形成した。感光性アクリル樹脂の膜厚は1μmである。なお電極取り出し部などの不要な酸化アルミニウム層はフォトリソ法およびドライエッチング法を用いて除去した。酸化アルミニウムの比誘電率は9.3、感光性アクリル樹脂の比誘電率は3.4である。
Aluminum oxide (Al 2 O 3 ) was formed to a thickness of 50 nm on the substrate 1 on which the gate electrode 2 and the capacitor electrode 3 were formed using an atomic layer deposition (ALD) method. Thereafter, a photosensitive acrylic resin is applied by a slit coating method, patterned by a photolithography method, and baked at 200 ° C., so that a region to be the first insulating layer 4 has a laminated structure of aluminum oxide and a photosensitive acrylic resin. The region to be the second insulating layer 5 was formed to be a layer made only of aluminum oxide. The film thickness of the photosensitive acrylic resin is 1 μm. Note that an unnecessary aluminum oxide layer such as an electrode extraction portion was removed by using a photolithography method and a dry etching method. The relative dielectric constant of aluminum oxide is 9.3, and the relative dielectric constant of the photosensitive acrylic resin is 3.4.
つづいて、銀ナノ粒子を分散させたインクを、インクジェット法を用いて所望の形状にパターニングし、150℃で1時間焼成し、ソース電極6およびドレイン電極7を形成した。
Subsequently, the ink in which the silver nanoparticles were dispersed was patterned into a desired shape using an ink jet method, and baked at 150 ° C. for 1 hour to form the source electrode 6 and the drain electrode 7.
その後、有機半導体材料としてポリ(3-ヘキシルチオフェン)を0.1重量%濃度で溶解させたメシチレン溶液をインクジェット法によりパターニングし、半導体層8を形成した。
Thereafter, a mesitylene solution in which poly (3-hexylthiophene) as an organic semiconductor material was dissolved at a concentration of 0.1% by weight was patterned by an ink jet method to form a semiconductor layer 8.
実施例3として、図3に示す有機薄膜トランジスタ120を作製した。
As Example 3, an organic thin film transistor 120 shown in FIG.
基板1として厚さ0.7mmの無アルカリガラスを使用した。ガラス基板1上に、DCマグネトロンスパッタを用いてMoを400nmの膜厚で成膜し、フォトリソグラフィ法により所望の形状にパターニングを行い、ゲート電極2およびキャパシタ電極3を形成した。
Non-alkali glass with a thickness of 0.7 mm was used as the substrate 1. On the glass substrate 1, Mo was formed into a film having a thickness of 400 nm by using DC magnetron sputtering, and patterned into a desired shape by a photolithography method to form the gate electrode 2 and the capacitor electrode 3.
ゲート電極2およびキャパシタ電極3を形成した基板1に、感光性ポリスチレン樹脂をスリットコート法で塗布し、フォトリソグラフィ法によりパターニングし、200℃で焼成し、第一の絶縁層4を形成した。続いて実施例1及び2とは比誘電率の異なる感光性アクリル樹脂を塗布し、フォトリソグラフィ法によりパターニングし、第二の絶縁層5を形成した。第一の絶縁層4および第二の絶縁層5の膜厚はともに1μmである。第一の絶縁層4の比誘電率は2.5、第二の絶縁層の比誘電率は4.2である。
A photosensitive polystyrene resin was applied to the substrate 1 on which the gate electrode 2 and the capacitor electrode 3 were formed by a slit coating method, patterned by a photolithography method, and baked at 200 ° C. to form a first insulating layer 4. Subsequently, a photosensitive acrylic resin having a different dielectric constant from that of Examples 1 and 2 was applied and patterned by photolithography to form a second insulating layer 5. The film thicknesses of the first insulating layer 4 and the second insulating layer 5 are both 1 μm. The relative dielectric constant of the first insulating layer 4 is 2.5, and the relative dielectric constant of the second insulating layer is 4.2.
つづいて、銀ナノ粒子を分散させたインクを、インクジェット法を用いて所望の形状にパターニングし、150℃で1時間焼成し、ソース電極6およびドレイン電極7を形成した。
Subsequently, the ink in which the silver nanoparticles were dispersed was patterned into a desired shape using an ink jet method, and baked at 150 ° C. for 1 hour to form the source electrode 6 and the drain electrode 7.
その後、有機半導体材料としてポリ(3-ヘキシルチオフェン)を0.1重量%濃度で溶解させたメシチレン溶液をインクジェット法によりパターニングし、半導体層8を形成した。
Thereafter, a mesitylene solution in which poly (3-hexylthiophene) as an organic semiconductor material was dissolved at a concentration of 0.1% by weight was patterned by an ink jet method to form a semiconductor layer 8.
実施例4として、図4に示す有機薄膜トランジスタ130を作製した。
As Example 4, an organic thin film transistor 130 shown in FIG.
基板1として厚さ0.7mmの無アルカリガラスを使用した。ガラス基板1上に、DCマグネトロンスパッタを用いてモリブデン(Mo)を400nmの膜厚で成膜し、フォトリソグラフィ法により所望の形状にパターニングを行い、ゲート電極2およびキャパシタ電極3を形成した。
Non-alkali glass with a thickness of 0.7 mm was used as the substrate 1. Molybdenum (Mo) was formed into a film thickness of 400 nm on the glass substrate 1 using DC magnetron sputtering, and patterned into a desired shape by a photolithography method to form the gate electrode 2 and the capacitor electrode 3.
ゲート電極2およびキャパシタ電極3を形成した基板1に、感光性シリコーン樹脂をスリットコート法で塗布し、露光、現像を行い所望の形状にパターニングし、200℃で焼成を行い、第一の絶縁層4を形成した。その後、第一の絶縁層4と同様の方法で第二の絶縁層5を形成した。第一の絶縁層4および第二の絶縁層5の膜厚は、ともに1μmとした。また、第一の絶縁層4の比誘電率は2.5、第二の絶縁層5の比誘電率は、4.2である。
A photosensitive silicone resin is applied to the substrate 1 on which the gate electrode 2 and the capacitor electrode 3 are formed by a slit coating method, exposed and developed, patterned into a desired shape, and baked at 200 ° C. to form a first insulating layer 4 was formed. Thereafter, the second insulating layer 5 was formed in the same manner as the first insulating layer 4. The film thicknesses of the first insulating layer 4 and the second insulating layer 5 were both 1 μm. The relative dielectric constant of the first insulating layer 4 is 2.5, and the relative dielectric constant of the second insulating layer 5 is 4.2.
つづいて、銀ナノ粒子を分散させた溶液をインクとして、インクジェット法を用いて所望の形状にパターニングし、180℃で1時間焼成し、ソース電極6およびドレイン電極7を形成した。
Subsequently, a solution in which silver nanoparticles were dispersed was used as an ink, and was patterned into a desired shape using an ink jet method, and baked at 180 ° C. for 1 hour to form a source electrode 6 and a drain electrode 7.
その後、有機半導体材料としてポリ(3-ヘキシルチオフェン)を0.1重量%濃度で溶解させたメシチレン溶液をインクジェット法によりパターニングし、半導体層8を形成した。
Thereafter, a mesitylene solution in which poly (3-hexylthiophene) as an organic semiconductor material was dissolved at a concentration of 0.1% by weight was patterned by an ink jet method to form a semiconductor layer 8.
実施例5として、図5に示す有機薄膜トランジスタ140を作製した。
As Example 5, an organic thin film transistor 140 shown in FIG.
基板1として厚さ0.7mmの無アルカリガラスを使用した。ガラス基板1上に、DCマグネトロンスパッタを用いてMoを400nmの膜厚で成膜し、フォトリソグラフィ法により所望の形状にパターニングを行い、ゲート電極2およびキャパシタ電極3を形成した。
Non-alkali glass with a thickness of 0.7 mm was used as the substrate 1. On the glass substrate 1, Mo was formed into a film having a thickness of 400 nm by using DC magnetron sputtering, and patterned into a desired shape by a photolithography method to form the gate electrode 2 and the capacitor electrode 3.
ゲート電極2およびキャパシタ電極3を形成した基板1に、酸化アルミニウム(Al2O3)を原子層堆積法(ALD法)を用いて100nmの膜厚で成膜した。その後、感光性シリコーン樹脂をスリットコート法で塗布し、フォトリソグラフィ法によりパターニングを行い、200℃で焼成し、第一の絶縁層4となる領域を酸化アルミニウムと感光性アクリル樹脂との積層構造とし、キャパシタ電極3上の第二の絶縁層5となる領域を酸化アルミニウムのみの層となるように形成した。感光性アクリル樹脂の膜厚は1μmである。なお、電極取り出し部などの不要な酸化アルミニウム層は、フォトリソ法およびドライエッチング法を用いて除去した。酸化アルミニウムの比誘電率は9.3、感光性シリコーン樹脂の比誘電率は2.5である。
Aluminum oxide (Al 2 O 3 ) was formed to a thickness of 100 nm on the substrate 1 on which the gate electrode 2 and the capacitor electrode 3 were formed by using an atomic layer deposition method (ALD method). Thereafter, a photosensitive silicone resin is applied by a slit coating method, patterned by a photolithography method, and baked at 200 ° C., so that a region to be the first insulating layer 4 has a laminated structure of aluminum oxide and a photosensitive acrylic resin. The region to be the second insulating layer 5 on the capacitor electrode 3 was formed to be a layer made only of aluminum oxide. The film thickness of the photosensitive acrylic resin is 1 μm. Note that an unnecessary aluminum oxide layer such as an electrode extraction portion was removed by using a photolithography method and a dry etching method. The relative dielectric constant of aluminum oxide is 9.3, and the relative dielectric constant of photosensitive silicone resin is 2.5.
つづいて、銀ナノ粒子を分散させたインクを、インクジェット法を用いて所望の形状にパターニングし、180℃で1時間焼成し、ソース電極6およびドレイン電極7を形成した。
Subsequently, the ink in which the silver nanoparticles were dispersed was patterned into a desired shape using an ink jet method, and baked at 180 ° C. for 1 hour to form the source electrode 6 and the drain electrode 7.
その後、有機半導体材料としてポリ(3-ヘキシルチオフェン)を0.1重量%濃度で溶解させたメシチレン溶液をインクジェット法によりパターニングし、半導体層8を形成した。
Thereafter, a mesitylene solution in which poly (3-hexylthiophene) as an organic semiconductor material was dissolved at a concentration of 0.1% by weight was patterned by an ink jet method to form a semiconductor layer 8.
実施例6として、図6に示す有機薄膜トランジスタ150を作製した。
As Example 6, an organic thin film transistor 150 shown in FIG.
基板1として厚さ0.7mmの無アルカリガラスを使用した。ガラス基板1上に、DCマグネトロンスパッタを用いてMoを400nmの膜厚で成膜し、フォトリソグラフィ法により所望の形状にパターニングを行い、ゲート電極2およびキャパシタ電極3を形成した。
Non-alkali glass with a thickness of 0.7 mm was used as the substrate 1. On the glass substrate 1, Mo was formed into a film having a thickness of 400 nm by using DC magnetron sputtering, and patterned into a desired shape by a photolithography method to form the gate electrode 2 and the capacitor electrode 3.
ゲート電極2およびキャパシタ電極3を形成した基板1に、感光性シリコーン樹脂をスリットコート法で塗布し、フォトリソグラフィ法によりパターニングし、200℃で焼成し、第一の絶縁層4を形成した。第一の絶縁層4の膜厚は、ゲート電極2上は1μmの膜厚とし、キャパシタ電極3上は0.5μmの膜厚として形成した。続いて感光性アクリル樹脂を塗布し、フォトリソグラフィ法によりパターニングし、第二の絶縁層5を0.5μmの膜厚で形成した。第一の絶縁層4の比誘電率は2.5、第二の絶縁層5の比誘電率は4.2である。
A photosensitive silicone resin was applied to the substrate 1 on which the gate electrode 2 and the capacitor electrode 3 were formed by a slit coating method, patterned by a photolithography method, and baked at 200 ° C. to form a first insulating layer 4. The film thickness of the first insulating layer 4 was 1 μm on the gate electrode 2 and 0.5 μm on the capacitor electrode 3. Subsequently, a photosensitive acrylic resin was applied and patterned by photolithography to form the second insulating layer 5 with a thickness of 0.5 μm. The relative dielectric constant of the first insulating layer 4 is 2.5, and the relative dielectric constant of the second insulating layer 5 is 4.2.
つづいて、銀ナノ粒子を分散させたインクを、インクジェット法を用いて所望の形状にパターニングし、180℃で1時間焼成し、ソース電極6およびドレイン電極7を形成した。
Subsequently, the ink in which the silver nanoparticles were dispersed was patterned into a desired shape using an ink jet method, and baked at 180 ° C. for 1 hour to form the source electrode 6 and the drain electrode 7.
その後、有機半導体材料としてポリ(3-ヘキシルチオフェン)を0.1重量%濃度で溶解させたメシチレン溶液をインクジェット法によりパターニングし、半導体層8を形成した。
Thereafter, a mesitylene solution in which poly (3-hexylthiophene) as an organic semiconductor material was dissolved at a concentration of 0.1% by weight was patterned by an ink jet method to form a semiconductor layer 8.
実施例7として、図7に示す有機薄膜トランジスタ160を作製した。
As Example 7, an organic thin film transistor 160 shown in FIG.
基板1として厚さ0.7mmの無アルカリガラスを使用した。ガラス基板1上に、銀(Ag)のナノ粒子を分散させた溶液をインクとして、インクジェット法を用いて所望の形状にパターニングし、150℃で1時間焼成し、ソース電極6およびドレイン電極7を形成した。
Non-alkali glass with a thickness of 0.7 mm was used as the substrate 1. A solution in which silver (Ag) nanoparticles are dispersed on a glass substrate 1 is used as an ink, and is patterned into a desired shape using an ink-jet method, followed by baking at 150 ° C. for 1 hour, and the source electrode 6 and the drain electrode 7 are formed. Formed.
ソース電極6およびドレイン電極7を形成した基板1に、有機半導体材料としてポリ(3-ヘキシルチオフェン)を0.1重量%濃度で溶解させたメシチレン溶液をインクジェット法によりパターニングし、半導体層8を形成した。
A mesitylene solution in which poly (3-hexylthiophene) as an organic semiconductor material is dissolved at a concentration of 0.1% by weight is patterned on the substrate 1 on which the source electrode 6 and the drain electrode 7 are formed, thereby forming a semiconductor layer 8. did.
その後、フッ素樹脂をインクジェット法で塗布し、第一の絶縁層4および第二の絶縁層5を形成する。図7に示すように、第二の絶縁層5の膜厚が第一の絶縁層4の膜厚よりも薄くなるように形成した。第一の絶縁層4の膜厚は1μm、第二の絶縁層5の膜厚は0.5μmとした。用いた樹脂の比誘電率は、2.0である。
Thereafter, a fluororesin is applied by an ink jet method to form the first insulating layer 4 and the second insulating layer 5. As shown in FIG. 7, the second insulating layer 5 was formed so as to be thinner than the first insulating layer 4. The film thickness of the first insulating layer 4 was 1 μm, and the film thickness of the second insulating layer 5 was 0.5 μm. The relative dielectric constant of the resin used is 2.0.
つづいて、銀ナノ粒子を分散させた溶液をインクとして、インクジェット法を用いて所望の形状にパターニングし、150℃で1時間焼成し、ゲート電極2およびキャパシタ電極3を形成した。
Subsequently, a solution in which silver nanoparticles were dispersed was used as an ink, and was patterned into a desired shape using an ink jet method, and baked at 150 ° C. for 1 hour to form the gate electrode 2 and the capacitor electrode 3.
実施例8として、図8に示す有機薄膜トランジスタ170を作製した。
As Example 8, an organic thin film transistor 170 shown in FIG.
基板1として厚さ0.7mmの無アルカリガラスを使用した。ガラス基板1上に、銀(Ag)のナノ粒子を分散させた溶液をインクとして、インクジェット法を用いて所望の形状にパターニングし、150℃で1時間焼成し、ソース電極6およびドレイン電極7を形成した。
Non-alkali glass with a thickness of 0.7 mm was used as the substrate 1. A solution in which silver (Ag) nanoparticles are dispersed on a glass substrate 1 is used as an ink, and is patterned into a desired shape using an ink-jet method, followed by baking at 150 ° C. for 1 hour, and the source electrode 6 and the drain electrode 7 are formed. Formed.
ソース電極6およびドレイン電極7を形成した基板1に、有機半導体材料としてポリ(3-ヘキシルチオフェン)を0.1重量%濃度で溶解させたメシチレン溶液をインクジェット法によりパターニングし、半導体層8を形成した。
A mesitylene solution in which poly (3-hexylthiophene) as an organic semiconductor material is dissolved at a concentration of 0.1% by weight is patterned on the substrate 1 on which the source electrode 6 and the drain electrode 7 are formed, thereby forming a semiconductor layer 8. did.
その後、半導体層8、ソース電極6、およびドレイン電極7の一部を覆うようにフッ素樹脂をインクジェット法により1μmの膜厚で塗布し、第一の絶縁層4を形成した。図8に示すように、第二の絶縁層5として酸化アルミニウム(Al2O3)を原子層体積法(ALD法)を用いて100nmの膜厚で成膜した。なお、電極の外部との接続部などに成膜された不要な酸化アルミニウム層は、フォトリソ法およびドライエッチング法を用いて除去した。第一の絶縁層4の比誘電率は2.0、第二の絶縁層5の比誘電率は9.3である。
Thereafter, a fluororesin was applied with a film thickness of 1 μm by an inkjet method so as to cover a part of the semiconductor layer 8, the source electrode 6, and the drain electrode 7, thereby forming the first insulating layer 4. As shown in FIG. 8, aluminum oxide (Al 2 O 3 ) was formed as the second insulating layer 5 to a thickness of 100 nm by using an atomic layer volume method (ALD method). Note that an unnecessary aluminum oxide layer formed on a connection portion with the outside of the electrode or the like was removed by using a photolithography method and a dry etching method. The relative dielectric constant of the first insulating layer 4 is 2.0, and the relative dielectric constant of the second insulating layer 5 is 9.3.
つづいて、銀ナノ粒子を分散させたインクを、インクジェット法を用いて所望の形状にパターニングし、150℃で1時間焼成し、ゲート電極2およびキャパシタ電極3を形成した。
Subsequently, the ink in which the silver nanoparticles were dispersed was patterned into a desired shape using an ink jet method, and baked at 150 ° C. for 1 hour to form the gate electrode 2 and the capacitor electrode 3.
実施例9として、図9に示す有機薄膜トランジスタ180を作製した。
As Example 9, an organic thin film transistor 180 shown in FIG.
基板1として厚さ0.7mmの無アルカリガラスを使用した。ガラス基板1上に、銀(Ag)のナノ粒子を分散させた溶液をインクとして、インクジェット法を用いて所望の形状にパターニングし、150℃で1時間焼成し、ソース電極6およびドレイン電極7を形成した。
Non-alkali glass with a thickness of 0.7 mm was used as the substrate 1. A solution in which silver (Ag) nanoparticles are dispersed on a glass substrate 1 is used as an ink, and is patterned into a desired shape using an ink-jet method, followed by baking at 150 ° C. for 1 hour, and the source electrode 6 and the drain electrode 7 are formed. Formed.
ソース電極6およびドレイン電極7を形成した基板1のドレイン電極7上の一部に原子層体積法(ALD法)を用いて100nmの膜厚で成膜した後、不要な酸化アルミニウム層を、フォトリソ法およびドライエッチング法を用いて除去し、第二の絶縁層5を形成した。第二の絶縁層5の比誘電率は9.3である。
After a film having a thickness of 100 nm is formed on a part of the drain electrode 7 of the substrate 1 on which the source electrode 6 and the drain electrode 7 are formed using an atomic layer volume method (ALD method), an unnecessary aluminum oxide layer is formed by photolithography. The second insulating layer 5 was formed by removing using a dry etching method. The relative dielectric constant of the second insulating layer 5 is 9.3.
次に、ソース電極6、ドレイン電極7、および基板1の一部にかかるように、有機半導体材料としてポリ(3-ヘキシルチオフェン)を0.1重量%濃度で溶解させたメシチレン溶液をインクジェット法によりパターニングし、半導体層8を形成した。
Next, a mesitylene solution in which poly (3-hexylthiophene) as an organic semiconductor material is dissolved at a concentration of 0.1% by weight as an organic semiconductor material so as to cover a part of the source electrode 6, the drain electrode 7, and the substrate 1 is formed by an inkjet method. The semiconductor layer 8 was formed by patterning.
その後、半導体層8、ソース電極6、およびドレイン電極7上の一部にフッ素樹脂をインクジェット法により、1μmの膜厚で塗布し、第一の絶縁層4を形成した。第一の絶縁層4の比誘電率は2.0である。
Thereafter, a fluororesin was applied to a part of the semiconductor layer 8, the source electrode 6, and the drain electrode 7 with a film thickness of 1 μm by an ink jet method to form the first insulating layer 4. The relative dielectric constant of the first insulating layer 4 is 2.0.
つづいて、銀ナノ粒子を分散させたインクを、インクジェット法を用いて所望の形状にパターニングし、150℃で1時間焼成し、ゲート電極2およびキャパシタ電極3を形成した。
Subsequently, the ink in which the silver nanoparticles were dispersed was patterned into a desired shape using an ink jet method, and baked at 150 ° C. for 1 hour to form the gate electrode 2 and the capacitor electrode 3.
(比較例1)
比較例1として、図10に示す有機薄膜トランジスタ200を作製した。 (Comparative Example 1)
As Comparative Example 1, an organicthin film transistor 200 shown in FIG.
比較例1として、図10に示す有機薄膜トランジスタ200を作製した。 (Comparative Example 1)
As Comparative Example 1, an organic
基板1として厚さ0.7mmの無アルカリガラスを使用した。ガラス基板1上に、DCマグネトロンスパッタを用いてMoを400nmの膜厚で成膜し、フォトリソグラフィ法により所望の形状にパターニングを行い、ゲート電極2およびキャパシタ電極3を形成した。
Non-alkali glass with a thickness of 0.7 mm was used as the substrate 1. On the glass substrate 1, Mo was formed into a film having a thickness of 400 nm by using DC magnetron sputtering, and patterned into a desired shape by a photolithography method to form the gate electrode 2 and the capacitor electrode 3.
ゲート電極2およびキャパシタ電極3を形成した基板1に、実施例1~3とは比誘電率の異なる感光性アクリル樹脂をスリットコート法で塗布し、フォトリソグラフィ法によりパターニングし、200℃で焼成し、ゲート電極2およびキャパシタ電極3上に第一の絶縁層4のみを形成した。第一の絶縁層4の膜厚は1μm、比誘電率は3.3である。
A photosensitive acrylic resin having a dielectric constant different from that of Examples 1 to 3 is applied to the substrate 1 on which the gate electrode 2 and the capacitor electrode 3 are formed by a slit coating method, patterned by a photolithography method, and baked at 200 ° C. Only the first insulating layer 4 was formed on the gate electrode 2 and the capacitor electrode 3. The film thickness of the first insulating layer 4 is 1 μm, and the relative dielectric constant is 3.3.
つづいて、銀ナノ粒子を分散させたインクを、インクジェット法を用いて所望の形状にパターニングし、150℃で1時間焼成し、ソース電極6およびドレイン電極7を形成した。
Subsequently, the ink in which the silver nanoparticles were dispersed was patterned into a desired shape using an ink jet method, and baked at 150 ° C. for 1 hour to form the source electrode 6 and the drain electrode 7.
その後、有機半導体材料としてポリ(3-ヘキシルチオフェン)を0.1重量%濃度で溶解させたメシチレン溶液をインクジェット法によりパターニングし、半導体層8を形成した。
Thereafter, a mesitylene solution in which poly (3-hexylthiophene) as an organic semiconductor material was dissolved at a concentration of 0.1% by weight was patterned by an ink jet method to form a semiconductor layer 8.
(比較例2)
比較例2として、図11に示す有機薄膜トランジスタ210を作製した。 (Comparative Example 2)
As Comparative Example 2, an organicthin film transistor 210 shown in FIG.
比較例2として、図11に示す有機薄膜トランジスタ210を作製した。 (Comparative Example 2)
As Comparative Example 2, an organic
基板1として厚さ0.7mmの無アルカリガラスを使用した。ガラス基板1上に、DCマグネトロンスパッタを用いてMoを400nmの膜厚で成膜し、フォトリソグラフィ法により所望の形状にパターニングを行い、ゲート電極2およびキャパシタ電極3を形成した。
Non-alkali glass with a thickness of 0.7 mm was used as the substrate 1. On the glass substrate 1, Mo was formed into a film having a thickness of 400 nm by using DC magnetron sputtering, and patterned into a desired shape by a photolithography method to form the gate electrode 2 and the capacitor electrode 3.
ゲート電極2およびキャパシタ電極3を形成した基板1に、感光性シリコーン樹脂をスリットコート法で塗布し、フォトリソグラフィ法によりパターニングし、200℃で焼成し、ゲート電極2およびキャパシタ電極3の上に第一の絶縁層4のみを形成した。第一の絶縁層4の膜厚は1μm、比誘電率は2.5である。
Photosensitive silicone resin is applied to the substrate 1 on which the gate electrode 2 and the capacitor electrode 3 are formed by slit coating, patterned by photolithography, and baked at 200 ° C. Only one insulating layer 4 was formed. The film thickness of the first insulating layer 4 is 1 μm and the relative dielectric constant is 2.5.
つづいて、銀ナノ粒子を分散させたインクを、インクジェット法を用いて所望の形状にパターニングし、180℃で1時間焼成し、ソース電極6およびドレイン電極7を形成した。
Subsequently, the ink in which the silver nanoparticles were dispersed was patterned into a desired shape using an ink jet method, and baked at 180 ° C. for 1 hour to form the source electrode 6 and the drain electrode 7.
その後、有機半導体材料としてポリ(3-ヘキシルチオフェン)を0.1重量%濃度で溶解させたメシチレン溶液をインクジェット法によりパターニングし、半導体層8を形成した。
Thereafter, a mesitylene solution in which poly (3-hexylthiophene) as an organic semiconductor material was dissolved at a concentration of 0.1% by weight was patterned by an ink jet method to form a semiconductor layer 8.
(比較例3)
比較例3として、図12に示す有機薄膜トランジスタ220を作製した。 (Comparative Example 3)
As Comparative Example 3, an organicthin film transistor 220 shown in FIG.
比較例3として、図12に示す有機薄膜トランジスタ220を作製した。 (Comparative Example 3)
As Comparative Example 3, an organic
基板1として厚さ0.7mmの無アルカリガラスを使用した。ガラス基板1上に、銀(Ag)のナノ粒子を分散させた溶液をインクとして、インクジェット法を用いて所望の形状にパターニングし、150℃で1時間焼成し、ソース電極6およびドレイン電極7を形成した。
Non-alkali glass with a thickness of 0.7 mm was used as the substrate 1. A solution in which silver (Ag) nanoparticles are dispersed on a glass substrate 1 is used as an ink, and is patterned into a desired shape using an ink-jet method, followed by baking at 150 ° C. for 1 hour, and the source electrode 6 and the drain electrode 7 are formed. Formed.
ソース電極6およびドレイン電極7を形成した基板1に、有機半導体材料としてポリ(3-ヘキシルチオフェン)を0.1重量%濃度で溶解させたメシチレン溶液をインクジェット法によりパターニングし、半導体層8を形成した。
A mesitylene solution in which poly (3-hexylthiophene) as an organic semiconductor material is dissolved at a concentration of 0.1% by weight is patterned on the substrate 1 on which the source electrode 6 and the drain electrode 7 are formed, thereby forming a semiconductor layer 8. did.
その後、半導体層8、ソース電極6、およびドレイン電極7を覆うようにフッ素樹脂をスリットコート法により膜厚1μmで塗布し、第一の絶縁層4を形成した。第一の絶縁層4の比誘電率は2.0である。
Thereafter, a fluororesin was applied with a film thickness of 1 μm by a slit coating method so as to cover the semiconductor layer 8, the source electrode 6, and the drain electrode 7, thereby forming the first insulating layer 4. The relative dielectric constant of the first insulating layer 4 is 2.0.
つづいて、銀ナノ粒子を分散させたインクを、インクジェット法を用いて所望の形状にパターニングし、150℃で1時間焼成し、ゲート電極2およびキャパシタ電極3を形成した。
Subsequently, the ink in which the silver nanoparticles were dispersed was patterned into a desired shape using an ink jet method, and baked at 150 ° C. for 1 hour to form the gate electrode 2 and the capacitor electrode 3.
以上の工程により、実施例1~9および比較例1~3に係る有機薄膜トランジスタを作製した。実施例1においては、第二の絶縁層5の膜厚を第一の絶縁層4の約半分にすることにより、キャパシタの容量を有機薄膜トランジスタ200と比較して2倍とすることができた。実施例2においては、第二の絶縁層5に高誘電率の膜を用いることで、キャパシタの容量を有機薄膜トランジスタ200と比較して大幅に増加させることができた。また、実施例3においては、第二の絶縁層5の比誘電率が第一の絶縁層4と比較して高いものを選択することにより、キャパシタの容量を有機薄膜トランジスタ200と比較して増加させることができた。いずれの実施例においても、キャパシタの容量を増加させることで、画像表示装置の書込み電圧の保持率を向上させ、安定的に画像表示装置を駆動させることが可能となった。
Through the above steps, organic thin film transistors according to Examples 1 to 9 and Comparative Examples 1 to 3 were produced. In Example 1, the capacitance of the capacitor could be doubled compared to the organic thin film transistor 200 by making the thickness of the second insulating layer 5 about half that of the first insulating layer 4. In Example 2, by using a film having a high dielectric constant for the second insulating layer 5, the capacitance of the capacitor could be significantly increased as compared with the organic thin film transistor 200. Further, in Example 3, the capacitance of the capacitor is increased as compared with the organic thin film transistor 200 by selecting the second insulating layer 5 having a relative dielectric constant higher than that of the first insulating layer 4. I was able to. In any of the embodiments, by increasing the capacitance of the capacitor, it is possible to improve the holding ratio of the writing voltage of the image display device and to drive the image display device stably.
実施例4においては、第一の絶縁層4よりも誘電率の大きい第二の絶縁層5とすることにより、キャパシタの容量を有機薄膜トランジスタ210と比較して1.6倍とすることができた。実施例5においては、第二の絶縁層5に高誘電率の膜を用いることで、キャパシタの容量を有機薄膜トランジスタ210と比較して約75倍と大幅に増加させることができた。また、実施例6においては、第二の絶縁層5の比誘電率が第一の絶縁層4と比較して高いものを選択することにより、キャパシタの容量を有機薄膜トランジスタ210と比較して約1.6倍に増加させることができた。いずれの実施例においても、キャパシタの容量を増加させることで、画像表示装置の書込み電圧の保持率を向上させ、安定的に画像表示装置を駆動させることが可能となった。
In Example 4, the capacitance of the capacitor could be 1.6 times that of the organic thin film transistor 210 by using the second insulating layer 5 having a dielectric constant larger than that of the first insulating layer 4. . In Example 5, by using a film having a high dielectric constant for the second insulating layer 5, the capacitance of the capacitor could be significantly increased by about 75 times compared to the organic thin film transistor 210. Further, in Example 6, by selecting a material having a relative dielectric constant of the second insulating layer 5 higher than that of the first insulating layer 4, the capacitance of the capacitor is about 1 compared with that of the organic thin film transistor 210. It was possible to increase it 6 times. In any of the embodiments, by increasing the capacitance of the capacitor, it is possible to improve the holding ratio of the writing voltage of the image display device and to drive the image display device stably.
実施例7においては、第二の絶縁層5の膜厚を第一の絶縁層4の約半分にすることにより、キャパシタの容量を有機薄膜トランジスタ220と比較して2倍とすることができた。実施例8においては、第二の絶縁層5に高誘電率の膜を用いることで、キャパシタの容量を有機薄膜トランジスタ220と比較して大幅に増加させることができた。また、実施例9においては、第二の絶縁層5の比誘電率が第一の絶縁層4と比較して高いものを選択することにより、キャパシタの容量を有機薄膜トランジスタ220と比較して増加させることができた。いずれの実施例においても、キャパシタの容量を増加させることで、画像表示装置の書込み電圧の保持率を向上させ、安定的に画像表示装置を駆動させることが可能となった。
In Example 7, the capacitance of the capacitor could be doubled compared to the organic thin film transistor 220 by making the film thickness of the second insulating layer 5 about half that of the first insulating layer 4. In Example 8, by using a film having a high dielectric constant for the second insulating layer 5, the capacitance of the capacitor could be significantly increased as compared with the organic thin film transistor 220. Further, in Example 9, the capacitance of the capacitor is increased as compared with the organic thin film transistor 220 by selecting the second insulating layer 5 having a higher relative dielectric constant than that of the first insulating layer 4. I was able to. In any of the embodiments, by increasing the capacitance of the capacitor, it is possible to improve the holding ratio of the writing voltage of the image display device and to drive the image display device stably.
以上説明したように、本発明によれば、キャパシタ電極3とドレイン電極7との間に形成される第二の絶縁層5の誘電率を大きくすることにより、薄膜トランジスタにおけるリーク電流を低く抑えながらキャパシタ容量を増加させることが可能となる。また、少なくともキャパシタ電極3とドレイン電極7との間に形成される第二の絶縁層5の膜厚を薄くすることで、さらにキャパシタ容量を増加させ、電圧保持率を向上させることが可能となる。
As described above, according to the present invention, the dielectric constant of the second insulating layer 5 formed between the capacitor electrode 3 and the drain electrode 7 is increased, so that the leakage current in the thin film transistor can be suppressed and the capacitor can be kept low. The capacity can be increased. In addition, by reducing the film thickness of at least the second insulating layer 5 formed between the capacitor electrode 3 and the drain electrode 7, it is possible to further increase the capacitor capacity and improve the voltage holding ratio. .
したがって、本発明によれば、印刷法を用いた有機薄膜トランジスタにおいて、十分なキャパシタ電極面積が確保できない場合においても、容量を確保することで、電圧保持率を維持し、安定して駆動可能な素子特性を示す有機薄膜トランジスタおよび画像表示装置を提供することが可能となる。
Therefore, according to the present invention, even in a case where a sufficient capacitor electrode area cannot be secured in an organic thin film transistor using a printing method, an element capable of maintaining a voltage holding ratio and stably driving by securing a capacitance. It becomes possible to provide an organic thin film transistor and an image display device exhibiting characteristics.
本発明は、画像表示装置、また各種センサーなどに好適に利用可能である。
The present invention can be suitably used for an image display device and various sensors.
1 基板
2 ゲート電極
3 キャパシタ電極
4 第一の絶縁層
5 第二の絶縁層 6 ソース電極
7 ドレイン電極
8 半導体層
9 保護層
10 層間絶縁膜
11 画素電極
100~180、200~220 有機薄膜トランジスタ DESCRIPTION OFSYMBOLS 1 Substrate 2 Gate electrode 3 Capacitor electrode 4 First insulating layer 5 Second insulating layer 6 Source electrode 7 Drain electrode 8 Semiconductor layer 9 Protective layer 10 Interlayer insulating film 11 Pixel electrode 100 to 180, 200 to 220 Organic thin film transistor
2 ゲート電極
3 キャパシタ電極
4 第一の絶縁層
5 第二の絶縁層 6 ソース電極
7 ドレイン電極
8 半導体層
9 保護層
10 層間絶縁膜
11 画素電極
100~180、200~220 有機薄膜トランジスタ DESCRIPTION OF
Claims (10)
- 絶縁性の基板上に少なくともゲート電極と、キャパシタ電極と、少なくとも前記ゲート電極を覆うように形成された第一の絶縁層と、少なくとも前記キャパシタ電極の一部を覆うように形成された第二の絶縁層と、ソース電極と、ドレイン電極と、有機半導体材料を含む半導体層を有する有機薄膜トランジスタであって、
前記第二の絶縁層の膜厚が、第一の絶縁膜の膜厚よりも薄い、有機薄膜トランジスタ。 On the insulating substrate, at least a gate electrode, a capacitor electrode, a first insulating layer formed to cover at least the gate electrode, and a second electrode formed to cover at least a part of the capacitor electrode An organic thin film transistor having an insulating layer, a source electrode, a drain electrode, and a semiconductor layer containing an organic semiconductor material,
An organic thin film transistor in which the film thickness of the second insulating layer is thinner than the film thickness of the first insulating film. - 絶縁性の基板上に少なくともゲート電極と、キャパシタ電極と、少なくとも前記ゲート電極を覆うように形成された第一の絶縁層と、少なくとも前記キャパシタ電極の一部を覆うように形成された第二の絶縁層と、ソース電極と、ドレイン電極と、有機半導体材料を含む半導体層を有する有機薄膜トランジスタであって、
前記第二の絶縁層の誘電率が前記第一の絶縁層の誘電率よりも大きい、有機薄膜トランジスタ。 On the insulating substrate, at least a gate electrode, a capacitor electrode, a first insulating layer formed to cover at least the gate electrode, and a second electrode formed to cover at least a part of the capacitor electrode An organic thin film transistor having an insulating layer, a source electrode, a drain electrode, and a semiconductor layer containing an organic semiconductor material,
An organic thin film transistor, wherein a dielectric constant of the second insulating layer is larger than a dielectric constant of the first insulating layer. - 前記第一の絶縁層が絶縁材料を2層以上積層してなる、請求項1または2に記載の有機薄膜トランジスタ The organic thin film transistor according to claim 1 or 2, wherein the first insulating layer is formed by laminating two or more insulating materials.
- 前記第二の絶縁層が絶縁材料を2層以上積層してなる、請求項1ないし3のいずれかに記載の有機薄膜トランジスタ。 The organic thin film transistor according to any one of claims 1 to 3, wherein the second insulating layer is formed by laminating two or more insulating materials.
- 前記第二の絶縁層が多層からなり、当該層の一部は、前記第一の絶縁層と同じ材料および組成である、請求項1ないし4のいずれか一項に記載の有機薄膜トランジスタ。 The organic thin film transistor according to any one of claims 1 to 4, wherein the second insulating layer is formed of a multilayer, and a part of the layer has the same material and composition as the first insulating layer.
- 絶縁性の基板上に少なくともソース電極と、ドレイン電極と、有機半導体材料を含む半導体層と、前記ソース電極および前記半導体層を覆うように形成された第一の絶縁層と、少なくとも前記ドレイン電極の一部を覆うように形成された第二の絶縁層と、ゲート電極と、キャパシタ電極と、を有する有機薄膜トランジスタであって、
前記第二の絶縁層の膜厚が、前記第一の絶縁層の膜厚よりも薄いことを特徴とする、有機薄膜トランジスタ。 At least a source electrode, a drain electrode, a semiconductor layer containing an organic semiconductor material, a first insulating layer formed so as to cover the source electrode and the semiconductor layer, and at least the drain electrode on an insulating substrate An organic thin film transistor having a second insulating layer formed so as to cover a part, a gate electrode, and a capacitor electrode,
An organic thin film transistor, wherein the thickness of the second insulating layer is thinner than the thickness of the first insulating layer. - 前記第二の絶縁層の誘電率が、前記第一の絶縁層の誘電率よりも大きいことを特徴とする、請求項6に記載の有機薄膜トランジスタ。 The organic thin film transistor according to claim 6, wherein a dielectric constant of the second insulating layer is larger than a dielectric constant of the first insulating layer.
- 前記第一の絶縁層が絶縁材料を2層以上積層してなることを特徴とする、請求項6または7に記載の有機薄膜トランジスタ。 The organic thin film transistor according to claim 6 or 7, wherein the first insulating layer is formed by laminating two or more insulating materials.
- 前記第二の絶縁層が絶縁材料を2層以上積層してなることを特徴とする、請求項6ないし8のいずれか一項に記載の有機薄膜トランジスタ。 9. The organic thin film transistor according to claim 6, wherein the second insulating layer is formed by laminating two or more insulating materials.
- 請求項1ないし9のいずれか一項に記載の有機薄膜トランジスタを用いた、画像表示装置。 An image display device using the organic thin film transistor according to any one of claims 1 to 9.
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JP2007293072A (en) * | 2006-04-26 | 2007-11-08 | Epson Imaging Devices Corp | Method of manufacturing electro-optical device and the electro-optical device, and electronic equipment |
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JP2019102602A (en) * | 2017-11-30 | 2019-06-24 | 株式会社Joled | Semiconductor device and display device |
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