JP2007293072A - Method of manufacturing electro-optical device and the electro-optical device, and electronic equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing an electro-optical device in which electrical connections with a lower-layer-side conductive layer formed below a gate insulating layer can be made efficiently, by using constitution for increasing the capacity value per unit area of retention capacitor, the electro-optical device, and to provide electronic equipment equipped with the electro-optical device. <P>SOLUTION: When an element substrate 10 of a liquid crystal device is constituted, a thick lower-layer side gate insulating layer 4a of the gate insulating layer is formed, then the lower-layer-side gate insulating layer 4a at a part overlapping with a lower electrode 3c, and in a formation region of a contact hole 89 for lower-layer side conductive layer connection is removed by dry etching. Then a thin upper-layer side gate insulating layer 4b is formed and used as a dielectric layer 4c of the retention capacitor 1h. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

The present invention relates to a method for manufacturing an electro-optical device having a thin film transistor and a storage capacitor on an element substrate, an electro-optical device, and an electronic apparatus.

Among various electro-optical devices, an active matrix type liquid crystal device includes, for example, FIG.
Liquid crystals are held between the element substrate 10 and the counter substrate (not shown) shown in (a) and (b). In the element substrate 10, a thin film transistor 1 for pixel switching is provided in each of a plurality of pixel regions 1e corresponding to the intersection of the gate line 3a (scanning line) and the source line 6a (data line).
c, and a pixel electrode 2a electrically connected to the drain region of the thin film transistor 1c
The liquid crystal orientation is controlled for each pixel by an image signal applied to the pixel electrode 2a from the source line 6a through the thin film transistor 1c. In the pixel region 1e, a storage capacitor 1h is formed in which a part of the capacitor line 3b or the like is the lower electrode 3c and an extended part of the drain electrode 6b is the upper electrode 6c. The gate insulating layer 4 of 1c is often used as the dielectric layer 4c. Here, if the capacitance value per unit area of the storage capacitor 1h is increased, the charge retention characteristics are improved. If the capacitance value per unit area of the storage capacitor 1h is increased, the occupied area can be reduced and the pixel aperture ratio can be increased. To do that,
The gate insulating layer 4 may be thinned, but in that case, the gate withstand voltage of the thin film transistor 1c is lowered.

Therefore, in forming a bottom gate thin film transistor in which a gate electrode, a gate insulating layer, and a semiconductor layer are sequentially stacked from the lower layer side, after forming the gate insulating layer, the semiconductor layer is formed in an island shape on the upper layer of the gate insulating layer. Next, the portion of the gate insulating layer that overlaps the lower electrode of the storage capacitor is etched halfway in the depth direction, and the portion whose thickness is reduced by etching is used as the dielectric layer of the storage capacitor. A configuration has been proposed (see Patent Document 1).

Further, in forming a top gate thin film transistor in which a semiconductor layer, a gate insulating layer, and a gate electrode are sequentially stacked from the lower layer side, a first insulating film made of a silicon oxide film formed by thermal oxidation of the semiconductor layer; After forming a laminated film with a second insulating film made of a silicon nitride film formed by a CVD method as a gate insulating layer, a region overlapping with the channel region of the gate insulating layer is covered with a resist mask, and the second insulating film Is removed by etching, and a configuration in which a thinned portion of the gate insulating layer is used as a dielectric layer of a storage capacitor has been proposed (see Patent Document 2).
Japanese Patent No. 2584290 Japanese Patent No. 3106656

In the element substrate 10, the lower conductive layer formed on the lower layer side of the gate insulating layer 4 is electrically connected to the lower conductive layer via the lower conductive layer connecting contact hole that penetrates the gate insulating layer 4 and the interlayer insulating film 8. Connection may be made. For example, the left end of FIG. 19B and FIG.
), The lower conductive layer 3s formed simultaneously with the gate line 3a and the upper conductive layer 6s formed simultaneously with the source line 6a are formed simultaneously with the pixel electrode 2a. There are cases where the conductive pattern 2s is electrically connected. In such a case, when the pixel electrode connecting contact hole 81 is formed in the passivation film 8, the upper conductive layer connecting contact hole 89 that electrically connects the upper conductive layer 6s and the conductive pattern 2s is simultaneously formed. Form.

However, since the contact hole 89 for connecting the lower conductive layer needs to penetrate both the passivation film 8 and the gate insulating layer 4, the contact hole 81
, 86 are difficult to form simultaneously. Therefore, to form the contact hole 89,
Etching for penetrating the gate insulating layer 4 is required after penetrating the passivation film 8, but it requires a long time for etching only by penetrating the gate insulating layer 4, resulting in low throughput. . Further, when dry etching is employed to form the lower-layer-side conductive layer connection contact hole 89, when the gate insulating layer 4 is thick, the gate insulating layer 4
Is exposed to static electricity or plasma for a long time, so that many defects occur in the gate insulating layer 4. As a result, the storage capacitor 1h used as a dielectric layer by reducing the thickness of the gate insulating layer 4 has a problem in that the withstand voltage is reduced and dielectric breakdown (short circuit) occurs.

In view of the above problems, the electrical connection to the lower conductive layer formed on the lower layer side of the gate insulating layer is efficiently performed using the configuration for increasing the capacitance value per unit area of the storage capacitor. An electro-optical device manufacturing method, an electro-optical device, and an electronic apparatus including the electro-optical device can be provided.

In order to solve the above problems, in the present invention, a thin film transistor, a pixel electrode electrically connected to the thin film transistor, and a gate insulating layer of the thin film transistor are sandwiched in each of a plurality of pixel regions on an element substrate. And a storage capacitor having a lower electrode and an upper electrode facing each other, and the element substrate penetrates the gate insulating layer and the interlayer insulating film with respect to the lower conductive layer formed on the lower layer side of the gate insulating layer. Forming a gate electrode of the thin film transistor, the lower electrode, and the lower conductive layer in the method of manufacturing an electro-optical device in which electrical connection is performed through a contact hole for connecting the lower conductive layer A gate insulating layer forming step for forming the gate insulating layer, and a semiconductor layer forming for forming a semiconductor layer of the thin film transistor A source / drain electrode forming step for forming source and drain electrodes of the thin film transistor, an interlayer insulating film forming step for forming the interlayer insulating film, a contact hole for connecting a pixel electrode by etching the interlayer insulating film, And a contact hole forming step for forming the lower conductive layer connecting contact hole and a pixel electrode forming step for forming the pixel electrode, and a region where the upper electrode and the lower electrode overlap with each other and the lower layer It is characterized by having a thinning process for reducing the film thickness by etching the gate insulating layer in the region where the side conductive layer connection contact hole is to be formed.

The electro-optical device manufactured by such a method includes, for example, a thin film transistor having a structure in which a gate electrode, a gate insulating layer, and a semiconductor layer are sequentially formed from the lower layer side in each of a plurality of pixel regions on an element substrate, A pixel electrode electrically connected to a drain region of the thin film transistor through a pixel electrode connecting contact hole formed in an interlayer insulating film covering the thin film transistor, and a lower electrode and an upper electrode facing each other with the gate insulating layer interposed therebetween And a lower-layer-side conductive layer connecting the lower-layer-side conductive layer formed on the lower-layer side of the gate insulating layer through the gate-insulating layer and the interlayer insulating film. Electrical connection is made through a contact hole. The gate insulating layer has a thickness that is greater than a region overlapping the lower electrode and the upper electrode, and a region overlapping the gate electrode and the semiconductor layer in the region where the contact hole for connecting the lower conductive layer is formed. Each having a thin first thin film portion and a second thin film portion, and the lower conductive layer connecting contact hole includes a lower hole penetrating the second thin film portion and an upper portion penetrating the interlayer insulating film. And a hall.

In the present invention, since the first thin film portion having a thin gate insulating layer is used as the dielectric layer of the storage capacitor, the thin film transistor can be held without lowering the gate withstand voltage and without causing the thin film transistor to have a large capacitance parasitically. The capacitance per unit area of the capacitance can be increased. Further, when forming the first thin film portion by thinning the gate insulating layer, the second thin film portion is formed by thinning the gate insulating layer even in the region where the contact hole for connecting the lower conductive layer is to be formed. Therefore, in the contact hole forming process, when the interlayer insulating film is etched to form the lower conductive layer connecting contact hole, the gate insulation remaining at the bottom when the upper hole of the lower conductive layer connecting contact hole is formed. The layer is thin. Accordingly, since the time required for etching the gate insulating layer when the lower conductive layer connecting contact hole is penetrated to the lower conductive layer is short, the throughput can be improved. In addition, when dry etching is used to form the contact hole for connecting the lower conductive layer, the gate insulating layer is not exposed to static electricity or plasma because the etching time is short, so defects occur in the gate insulating layer. Can be prevented. Therefore, even with a storage capacitor used as a dielectric layer with a thin gate insulating layer, the breakdown voltage is reduced and dielectric breakdown (short)
Does not occur.

In the method for manufacturing an electro-optical device according to the invention, in the gate insulating layer forming step, a lower layer on which a lower insulating layer composed of one or more insulating films constituting a lower layer side portion of the gate insulating layer is formed. Performing a side gate insulating layer forming step and an upper layer side gate insulating layer forming step of forming an upper gate insulating layer composed of one or more insulating films constituting the upper layer side portion of the gate insulating layer, It is preferable to perform the thinning step after the side gate insulating layer forming step and before the upper layer side gate insulating layer forming step.

In the electro-optical device manufactured by such a method, the gate insulating layer includes a lower gate insulating layer made of one or more insulating films and an upper gate insulating layer made of one or more insulating films. The first thin film portion and the second thin film portion are constituted by the removed portion of the lower gate insulating layer.

By adopting such a structure, the upper gate insulating layer and the semiconductor layer can be continuously formed, so that a clean interface can be formed between the gate insulating layer and the semiconductor layer. Can be improved. In addition, when using the part where the gate insulating layer is partially thinned as the dielectric layer of the storage capacitor, the gate insulating layer is formed only by the upper gate insulating layer without leaving the lower gate insulating layer. Therefore, it is not necessary to employ a configuration in which etching is performed up to a middle position in the depth direction. Therefore, it is possible to prevent variation in the storage capacitance due to variation in etching depth. Further, of the lower gate insulating layer and the upper gate insulating layer, the lower gate insulating layer is removed, and the upper gate insulating layer is used as a dielectric layer of the storage capacitor. For example, since the lower gate insulating layer is not exposed to static electricity or plasma when dry etching is partially performed, it is possible to prevent the upper gate insulating layer from being damaged or defective. Further, since the upper gate insulating layer does not come into contact with the etching solution when the lower gate insulating layer is partially wet etched, no pinhole is generated in the upper gate insulating layer. Therefore, it is possible to prevent the withstand voltage of the storage capacitor from being lowered.

In the present invention, after the gate insulating layer forming step is performed in a vacuum atmosphere, it is preferable that the element substrate is kept in the vacuum atmosphere until the semiconductor layer forming step is started.

In the present invention, in the contact hole forming step, it is preferable that etching is continuously performed until the contact hole for connecting the lower conductive layer reaches the lower conductive layer. In the present invention, since the thickness of the gate insulating layer at the portion where the contact hole for connecting the lower conductive layer is formed is thin, the etching is continuously performed until the contact hole for connecting the lower conductive layer reaches the lower conductive layer. Thus, even when the throughput is improved, the electrode located at the bottom of the pixel electrode connection contact hole is not significantly damaged.

The present invention is effective when applied to dry etching in the contact hole forming step.

In the present invention, in the pixel electrode forming step, a conductive pattern electrically connected to the lower conductive layer via the lower conductive layer connection contact hole may be formed simultaneously with the pixel electrode. In this case, in the source / drain electrode forming step, an upper conductive layer is formed simultaneously with the source and the drain electrode, and in the contact hole forming step, the interlayer insulating film is penetrated to reach the upper conductive layer. An upper conductive layer connecting contact hole is formed, and in the pixel electrode forming step, the conductive pattern is formed so as to be electrically connected to the upper conductive layer via the upper conductive layer connecting contact hole. May be.

In this invention, it has the bonding process which bonds the surface in which the conductive layer of the counter substrate was formed with respect to the said element substrate, and in this bonding process, it is a conductive material between the said element substrate and the said counter substrate. In some cases, the lower conductive layer and the conductive layer of the counter substrate are electrically connected in the contact hole for connecting the lower conductive layer.

The electro-optical device according to the present invention can be used in an electronic apparatus such as a mobile phone or a mobile computer.

Embodiments of the present invention will be described below with reference to the drawings. In the drawings used for the following description, the scales are different for each layer and each member in order to make each layer and each member large enough to be recognized on the drawing. Further, in the following description, parts having common functions are described with the same reference numerals so that the correspondence with the example shown in FIG. 19 becomes clear.

[Embodiment 1]
(Overall configuration of liquid crystal device)
FIGS. 1A and 1B are a plan view of a liquid crystal device (electro-optical device) as viewed from the side of the counter substrate together with each component formed thereon, and a cross-sectional view thereof taken along the line HH ′. . FIG.
), (B), the liquid crystal device 1 of the present embodiment is a TN (twisted nematic)
Mode, ECB (Electrically Controlled Birefrin
generation) mode, or VAN (Vertical Aligned Nemat)
ic) mode transmissive active matrix liquid crystal device. In the liquid crystal device 1, the element substrate 10 and the counter substrate 20 are bonded to each other through the sealing material 22, and the liquid crystal 1 is interposed therebetween.
f is held.

In the element substrate 10, the data line driving IC 60 and the scanning line driving IC 30 are mounted on the end region located outside the sealing material 22 and mounted along the side of the substrate. A terminal 12 is formed. The sealing material 22 is an adhesive made of a photo-curing resin or a thermosetting resin for bonding the element substrate 10 and the counter substrate 20 around them, and is used for setting the distance between the substrates to a predetermined value. Gap materials such as glass fiber or glass beads are blended. A liquid crystal injection port 25 is formed in the sealing material 22 by the discontinuous portion. After the liquid crystal 1f is injected, the sealing material 22 is sealed with a sealing material 26.

As will be described in detail later, thin film transistors 1c and pixel electrodes 2a are formed in a matrix on the element substrate 10, and an alignment film 19 is formed on the surface thereof. On the counter substrate 20, a frame 24 (not shown in FIG. 1B) made of a light-shielding material is formed in the inner region of the sealing material 22, and the inner side is an image display region 1 a. Although the illustration is omitted for the counter substrate 20,
A light shielding film called a black matrix or black stripe is formed in a region opposite to the vertical and horizontal boundary regions of each pixel, and on the upper layer side, a counter electrode 28 and an alignment film 2 are formed.
9 is formed. Although not shown in FIG. 1B, an RGB color filter is formed together with the protective film on the counter substrate 20 in a region facing each pixel of the element substrate 10. It can be used as a color display device for electronic devices such as computers, mobile phones, and liquid crystal televisions.

As schematically shown in FIG. 1 (a), between the element substrate 10 and the counter substrate 20, as will be described later, a conductive material 23 for inter-substrate conduction blended in the sealing material 22 causes the element to be Board 1
The constant potential wiring formed at 0 and the counter electrode 28 of the counter substrate 20 are electrically connected.

(Configuration of element substrate 10)
FIG. 2 is an explanatory diagram showing an electrical configuration of the element substrate of the liquid crystal device shown in FIG. As shown in FIG. 2, the element substrate 10 includes a plurality of source lines 6a (in a region corresponding to the image display region 1a.
The data line) and the gate line 3a (scanning line) are formed so as to cross each other, and the pixel 1b is formed at a position corresponding to the intersection of these wirings. The gate line 3a extends from the scanning line driving IC 30 and the source line 6a extends from the data line driving IC 60. Further, on the element substrate 10, a pixel switching thin film transistor 1c for controlling the driving of the liquid crystal 1f is formed in each pixel 1b. A source line 6a is electrically connected to a source of the thin film transistor 1c. A gate line 3a is electrically connected to the gate.

Furthermore, the capacitor substrate 3b is formed in the element substrate 10 in parallel with the gate line 3a. In this embodiment, the liquid crystal capacitor 1 formed between the thin film transistor 1 c and the counter substrate 20.
g is connected in series, and a holding capacitor 1h is connected in parallel to the liquid crystal capacitor 1g. Here, the capacitor line 3b is connected to the scanning line driving IC 30, but is held at a constant potential. Note that the storage capacitor 1h may be configured between the previous gate line 3a, and in this case, the capacitor line 3b can be omitted.

In the liquid crystal device 1 configured as described above, the thin film transistor 1c is turned on for a certain period of time so that an image signal supplied from the source line 6a is supplied to the liquid crystal capacitance 1g of each pixel 1b.
Is written at a predetermined timing. The image signal of a predetermined level written in the liquid crystal capacitor 1g is
The liquid crystal capacitor 1g is held for a certain period, and the hold capacitor 1h prevents the image signal held in the liquid crystal capacitor 1g from leaking.

(Configuration of each pixel)
3A, 3B, and 3C are plan views of one pixel of the liquid crystal device according to Embodiment 1 of the present invention, when the liquid crystal device is cut at a position corresponding to A1-B1. It is sectional drawing and a top view of a contact part. FIG. 4 is an explanatory diagram of a contact portion of the liquid crystal device. In FIG. 3A, the pixel electrode is indicated by a thick and long dotted line, the gate line and a thin film simultaneously formed therewith are indicated by a thin solid line, the source line and a thin film simultaneously formed therewith are indicated by a thin one-dot chain line, Is indicated by a thin and short dotted line. In the gate insulating layer constituting the storage capacitor, the thin film portion is indicated by a thin two-dot chain line, and the contact hole is indicated by a thin solid line as in the case of the gate line.

As shown in FIG. 3A, in the element substrate 10, the following elements constituting the pixel 1b are configured in the pixel region 1e surrounded by the gate line 3a and the source line 6a. First, in the pixel region 1e, a semiconductor layer 7a made of an amorphous silicon film constituting an active layer of the bottom gate type thin film transistor 1c is formed. A gate electrode is formed by a protruding portion from the gate line 3a. In the semiconductor layer 7a, a source line 6a overlaps with a source side end portion as a source electrode, and a drain electrode 6b overlaps with a drain side end portion. A capacitor line 3b is formed in parallel with the gate line 3a.

In the pixel region 1e, a storage capacitor 1h is formed in which a protruding portion from the capacitor line 3b is a lower electrode 3c and an extended portion from the drain electrode 6b is an upper electrode 6c. The upper electrode 6
For c, an ITO film (Indium Tin) is formed through contact holes 81 and 91.
The pixel electrode 2a made of Oxide) is electrically connected, and the contact hole 81
Corresponds to the pixel electrode connection contact hole in the present invention.

An A1-B1 cross section of the element substrate 10 configured as described above is expressed as shown in FIG. First, a gate line 3a (gate electrode) and a capacitor line 3b (lower electrode 3c of a storage capacitor 1h) are formed on an insulating substrate 11 made of a glass substrate or a quartz substrate. In this embodiment, each of the gate line 3a and the capacitor line 3b has a two-layer structure in which a molybdenum film having a thickness of 20 nm is stacked on a neodymium-containing aluminum alloy film having a thickness of 150 nm.

In this embodiment, the gate insulating layer 4 is provided on the upper layer side of the gate line 3a so as to cover the gate line 3a.
Is formed. In the upper layer of the gate insulating layer 4, a semiconductor layer 7a constituting an active layer of the thin film transistor 1c is formed in a region partially overlapping with the protruding portion (gate electrode) of the gate line 3a. Of the semiconductor layer 7a, an ohmic contact layer 7b made of a doped silicon film and a source line 6a are stacked on the upper layer of the source region, and an ohmic contact layer 7c made of a doped silicon film on the upper layer of the drain region. And drain electrode 6
b is formed, and the thin film transistor 1c is configured. The upper electrode 6c of the storage capacitor 1h is formed by the extended portion of the drain electrode 6b. In this embodiment, the semiconductor layer 7
a is made of an intrinsic amorphous silicon film having a thickness of 150 nm, and the ohmic contact layers 7b and 7c are made of an n ⁺ type amorphous silicon film having a thickness of 50 nm doped with phosphorus. Each of the source line 6a and the drain electrode 6b (upper electrode 6c) includes a molybdenum film having a thickness of 5 nm, an aluminum film having a thickness of 1500 nm, and a molybdenum film having a thickness of 50 nm from the lower layer side to the upper layer side. It has a laminated three-layer structure.

A passivation film 8 (interlayer insulating film) made of a silicon nitride film and a planarizing film 9 made of a photosensitive resin layer such as an acrylic resin are formed on the upper layer side of the source line 6a, drain electrode 6b, and upper electrode 6c. The pixel electrode 2a is formed on the planarizing film 9. The pixel electrode 2a is electrically connected to the upper electrode 6c through a contact hole 91 formed in the planarizing film 9 and a contact hole 81 formed in the passivation film 8, and is connected through the upper electrode 6c and the drain electrode 6b. Are electrically connected to the drain region of the thin film transistor 1c. An alignment film 19 is formed on the surface of the pixel electrode 2a. In this embodiment, the passivation film 8 is made of a silicon nitride film having a thickness of 250 nm, and the pixel electrode 2a is made of an ITO film having a thickness of 100 nm.

The counter substrate 20 is disposed so as to face the element substrate 10 configured as described above, and the liquid crystal 1 f is held between the element substrate 10 and the counter substrate 20. The counter substrate 20 is provided with a color filter 27 for each color, a counter electrode 28, and an alignment film 29, and a liquid crystal capacitor 1g (see FIG. 2) is formed between the pixel electrode 2a and the counter electrode 28. Note that a black matrix, a protective film, or the like may be formed on the counter substrate 20 side, but the illustration thereof is omitted.

The liquid crystal device 1 includes various contact portions 1s described with reference to FIG.
Among such contact portions 1s, a typical configuration is the left end portion of FIG. 3B and FIG.
). Of the contact portion 1s shown in FIG. 4, the contact portion 1 shown in FIG.
s is a top view of the area | region which comprises the bidirectional | two-way diode (electrostatic protection element) shown in FIG.4 (b) on the element substrate 10 using two thin-film transistors. Here, the two thin film transistors are formed at the same time as the pixel switching thin film transistor 1c, and have the same structure as the pixel switching thin film transistor 1c, such as including a semiconductor layer 7s formed simultaneously with the semiconductor layer 7a. Yes. However, one of the source / drain electrodes functions as a diode by electrically connecting the gate electrode. In order to configure such a diode, the lower conductive layer 3s formed simultaneously with the gate line 3a, and the source line 6a
It is necessary to electrically connect the upper conductive layer 6s formed at the same time. Therefore, in this embodiment, as shown in FIGS. 3B, 3C, and 4A, the conductive pattern 2s formed simultaneously with the pixel electrode 2a passes through the passivation film 8 and the gate insulating layer 4. The lower conductive layer 3s is electrically connected to the lower conductive layer 3s through the lower conductive layer connecting contact hole 89, and is connected to the upper conductive layer 6s through the upper conductive layer connecting contact hole 86 that penetrates the passivation film 8. It is electrically connected.

4C and 4D, the contact portion 1s shown in FIG.
The mounting terminals 12 and the terminals for mounting the bumps of the data line driving IC 60 and the scanning line driving IC 30 are configured, and the pixel electrode is connected to the lower conductive layer 3s formed simultaneously with the gate line 3a. The conductive pattern 2s formed simultaneously with 2a is electrically connected through the lower conductive layer connecting contact hole 89 penetrating the passivation film 8 and the gate insulating layer 4, and a terminal is constituted by the conductive pattern 2s. .

Further, the contact portion 1s shown in FIGS. 4E and 4F is described with reference to FIG. 1A with respect to the lower conductive layer 3s formed simultaneously with the gate line 3a in the element substrate 10. The lower conductive layer 3 s is a portion that electrically connects the counter electrode 28 of the counter substrate 20 through the conductive material 23, and the lower conductive layer 3 s is a contact hole for connecting the upper conductive layer that penetrates the passivation film 8 and the gate insulating layer 4. The upper side is open by 89.

The configuration of the contact portion 1s shown in FIGS. 4C to 4F is a modification of the configuration of the contact portion 1s shown in FIGS. 3B and 3C and FIGS. 4A and 4B. Therefore, the configuration of the contact portion 1s shown in FIGS. 3B and 3C and FIGS. 4A and 4B will be mainly described below.

(Detailed configuration of gate insulating layer, dielectric layer, and contact part)
In FIG. 3B again, the gate insulating layer 4 has a two-layer structure of a lower gate insulating layer 4a made of a thick silicon nitride film on the lower layer side and an upper gate insulating layer made of a thin silicon nitride film on the upper layer side. It has become. In this embodiment, the film thickness of the lower gate insulating layer 4a is formed so as to reduce the influence of the parasitic capacitance of the thin film transistor, and the film thickness of the upper gate insulating film is formed thinner than that of the lower gate insulating film. . For example, the lower gate insulating film is 250 to 500 nm.
The thickness of the upper gate insulating layer 4b is preferably 50 to 200 nm and preferably 100 nm. These film thicknesses are determined by optimization in consideration of the balance between the writing capability, the parasitic capacitance, and the storage capacitance of the thin film transistor. For example, when the pixel 1b has a high definition and a small size (for example, the short side of one pixel is 40 μm or less), the storage capacitor 1h and the liquid crystal capacitor 1g in the pixel 1b are small. Ruled by resolution. For this reason, in such a high-definition pixel, the ratio of the parasitic capacitance of the thin film transistor 1c to the capacitance of the entire pixel increases. This parasitic capacitance ratio (
Hereinafter, it is known that when the parasitic capacitance ratio) is increased, the electro-optical device 1 is known to cause display quality degradation such as flicker, crosstalk, and burn-in, and the parasitic capacitance ratio is designed to be as small as possible. Is common. However, when the parasitic capacitance ratio is restricted by the high-definition layout as described above, it is difficult to improve this with the conventional method. However, if the structure and process of the present invention are used, the thickness of the gate insulating film of the thin film transistor 1c can be set and manufactured completely independently of the storage capacitor 1h side. That is, in the high-definition pixel, the parasitic capacitance of the thin film transistor 1c can be reduced and the parasitic capacitance ratio can be reduced by setting the gate insulating film thicker than the standard condition. In such a condition setting, the current driving capability (signal writing capability to the pixel) of the thin film transistor 1c is reduced. However, in the high-definition pixel, the pixel capacitance itself to be written is small. The design can be performed so that there is no problem in the writing ability even if the film thickness is increased.

In this embodiment, the lower gate insulating layer 4a in the gate insulating layer 4 is removed over the entire thickness direction in a region overlapping the lower electrode 3c and the upper electrode 6c of the storage capacitor 1h, and an opening 41 is formed. Yes. On the other hand, the upper gate insulating layer 4b is formed on substantially the entire surface. For this reason, the gate insulating layer 4 is a thin first film composed of only the upper-side gate insulating layer 4b in a region overlapping the lower electrode 3c and the upper electrode 6c (region overlapping the opening 41 in a plane). A thin film portion 4c is provided, and the dielectric layer of the storage capacitor 1h is configured by the first thin film portion 4c. Here, on the upper layer side of the lower electrode 3c, a thick portion having the same thickness as the gate insulating layer 4 remains along the edge of the lower electrode 3c, and the dielectric layer 4c is surrounded by the thick insulating film. ing. For this reason, it is possible to prevent a withstand voltage drop that easily occurs at the edge portion of the lower electrode 3c and the edge portion of the upper electrode 6c.

Further, in the present embodiment, even in the contact portion 1s, the contact hole 89 for connecting the lower conductive layer side
In the formation region, the lower gate insulating layer 4a of the gate insulating layer 4 is removed over the entire thickness direction, and an opening 43 is formed. Here, the opening 43 is formed over a wide range surrounding the lower-layer-side conductive layer connection contact hole 89, but is located in a region where the lower-layer-side conductive layer 3s is formed. On the other hand, the upper layer side gate insulating layer 4 b is also formed inside the opening 43. For this reason, the gate insulating layer 4 is provided with a thin second thin film portion 4d composed of only the upper gate insulating layer 4b above the lower conductive layer 3s. Therefore, the lower conductive layer connecting contact hole 89 includes the upper hole 87 penetrating the passivation film and the second thin film portion 4d having only the upper gate insulating layer 4b of the gate insulating layer 4 having a small thickness. And a lower hole 46 penetrating therethrough.

(Manufacturing method of the liquid crystal device 1)
FIGS. 5A to 5G and FIGS. 6A to 6E are process cross-sectional views illustrating a method for manufacturing the element substrate 10 used in the liquid crystal device 1 of the present embodiment. In addition, in order to manufacture the element substrate 10, the following processes are performed in the state of the large sized substrate which can take many element substrates 10, but in the following description,
A large substrate will be described as the element substrate 10.

First, in the gate electrode formation step shown in FIG. 5A, a metal film (a 150 nm thick aluminum alloy film and a 20 nm thick molybdenum film is laminated on the surface of an insulating substrate 11 such as a large glass substrate). After the film is formed, the metal film is patterned using a photolithography technique, and the gate line 3a (gate electrode), the capacitor line 3b (lower electrode 3c), and the lower-layer side conductive layer 3s are formed simultaneously.

Next, as shown in FIG. 5B, in the gate insulating layer forming step (lower gate insulating layer forming step), a thick lower gate insulating layer constituting the lower layer side of the gate insulating layer 4 is formed by plasma CVD. 4a is formed. In this embodiment, the lower gate insulating layer 4a has a film thickness of about 30.
It consists of a 0 nm silicon nitride film.

Next, in the thinning process shown in FIG. 5C, the lower electrode 3 is formed by using a photolithography technique.
After the formation of a resist mask (not shown) having an opening in the contact portion 1 s and a region overlapping with c in a plane, the lower gate insulating layer 4 a is reacted with a fluorine-based etching gas such as SF _6. Openings 41 and 43 are formed by performing reactive ion etching (dry etching). Such reactive ion etching utilizes the synergistic effect of the physical sputtering effect of ions and the chemical etching effect of radicals, and therefore has excellent anisotropy and high productivity.

Next, in the gate insulating layer forming step (upper layer side gate insulating layer forming step) shown in FIG.
The thin upper gate insulating layer 4 constituting the upper layer side of the gate insulating layer 4 is formed by plasma CVD.
b is formed. In this embodiment, the upper gate insulating layer 4b is made of a silicon nitride film having a thickness of about 100 nm. As a result, a gate insulating layer 4 including a thick lower gate insulating layer 4a and a thin upper gate insulating layer 4b is formed on the upper layer side of the gate line 3a (gate electrode). On the other hand, a first thin film portion 4c made only of the upper gate insulating layer 4b is formed in a region overlapping the opening 41 in a plane, and an upper gate insulating layer is formed in a region overlapping the opening 43 in a plane. A second thin film portion 4d consisting only of the layer 4b is formed.

Next, in the semiconductor layer forming step shown in FIG. 5E, the film thickness is 15 by plasma CVD.
An intrinsic amorphous silicon film 7d having a thickness of 0 nm and an n ⁺ type silicon film 7e having a thickness of 50 nm are successively formed. At that time, the semiconductor substrate forming process shown in FIG. 5E is performed while the element substrate 10 subjected to the upper gate insulating layer forming process shown in FIG. Avoid contact with the atmosphere. Thereby, the amorphous silicon film 7d can be laminated with the surface of the gate insulating layer 4 (upper gate insulating layer 4b) being clean.

Next, as shown in FIG. 5F, the amorphous silicon film 7d and the n ⁺ -type silicon film 7e are etched using a photolithography technique, and the island-shaped semiconductor layer 7a and the island-shaped n ⁺ A type silicon film 7e is formed. Also in this etching, reactive ion etching (dry etching) using a fluorine-based etching gas such as SF ₆ is performed.

Next, in the source / drain electrode formation step shown in FIG. 5G, a metal film (a laminated film of a molybdenum film having a thickness of 5 nm, an aluminum film having a thickness of 1500 nm, and a molybdenum film having a thickness of 50 nm) is formed. After the formation, patterning is performed using a photolithography technique to form the source line 6a, the drain electrode 6b, the upper electrode 6c, and the upper conductive layer 6s. continue,
Using the source line 6a and the drain electrode 6b as a mask, the n ⁺ type silicon film 7e between the source line 6a and the drain electrode 6b is removed by etching to separate the source and drain. As a result, the n ⁺ -type silicon film 7e is removed from the region where the source line 6a and the drain electrode 6b are not formed, and ohmic contact layers 7b and 7c are formed. At that time, a part of the surface of the semiconductor layer 7a is etched. In this manner, a bottom gate type pixel switching thin film transistor 1c is formed, and a storage capacitor 1h is formed.

Next, in the interlayer insulating film forming step shown in FIG. 6A, a passivation film 8 made of a silicon nitride film having a thickness of 250 nm is formed by plasma CVD.

Next, in the flattening film forming step shown in FIG. 6B, a photosensitive resin such as an acrylic resin is applied by spin coating, then exposed and developed, and then the flattening film 9 provided with the contact holes 91 is formed. Form.

Next, in the contact hole forming step shown in FIG. 6C, the passivation film 8 is etched using a photolithography technique, so that the pixel electrode connection contact hole 81, the upper conductive layer connection contact hole 86, Then, a contact hole 89 for connecting the lower conductive layer is formed. Also in this etching, reactive ion etching (dry etching) using a fluorine-based etching gas such as SF ₆ is performed.

At that time, the pixel electrode connection contact hole 81 and the upper conductive layer connection contact hole 86 are formed simultaneously because they only penetrate the passivation film 8, but the lower conductive layer connection contact hole 89 is Since it is necessary to penetrate the passivation film 8 and the gate insulating layer 4, only the upper hole 87 that penetrates the passivation film 8 is formed in the contact hole 89 for connecting the lower conductive layer.

Therefore, in the contact hole forming step, another mask is formed by using the photolithography technique, and the gate insulating layer 4 (located at the bottom of the upper hole 87 (see FIG. 6D)).
The upper gate insulating layer 4b / second thin film portion 4d) is removed. As a result, the gate insulating layer 4
The lower hole 46 is formed, and the lower conductive layer connecting contact hole 89 reaches the lower conductive layer 3s. Also in this etching, reactive ion etching (dry etching) using a fluorine-based etching gas such as SF ₆ is performed.

Next, in the pixel electrode formation step shown in FIG. 6E, the film thickness is 100 nm by sputtering.
After forming the ITO film, patterning is performed using a photolithography technique and wet etching to form the pixel electrode 2a. As a result, the pixel electrode 2a is electrically connected to the upper electrode 6c through the contact holes 91 and 81. Subsequently, the alignment film 19 shown in FIG.
After forming a polyimide film for forming, a rubbing treatment is performed.

In this way, the element substrate 10 on which various wirings and TFTs are formed in the state of a large substrate is bonded to the separately formed large counter substrate 20 and the sealing material 22 and then cut into a predetermined size. As a result, the liquid crystal injection port 25 is opened.
After injecting the liquid crystal 1 f between the counter substrate 20 and the counter substrate 20, the liquid crystal injection port 25 is sealed with a sealing material 26.

(Main effects of this form)
As described above, in the liquid crystal device 1 of the present embodiment, the first thin film portion 4c in which the gate insulating layer 4 is thin is used as the dielectric layer of the storage capacitor 1h, so that the gate withstand voltage of the thin film transistor 1c is not reduced. The capacitance per unit area of the holding capacitor 1h can be increased. In addition, the upper gate insulating layer 4b constituting the dielectric layer 4c is a silicon nitride film (relative dielectric constant is about 7 to 8), and has a higher dielectric constant than the silicon oxide film. Capacitance per hit is high. Therefore, the holding capacitor 1h has a high charge holding characteristic,
The pixel aperture ratio can be increased by reducing the occupied area as the capacitance value per unit area increases.

In the present embodiment, when forming the first thin film portion 4c by thinning the gate insulating layer 4, the gate insulating layer 4 is thinned even in the region where the lower-layer-side conductive layer connection contact hole 89 is to be formed. 2 thin film portions 4d are formed. Therefore, in the contact hole forming step, when the passivation film 8 is etched to form the lower conductive layer connection contact hole 89, the bottom hole is formed when the upper hole 87 of the lower conductive layer connection contact hole 89 is formed. The remaining gate insulating layer 4 is thin. Therefore, since the time required for etching the gate insulating layer 4 when the lower conductive layer connecting contact hole 89 is penetrated to the lower conductive layer 3s is short, the throughput can be improved.

Furthermore, in this embodiment, dry etching is employed to form the lower-layer-side conductive layer connection contact hole 89, but the thickness of the gate insulating layer 4 where the lower-layer-side conductive layer connection contact hole 89 is formed is thin. Accordingly, since the time for dry etching is short and the time for which the gate insulating layer is exposed to static electricity or plasma is short, it is possible to prevent the gate insulating layer 4 from being defective. Therefore, even with the storage capacitor 1h used as a dielectric layer by reducing the film thickness of the gate insulating layer 4, it is possible to prevent a decrease in withstand voltage and occurrence of dielectric breakdown (short circuit).

In this embodiment, since the thin film transistor 1c has a bottom gate structure, the upper gate insulating layer 4b, the intrinsic amorphous silicon film 7d for forming the active layer (semiconductor layer 7a), and the ohmic contact layers 7b and 7c are provided. Since the n ⁺ -type silicon film 7e for the configuration can be continuously formed, the amorphous silicon film 7d can be formed on the clean upper gate insulating layer 4b. In addition, in this embodiment, when the upper gate insulating layer 4b, the amorphous silicon film 7d, and the ohmic contact layers 7b and 7c are formed, the element substrate 10 is kept in a vacuum atmosphere, so that the upper gate insulating layer 4b Surface contamination can be reliably prevented. Therefore, the interface between the gate insulating layer 4 and the semiconductor layer 7a is clean, and the thin film transistor 1c has high reliability.

Further, in the present embodiment, when the portion where the gate insulating layer 4 is partially thinned is used as the dielectric layer 4c of the storage capacitor 1h, the lower gate insulating layer 4a is not left, but only the upper gate insulating layer 4b is used as the dielectric. Since the layer 4c is configured, unlike the case where the lower gate insulating layer 4a is partially left, it is possible to prevent the capacitance variation of the storage capacitor 1h due to the variation in the etching depth. In addition, in this embodiment, the portion where the gate insulating layer 4 is partially thinned is the storage capacitor 1
When used as the dielectric layer 4c of h, the lower layer side gate insulating layer 4a is removed from the lower layer side gate insulating layer 4a and the upper layer side gate insulating layer 4b, and the upper layer side formed on the upper layer of the lower layer side gate insulating layer 4a The gate nitride film 4b is used as the dielectric layer 4c of the storage capacitor 1h. With such an upper gate insulating layer 4b, the upper gate insulating layer 4b is not exposed to static electricity or plasma when the lower gate insulating layer 4a is removed by dry etching.
The defect density is low. Therefore, it is possible to prevent problems such as a decrease in the withstand voltage of the storage capacitor 1h.

In this embodiment, the lower gate insulating layer 4a is dry-etched to form the opening 4
1 is formed, the opening 41 may be formed by wet etching. Even in such a case, since the upper gate insulating layer 4b does not come into contact with the etching solution for the lower gate insulating layer 4a, no pinhole is generated in the upper gate insulating layer 4b. Therefore, it is possible to prevent the withstand voltage of the storage capacitor 1h from varying.

[Improvement of Embodiment 1]
In the first embodiment, after forming the upper hole 87 of the contact hole 89 for lower layer side conductive layer connection in the contact hole forming step shown in FIG. 6C, in another etching step, shown in FIG. 6D. As described above, the lower insulating layer 46 is formed by removing the gate insulating layer 4 (upper layer side gate insulating layer 4b / second thin film portion 4d) located at the bottom of the upper hole 87, but in this embodiment, the upper electrode 6c is formed. The upper conductive layer 6s is thick, and the gate insulating layer 4 is thin at the portion where the lower conductive layer connection contact hole 89 is formed. Therefore, after performing the interlayer insulating film forming step shown in FIG. 7A and the planarizing film forming step shown in FIG. 7B by the same method as in the first embodiment, it is shown in FIG. 7C. In the contact hole forming step, the contact holes 81, 86, and 89 may be simultaneously formed, and then the pixel electrode forming step shown in FIG.

The present embodiment is not limited to the first embodiment, and can be applied to any embodiment described below.

[Embodiment 2]
8A, 8B, and 8C are plan views of one pixel of the liquid crystal device according to the second embodiment of the present invention, when the liquid crystal device is cut at a position corresponding to A2-B2. It is sectional drawing and a top view of a contact part. 9A to 9G show the element substrate 10 used in the liquid crystal device 1 of the present embodiment.
It is process sectional drawing which shows the process until forming a source / drain electrode among these manufacturing processes. In this embodiment and any of the embodiments described below, in the plan view, the pixel electrode is indicated by a thick and long dotted line, the gate line and a thin film formed simultaneously with the gate line are indicated by a thin solid line, and the source line and the thin line formed simultaneously are formed. The thin film is indicated by a thin alternate long and short dashed line, the semiconductor layer is indicated by a thin and short dotted line, and the thin film portion of the gate insulating layer constituting the storage capacitor is indicated by a thin two-dot chain line,
The contact hole is indicated by a thin solid line as with the gate line. Further, in this embodiment and any of the embodiments described below, the basic configuration of this embodiment is the same as that of Embodiment 1, and therefore, common portions are denoted by the same reference numerals and illustrated. Those descriptions are omitted.

As shown in FIGS. 8A and 8B, in this embodiment as well, in the element substrate 10, the pixel region 1e surrounded by the gate line 3a and the source line 6a has a bottom gate type. A thin film transistor 1c and a storage capacitor 1h are formed. In the storage capacitor 1h, a protruding portion from the capacitor line 3b is a lower electrode 3c, and an extended portion from the drain electrode 6b is an upper electrode 6c. As in the first embodiment, the gate insulating layer 4 includes a lower gate insulating layer 4a made of a lower silicon nitride film and an upper gate insulating layer made of an upper thin silicon nitride film.
It has a layered structure. The lower gate insulating layer 4a is removed over the entire thickness direction in a region overlapping the lower electrode 3c and the upper electrode 6c of the storage capacitor 1h in a plane, and an opening 41 is formed. For this reason, the dielectric layer of the storage capacitor 1 h is the first thin film of the gate insulating layer 4.
Thin film portion 4c (lower gate insulating layer 4a). The lower electrode 3c
On the upper layer side, an insulating film having the same thickness as the gate insulating layer 4 is formed along the edge of the lower electrode 3c, and the dielectric layer 4c is surrounded by the thick insulating film.

Also in this embodiment, as in the first embodiment, as shown in FIGS. 8B and 8C, the gate insulating layer 4 is formed in the contact portion 1s even in the formation region of the lower-layer-side conductive layer connection contact hole 89, as shown in FIGS. The lower gate insulating layer 4a is removed over the entire thickness direction, and an opening 43 is formed. For this reason, the gate insulating layer 4 is formed on the upper layer side gate insulating layer 4 on the lower layer side conductive layer 3s.
the lower conductive layer connecting contact hole 89 includes an upper hole 87 penetrating the passivation film and an upper gate of the gate insulating layer 4. And a lower hole 46 penetrating the thin second thin film portion 4d made of only the insulating layer 4b.

In this embodiment, the etching stopper layer 7x is formed in the region sandwiched between the end of the source line 6a (source electrode) and the end of the drain electrode 6b on the upper layer side of the semiconductor layer 7a. Ohmic contact layers 7b and 7c are formed so as to cover the upper layer of the stopper layer 7x. In this embodiment, the etching stopper layer 7x is made of a silicon nitride film having a thickness of 150 nm. Since other configurations are the same as those of the first embodiment, description thereof is omitted.

In order to manufacture the element substrate 10 having such a configuration, a metal film (a laminated film of an aluminum alloy film and a molybdenum film) is formed on the surface of the insulating substrate 11 in the gate electrode formation step shown in FIG. Thereafter, the metal film is patterned using a photolithography technique, and the gate line 3
a (gate electrode), capacitor line 3b (lower electrode 3c), and lower conductive layer 3s are formed.

Next, in the lower gate insulating layer forming step shown in FIG.
After forming a thick silicon nitride film (lower gate insulating layer 4a) constituting the lower layer side of the gate insulating layer 4 by plasma CVD, the lower gate insulating layer 4a is etched in the thinning process, Openings 41 and 43 are formed. Next, in the upper layer side gate insulating layer forming step shown in FIG. 9C, a thin silicon nitride film (upper side gate insulating layer 4b) constituting the upper layer side of the gate insulating layer 4 is formed. As a result, the gate insulating layer 4 includes the first thin film portion 4.
c and the second thin film portion 4d are formed.

Next, in the semiconductor layer forming step shown in FIG. 9D, an intrinsic amorphous silicon film 7d is formed by plasma CVD. At that time, the element substrate 10 subjected to the upper-layer side gate insulating layer forming step shown in FIG. 9C is subjected to the semiconductor layer forming step shown in FIG. 10 is not in contact with the atmosphere. As a result, the amorphous silicon film 7d is cleaned with the surface of the gate insulating layer 4 (upper gate insulating layer 4b) clean.
(Active layer) can be stacked. Next, the film thickness is 150 on the upper layer side of the amorphous silicon film 7d.
After forming a silicon nitride film of nm, the silicon nitride film is etched to form an etching stopper layer 7x. Also in this etching, reactive ion etching (dry etching) using a fluorine-based etching gas such as SF ₆ is performed.

Next, as shown in FIG. 9E, an n ⁺ -type silicon film 7e is formed on the upper layer side of the etching stopper layer 7x. Next, as shown in FIG. 9F, the amorphous silicon film 7d and the n ⁺ -type silicon film 7e are dry-etched using a photolithography technique, and the island-shaped semiconductor layer 7a and the n ⁺ -type silicon are then etched. A film 7e is formed.

Next, in the source / drain electrode formation step shown in FIG. 9G, a metal film (molybdenum film,
(A laminated film of an aluminum film and a molybdenum film) and then patterned using a photolithography technique to form a source line 6a, a drain electrode 6b, an upper electrode 6c, and an upper conductive layer 6s. Subsequently, using the source line 6a and the drain electrode 6b as a mask, the n ⁺ -type silicon film 7e between the source line 6a and the drain electrode 6b is removed by etching to separate the source and drain. As a result, the n ⁺ -type silicon film 7e is removed from the region where the source line 6a and the drain electrode 6b are not formed, and ohmic contact layers 7b and 7c are formed. At that time, the etching stopper layer 7x has a function of protecting the semiconductor layer 7a. In this manner, a bottom gate type pixel switching thin film transistor 1c is formed, and a storage capacitor 1h is formed. Since the subsequent steps are the same as those in the first embodiment, description thereof is omitted.

Thus, in this embodiment, since the basic configuration of the storage capacitor 1h is the same as that of Embodiment 1, a highly reliable thin film transistor 1c can be formed, and a storage capacitor 1h having a large capacity and stable withstand voltage can be provided. The effects similar to those of the first embodiment can be obtained.

As shown in FIG. 9D, when the etching stopper layer 7x is formed, the amorphous silicon film 7d has a function of protecting the upper gate insulating layer 4b. Therefore, even when the etching stopper layer 7x is formed, it is possible to prevent a defect from occurring in the upper gate insulating layer 4b used as the dielectric layer 4c.

[Embodiment 3]
FIGS. 10A, 10B, and 10C are plan views of one pixel of the liquid crystal device according to Embodiment 2 of the present invention, when the liquid crystal device is cut at a position corresponding to A3-B3. It is sectional drawing and a top view of a contact part. FIGS. 11A to 11G are process cross-sectional views showing processes up to formation of source / drain electrodes in the manufacturing process of the element substrate 10 used in the liquid crystal device 1 of the present embodiment.

As shown in FIGS. 10A and 10B, in the present embodiment as well, the element substrate 10 is the same as in the first embodiment.
In FIG. 2, a bottom gate type thin film transistor 1c and a storage capacitor 1h are formed in the pixel region 1e surrounded by the gate line 3a and the source line 6a.

In this embodiment, the storage capacitor 1h is the same as that of Embodiment 1 in that the protruding portion from the capacitor line 3b is the lower electrode 3c. However, the upper electrode 5a of the storage capacitor 1h is connected to the gate insulating layer 4
The upper electrode 5a is electrically connected to the drain electrode 6b through a partially overlapping portion with the drain electrode 6b. In this embodiment, the thickness of the ITO film constituting the upper electrode 5a is 50 nm. Note that the pixel electrode 2 a formed in the upper layer of the planarizing film 9 is electrically connected to the upper electrode 5 a through the contact holes 81 and 91.

As in the first embodiment, the gate insulating layer 4 has a two-layer structure of a lower gate insulating layer 4a made of a thick silicon nitride film on the lower layer side and an upper gate insulating layer made of a thin silicon nitride film on the upper layer side. It has become. The lower gate insulating layer 4a is removed over the entire thickness direction in a region overlapping the lower electrode 3c and the upper electrode 5a of the storage capacitor 1h in a plane, and an opening 41 is formed. For this reason, the dielectric layer of the storage capacitor 1 h is constituted by the first thin film portion 4 c (lower gate insulating layer 4 a) having a small thickness in the gate insulating layer 4. In the upper layer side of the lower electrode 3c, an insulating film having the same thickness as that of the gate insulating layer 4 is formed along the edge of the lower electrode 3c. The dielectric layer 4c is surrounded by the thick insulating film. ing.

Also in this embodiment, as in the first embodiment, as shown in FIGS. 10B and 10C, the gate insulating layer 4 is formed in the contact portion 1 s even in the formation region of the lower-layer-side conductive layer connection contact hole 89. The lower gate insulating layer 4a is removed over the entire thickness direction, and an opening 43 is formed. For this reason, the gate insulating layer 4 includes a second thin film portion 4d having a thin film thickness composed of only the upper gate insulating layer 4b above the lower conductive layer 3s, and a lower conductive layer connecting contact hole 89. The upper hole 87 that penetrates the passivation film and the gate insulating layer 4
Among them, a lower hole 46 penetrating through the thin second thin film portion 4d made of only the upper gate insulating layer 4b is provided. Since other configurations are the same as those of the first embodiment, description thereof is omitted.

In order to manufacture the element substrate 10 having such a configuration, a metal film (a laminated film of an aluminum alloy film and a molybdenum film) is formed on the surface of the insulating substrate 11 in the gate electrode formation step shown in FIG. Thereafter, the metal film is patterned using a photolithography technique to form the gate line 3a (gate electrode), the capacitor line 3b (lower electrode 3c), and the lower conductive layer 3s.

Next, as in the first embodiment, in the lower gate insulating layer forming step shown in FIG. 11B, a thick silicon nitride film (lower gate insulating layer) constituting the lower layer of the gate insulating layer 4 is formed by plasma CVD. After the formation of the layer 4a), the lower gate insulating layer 4a is etched to form openings 41 and 43 in the thinning step. Next, in the upper layer side gate insulating layer forming step shown in FIG. 11C, a thin silicon nitride film (upper side gate insulating layer 4b) constituting the upper layer side of the gate insulating layer 4 is formed. As a result, the first thin film portion 4 c and the second thin film portion 4 d are formed in the gate insulating layer 4.

Next, in the semiconductor layer forming step shown in FIG. 11D, an intrinsic amorphous silicon film 7d and an n ⁺ -type silicon film 7e are sequentially formed. At that time, the element substrate 10 subjected to the upper gate insulating layer forming step shown in FIG. 11C is subjected to the semiconductor layer forming step shown in FIG. 10 is not in contact with the atmosphere. Thereby, the amorphous silicon film 7d (active layer) can be laminated in a state where the surface of the gate insulating layer 4 (upper gate insulating layer 4b) is clean.

Next, as shown in FIG. 11E, the amorphous silicon film 7d and the n ⁺ -type silicon film 7e are dry-etched by using a photolithography technique to form the island-shaped semiconductor layer 7a and the island-shaped n ^{A +} type silicon film 7e is formed.

Next, in the upper electrode formation step shown in FIG.
After the m-th ITO film is formed, the upper electrode 5a is formed by performing wet etching on the ITO film using a photolithography technique. In this way, the storage capacitor 1h is formed.

Next, as shown in FIG. 11G, after forming a metal film (a laminated film of a molybdenum film, an aluminum film, and a molybdenum film), patterning is performed using a photolithography technique,
A source line 6a, a drain electrode 6b, an upper electrode 6c, and an upper conductive layer 6s are formed. Subsequently, using the source line 6a and the drain electrode 6b as a mask, the n ⁺ -type silicon film 7e between the source line 6a and the drain electrode 6b is removed by etching to separate the source and drain. As a result, the n ⁺ -type silicon film 7e is removed from the region where the source line 6a and the drain electrode 6b are not formed, and ohmic contact layers 7b and 7c are formed. In this way, the bottom gate type pixel switching thin film transistor 1c is formed. Since the subsequent steps are the same as those in the first embodiment, description thereof is omitted.

Thus, in this embodiment, since the basic configuration of the storage capacitor 1h is the same as that of Embodiment 1, a highly reliable thin film transistor 1c can be formed, and a storage capacitor 1h having a large capacity and stable withstand voltage can be provided. The effects similar to those of the first embodiment can be obtained.

Further, since the ITO film (transparent electrode) is used as the upper electrode 5a, the pixel aperture ratio can be increased as compared with the case where the extended portion of the drain electrode 6b is used as the upper electrode.

[Embodiment 4]
12A, 12 </ b> B, and 12 </ b> C are plan views for one pixel of the liquid crystal device according to Embodiment 4 of the present invention, when the liquid crystal device is cut at a position corresponding to A <b> 4-B <b> 4. It is sectional drawing and a top view of a contact part. FIGS. 13A to 13G are process cross-sectional views showing processes until a contact hole is formed in the passivation film in the manufacturing process of the element substrate 10 used in the liquid crystal device 1 of the present embodiment.

As shown in FIGS. 12 (a) and 12 (b), in the present embodiment as well, the element substrate 10 is the same as in the first embodiment.
In FIG. 2, a bottom gate type thin film transistor 1c and a storage capacitor 1h are formed in the pixel region 1e surrounded by the gate line 3a and the source line 6a. However, unlike the first to third embodiments, in this embodiment, the planarization film is not formed, and the pixel electrode 2a is formed in the upper layer of the passivation film 8, and the pixel electrode connection formed in the passivation film 8 is performed. It is electrically connected to the drain electrode 6b through the contact hole 81 for use.

The storage capacitor 1h is the same as that of the first embodiment in that the protruding portion from the capacitor line 3b is the lower electrode 3c. However, the upper electrode of the storage capacitor 1h is the lower electrode 3 of the pixel electrode 2a.
It is comprised by the part which overlaps with c planarly.

As in the first embodiment, the gate insulating layer 4 has a two-layer structure of a lower gate insulating layer 4a made of a thick silicon nitride film on the lower layer side and an upper gate insulating layer made of a thin silicon nitride film on the upper layer side. It has become. The lower gate insulating layer 4a is removed over the entire thickness direction in a region overlapping the lower electrode 3c and the pixel electrode 2a of the storage capacitor 1h in a plane, and an opening 41 is formed. For this reason, the dielectric layer of the storage capacitor 1 h is the first thin film of the gate insulating layer 4.
Thin film portion 4c (lower gate insulating layer 4a). The lower electrode 3c
On the upper layer side, an insulating film having the same thickness as the gate insulating layer 4 is formed along the edge of the lower electrode 3c, and the dielectric layer 4c is surrounded by the thick insulating film.

Also in this embodiment, as in the first embodiment, as shown in FIGS. 12B and 12C, the gate insulating layer 4 is also formed in the contact portion 1s in the formation region of the lower-layer-side conductive layer connection contact hole 89, as shown in FIGS. The lower gate insulating layer 4a is removed over the entire thickness direction, and an opening 43 is formed. For this reason, the gate insulating layer 4 includes a second thin film portion 4d having a thin film thickness composed of only the upper gate insulating layer 4b above the lower conductive layer 3s, and a lower conductive layer connecting contact hole 89. The upper hole 87 that penetrates the passivation film and the gate insulating layer 4
Among them, a lower hole 46 penetrating through the thin second thin film portion 4d made of only the upper gate insulating layer 4b is provided. Since other configurations are the same as those of the first embodiment, description thereof is omitted.

In order to manufacture the element substrate 10 having such a configuration, a metal film (a laminated film of an aluminum alloy film and a molybdenum film) is formed on the surface of the insulating substrate 11 in the gate electrode forming step shown in FIG. Thereafter, the metal film is patterned using a photolithography technique to form a gate line 3a (gate electrode), a capacitor line 3b (lower electrode 3c), and a lower conductive layer 3s.

Next, as in the first embodiment, in the lower gate insulating layer forming step shown in FIG. 13B, a thick silicon nitride film (lower gate insulating layer) constituting the lower layer of the gate insulating layer 4 is formed by plasma CVD. After forming the layer 4a), in the thinning process, the lower gate insulating layer 4a is etched to form openings 41 and 43 at positions overlapping the lower electrode 3c. next,
In the upper layer side gate insulating layer forming step shown in FIG. 13C, a thin silicon nitride film (upper side gate insulating layer 4b) constituting the upper layer side of the gate insulating layer 4 is formed. As a result, the first thin film portion 4 c and the second thin film portion 4 d are formed in the gate insulating layer 4.

Next, in the semiconductor layer forming step shown in FIG. 13D, an intrinsic amorphous silicon film 7d and an n ⁺ -type silicon film 7e are sequentially formed. At that time, the element substrate 10 subjected to the upper-layer side gate insulating layer forming step shown in FIG. 13C is subjected to the semiconductor layer forming step shown in FIG. 10 is not in contact with the atmosphere. Thereby, the amorphous silicon film 7d (active layer) can be laminated in a state where the surface of the gate insulating layer 4 (upper gate insulating layer 4b) is clean.

Next, as shown in FIG. 13E, the amorphous silicon film 7d and the n ⁺ -type silicon film 7e are dry-etched by using a photolithography technique to form the island-shaped semiconductor layer 7a and the island-shaped n ^{A +} type silicon film 7e is formed.

Next, as shown in FIG. 13F, after forming a metal film (a laminated film of a molybdenum film, an aluminum film, and a molybdenum film), patterning is performed using a photolithography technique,
A source line 6a, a drain electrode 6b, an upper electrode 6c, and an upper conductive layer 6s are formed. Subsequently, using the source line 6a and the drain electrode 6b as a mask, the n ⁺ -type silicon film 7e between the source line 6a and the drain electrode 6b is removed by etching to separate the source and drain. As a result, the n ⁺ -type silicon film 7e is removed from the region where the source line 6a and the drain electrode 6b are not formed, and ohmic contact layers 7b and 7c are formed. In this way, the bottom gate type pixel switching thin film transistor 1c is formed.

Next, as shown in FIG. 13G, after forming a passivation film 8 made of a silicon nitride film having a thickness of 250 nm by plasma CVD in the interlayer insulating film forming step,
In the contact hole forming step, the passivation film 8 is etched using a photolithography technique, so that the pixel electrode connection contact hole 81, the upper conductive layer connection contact hole 86, and the lower conductive layer connection contact hole 89 are formed. Form. Also in this etching, reactive ion etching (dry etching) using a fluorine-based etching gas such as SF ₆ is performed. Since the subsequent steps are the same as those in the first embodiment, description thereof is omitted.

Thus, in this embodiment, since the basic configuration of the storage capacitor 1h is the same as that of Embodiment 1, a highly reliable thin film transistor 1c can be formed, and a storage capacitor 1h having a large capacity and stable withstand voltage can be provided. The effects similar to those of the first embodiment can be obtained.

[Embodiment 5]
FIGS. 14A, 14B, and 14C are plan views of one pixel of the liquid crystal device according to Embodiment 5 of the present invention, when the liquid crystal device is cut at a position corresponding to A5-B5. It is sectional drawing and a top view of a contact part.

As shown in FIGS. 14 (a) and 14 (b), in this embodiment as well, the element substrate 10 is the same as in the first embodiment.
In FIG. 2, a bottom gate type thin film transistor 1c and a storage capacitor 1h are formed in the pixel region 1e surrounded by the gate line 3a and the source line 6a. However, unlike the first to fourth embodiments, the capacitor line is not formed in this embodiment, and the previous stage in the scanning direction (direction intersecting with the extending direction of the gate line 3a / extending direction of the source line 6a). A lower electrode 3c of the storage capacitor 1h is constituted by a part of the gate line 3a on the side.

In the storage capacitor 1h, an upper electrode 6d is formed in a region overlapping with the lower electrode 3c. In this embodiment, a metal layer formed simultaneously with the source line 6a and the drain electrode 6b is used as the upper electrode 6d. ing. Here, the upper electrode 6d is formed separately from the drain electrode 6b. For this reason, the pixel electrode 2a formed in the upper layer of the planarizing film 9 is electrically connected to the upper electrode 6d through the contact hole 81 of the passivation film 8 and the contact hole 91 of the planarizing film 9, and the passivation film 8 and the contact hole 92 of the planarizing film 9 are electrically connected to the drain electrode 6b.

As in the first embodiment, the gate insulating layer 4 has a two-layer structure of a lower gate insulating layer 4a made of a thick silicon nitride film on the lower layer side and an upper gate insulating layer made of a thin silicon nitride film on the upper layer side. It has become. The lower gate insulating layer 4a is removed over the entire thickness direction in a region overlapping the lower electrode 3c and the upper electrode 6d of the storage capacitor 1h in a plane, and an opening 41 is formed. For this reason, the dielectric layer of the storage capacitor 1 h is constituted by the first thin film portion 4 c (lower gate insulating layer 4 a) having a small thickness in the gate insulating layer 4. In the upper layer side of the lower electrode 3c, an insulating film having the same thickness as that of the gate insulating layer 4 is formed along the edge of the lower electrode 3c. The dielectric layer 4c is surrounded by the thick insulating film. ing.

Also in this embodiment, as in the first embodiment, as shown in FIGS. 14B and 14C, the gate insulating layer 4 is formed in the contact portion 1 s even in the formation region of the lower-layer-side conductive layer connection contact hole 89. The lower gate insulating layer 4a is removed over the entire thickness direction, and an opening 43 is formed. For this reason, the gate insulating layer 4 includes a second thin film portion 4d having a thin film thickness composed of only the upper gate insulating layer 4b above the lower conductive layer 3s, and a lower conductive layer connecting contact hole 89. The upper hole 87 that penetrates the passivation film and the gate insulating layer 4
Among them, a lower hole 46 penetrating through the thin second thin film portion 4d made of only the upper gate insulating layer 4b is provided. Since other configurations are the same as those of the first embodiment, description thereof is omitted.

The element substrate 10 having such a configuration can be basically manufactured by the same method as in the first embodiment. That is, in the gate electrode formation step shown in FIG.
The gate line 3a is formed in the planar shape shown in FIG. When forming the source line 6a and the drain electrode 6b in the source / drain electrode formation step shown in FIG. 5G, the upper electrode 6d is formed. Further, in the planarizing film forming step shown in FIG. 6B, the planarizing film 9 including the contact holes 91 and 92 is formed, and in the contact hole forming step shown in FIG. When the passivation film 8 is etched using the contact holes 81 and 82, the contact holes 81 and 82 are overlapped with the contact holes 91 and 92, respectively.
Form. Further, a contact hole 89 is formed in the contact portion 1s.

[Embodiment 6]
FIGS. 15A, 15B, and 15C are plan views of one pixel of the liquid crystal device according to Embodiment 6 of the present invention, when the liquid crystal device is cut at a position corresponding to A6-B6. It is sectional drawing and a top view of a contact part. FIGS. 16A to 16E are process cross-sectional views showing processes up to forming source / drain electrodes in the manufacturing process of the element substrate 10 used in the liquid crystal device 1 of the present embodiment.

In the first to fifth embodiments, the lower gate insulating layer 4a is removed to form the first thin film portion 4c and the second thin film portion 4d, but FIGS. In this embodiment, the upper gate insulating layer 4b is removed to form the recesses 42 and 44, and the first thin film portion 4c and the second thin film portion 4d are formed. Since other configurations are the same as those of the first embodiment, detailed description thereof is omitted.

In order to manufacture the element substrate 10 having such a configuration, a metal film (a laminated film of an aluminum alloy film and a molybdenum film) is formed on the surface of the insulating substrate 11 in the gate electrode forming step shown in FIG. Thereafter, the metal film is patterned by using a photolithography technique to form the gate line 3a (gate electrode), the capacitor line 3b (lower electrode 3c), and the lower conductive layer 3s.

Next, in the gate insulating layer forming step shown in FIG. 15B, a thin lower gate insulating layer 4a constituting the lower layer side of the gate insulating layer 4 and a thick upper gate insulating layer constituting the upper layer side of the gate insulating layer 4 Layer 4b is formed. Subsequently, in the semiconductor layer forming step, an intrinsic amorphous silicon film 7d for forming an active layer and an n ⁺ type silicon film 7e for forming an ohmic contact layer are sequentially formed, and etching is performed. As shown in (c), the semiconductor layer 7a and the n ⁺ type silicon film 7e constituting the active layer are patterned in an island shape. Next, in the thinning process shown in FIG. 15D, the upper gate insulating layer 4a is etched to remove the upper gate insulating layer 4b, and the recesses 42 and 44 are formed. Next, in the source / drain electrode formation step, after forming a conductive film, etching is performed to form a source electrode (source line 6a) and a drain electrode 6b. Subsequently, the n ⁺ -type silicon film 7e is etched to form ohmic contact layers 7b and 7c. as a result,
A thin film transistor 1c is formed. In addition, a storage capacitor 1h is formed in which the lower gate insulating layer 4a is the dielectric layer 4c and the extended portion of the drain electrode 6b is the upper electrode 6c. Since the subsequent steps are the same as those in the first embodiment, description thereof is omitted.

Even in the element substrate 10 having such a configuration, since the thickness of the gate insulating layer 4 where the contact hole 89 for connecting the lower conductive layer is formed is thin, the gate insulating layer becomes static or plasma because of the short dry etching time. There are effects such as shortening the time of exposure.

[Embodiment 7]
17A, 17B, and 17C are plan views of one pixel of the liquid crystal device according to Embodiment 7 of the present invention, when the liquid crystal device is cut at a position corresponding to A7-B7. It is sectional drawing and a top view of a contact part.

In the first to sixth embodiments, the gate insulating layer 4 employs a two-layer structure of the lower gate insulating layer 4a and the upper gate insulating layer 4b, and the upper gate insulating layer 4b is removed to remove the first thin film. Although the portion 4c and the second thin film portion 4d are formed, as shown in FIGS. 17A, 17B, and 17C, in this embodiment, the gate insulating layer 4 is constituted by a single insulating film. Then, the gate insulating layer 4 is removed by etching to an intermediate position in the thickness direction to remove the first thin film portion 4c and the second thin film portion 4c.
The thin film portion 4d is formed. Since other configurations are the same as those of the first embodiment, detailed description thereof is omitted. Since the element substrate 10 having such a structure can be manufactured by the same method as in the sixth embodiment, the description thereof will be omitted. However, the thickness of the gate insulating layer 4 at the portion where the lower-layer-side conductive layer connection contact hole 89 is formed is Since it is thin, the dry etching time is short, and the time that the gate insulating layer is exposed to static electricity or plasma can be shortened.

[Other embodiments]
In the first to sixth embodiments, both the lower gate insulating layer 4a and the upper gate insulating layer 4b constituting the gate insulating layer 4 are composed of the same insulating film. 4a and upper gate insulating layer 4b may be composed of different insulating films. In this case, when the gate insulating layer 4 is constituted by a silicon oxide film and a silicon nitride film, the upper gate insulating layer 4b used as the dielectric layer 4c is preferably constituted by a silicon nitride film having a high dielectric constant. In the above embodiment, the lower gate insulating layer 4a and the upper gate insulating layer 4b are each composed of a single insulating film. However, the lower gate insulating layer 4a and the upper gate insulating layer 4b are provided. However, each may be composed of a plurality of insulating films.

In the first to fifth embodiments described above, when the portion where the gate insulating layer 4 is partially thinned is used as the dielectric layer 4c of the storage capacitor 1h, the lower gate insulating layer 4a only in the inner region from the outer periphery of the lower electrode 3c. In the case where the withstand voltage drop that is likely to occur at the edge portion of the lower electrode 3c and the edge portion of the upper electrode is not a problem, or when other measures are taken,
The lower gate insulating layer 4a may be removed over a region wider than the lower electrode 3c and the upper electrode.

In the above embodiment, a multilayer film of an aluminum alloy film and a molybdenum film is used for the gate line 3a, and a multilayer film of an aluminum film and a molybdenum film is used for the source line 6a, but other metal films are used for these wirings. Further, a conductive film such as a silicide film may be used. In the above embodiment, an intrinsic amorphous silicon film is used as the semiconductor layer 7a. However, another silicon film, an organic semiconductor film, or a transparent semiconductor film such as zinc oxide may be used.

In the above embodiment, a transmissive liquid crystal device has been described as an example. However, the present invention may be applied to a transflective liquid crystal device or a totally reflective liquid crystal device. In the above embodiment, TN
Although the active matrix type liquid crystal device in the mode, ECB mode, and VAN mode has been described as an example, the present invention may be applied to a liquid crystal device (electro-optical device) in an IPS (In-Plane Switching) mode.

Furthermore, the electro-optical device is not limited to a liquid crystal device, and an organic EL (electroluminescence) device, for example, is electrically connected to a thin film transistor in each pixel region on an element substrate holding an organic EL film as an electro-optical material. Since the pixel electrode connected to and the storage capacitor having the lower electrode on the lower layer side than the gate insulating layer of the thin film transistor are formed, the present invention may be applied to such an organic EL device.

[Embodiment of Electronic Device]
FIG. 18 shows an embodiment in which the liquid crystal device according to the present invention is used as a display device of various electronic devices. The electronic device shown here is a personal computer, a cellular phone, or the like, and includes a display information output source 170, a display information processing circuit 171, a power supply circuit 172, a timing generator 173, and the liquid crystal device 1. Further, the liquid crystal device 1 includes a panel 175 and a drive circuit 176, and the above-described liquid crystal device 1 can be used. The display information output source 170 includes a ROM (Read Only Memory) and a RAM (Random).
A memory unit such as an access memory), a storage unit such as various disks, a tuning circuit that tunes and outputs a digital image signal, and a display such as an image signal of a predetermined format based on various clock signals generated by the timing generator 173 Information is supplied to the display information processing circuit 171. The display information processing circuit 171
It is equipped with various known circuits such as a serial-parallel conversion circuit, an amplification / inversion circuit, a rotation circuit, a gamma correction circuit, a clamp circuit, etc., and executes processing of input display information,
The image signal is supplied to the drive circuit 176 together with the clock signal CLK. The power supply circuit 172 supplies a predetermined voltage to each component.

(A), (b) is the top view which looked at the liquid crystal device (electro-optical device) from the opposing substrate side with each component formed on it, respectively, and its HH 'sectional drawing. It is explanatory drawing which shows the electrical structure of the element substrate of the liquid crystal device shown in FIG. (A), (b), (c) is a plan view of one pixel of the liquid crystal device according to Embodiment 1 of the present invention, and a cross section when the liquid crystal device is cut at a position corresponding to A1-B1. It is a figure and a top view of a contact part. It is explanatory drawing of the contact part of the liquid crystal device to which this invention was applied. (A)-(g) is process sectional drawing which shows the manufacturing method of the element substrate used for the liquid crystal device shown in FIG. (A)-(e) is process sectional drawing which shows the manufacturing method of the element substrate used for the liquid crystal device shown in FIG. (A)-(d) is process sectional drawing which shows another manufacturing method of the element substrate using the liquid crystal device which concerns on Embodiment 1 of this invention. (A), (b), (c) is a plan view for one pixel of the liquid crystal device according to Embodiment 2 of the present invention, and a cross section when the liquid crystal device is cut at a position corresponding to A2-B2. It is a figure and a top view of a contact part. (A)-(g) is process sectional drawing which shows the manufacturing method of the element substrate used for the liquid crystal device shown in FIG. (A), (b), (c) is a plan view of one pixel of the liquid crystal device according to Embodiment 3 of the present invention, and a cross section when the liquid crystal device is cut at a position corresponding to A3-B3. It is a figure and a top view of a contact part. (A)-(g) is process sectional drawing which shows the manufacturing method of the element substrate used for the liquid crystal device shown in FIG. (A), (b), (c) is a plan view of one pixel of the liquid crystal device according to Embodiment 4 of the present invention, and a cross section when the liquid crystal device is cut at a position corresponding to A4-B4. It is a figure and a top view of a contact part. (A)-(g) is process sectional drawing which shows the manufacturing method of the element substrate used for the liquid crystal device shown in FIG. (A), (b), (c) is a plan view of one pixel of the liquid crystal device according to Embodiment 5 of the present invention, and a cross section when the liquid crystal device is cut at a position corresponding to A5-B5. It is a figure and a top view of a contact part. (A), (b), (c) is a plan view of one pixel of the liquid crystal device according to Embodiment 6 of the present invention, and a cross section when the liquid crystal device is cut at a position corresponding to A6-B6. It is a figure and a top view of a contact part. (A)-(e) is process sectional drawing which shows the manufacturing method of the element substrate used for the liquid crystal device shown in FIG. (A), (b), (c) is a plan view of one pixel of the liquid crystal device according to Embodiment 7 of the present invention, and a cross section when the liquid crystal device is cut at a position corresponding to A7-B7. It is a figure and a top view of a contact part. It is explanatory drawing at the time of using the liquid crystal device which concerns on this invention as a display apparatus of various electronic devices. (A), (b), (c) is a plan view of one pixel of a conventional liquid crystal device, a cross-sectional view when the liquid crystal device is cut at a position corresponding to A11-B11, and a plane of a contact portion, respectively. FIG.

Explanation of symbols

1. Liquid crystal device (electro-optical device), 1b, pixel, 1c, thin film transistor, 1e,.
Pixel area, 1f ... Liquid crystal, 1g ... Liquid crystal capacity, 1h ... Holding capacity, 1s ... Contact part, 2a ... Pixel electrode, 3a ... Gate line (gate electrode / scanning line), 3b ... Capacitor line 3c
..Lower electrode of storage capacitor, 3s..Lower side conductive layer, 4 .... Gate insulating layer, 4a..Lower side gate insulating layer, 4b..Upper side gate insulating layer, 4c..First thin film portion, 4d ··· Second thin film portion, 5a, 6c, 6d · · Upper electrode of storage capacitor, 6a · · Source line (data line), 6b
..Drain electrode, 6 s ..Upper conductive layer, 41, 43 ..Opening, 42, 44 ..Recess,
46 .. Lower hole of contact hole for connecting lower conductive layer, 81 ..Contact hole for connecting pixel electrode, 86 ..Contact hole for connecting upper conductive layer, 87 ..Contact hole for connecting lower conductive layer Upper hole, 89 ... Contact hole for connecting lower conductive layer

Claims (11)

A storage capacitor having a thin film transistor, a pixel electrode electrically connected to the thin film transistor, and a lower electrode and an upper electrode facing each other with a gate insulating layer of the thin film transistor interposed in each of a plurality of pixel regions on the element substrate And, in the element substrate, via a contact hole for connecting the lower conductive layer that penetrates the gate insulating layer and the interlayer insulating film with respect to the lower conductive layer formed on the lower layer side of the gate insulating layer. In the method of manufacturing an electro-optical device in which electrical connection is performed,
A gate electrode forming step of forming the gate electrode of the thin film transistor, the lower electrode, and the lower conductive layer;
A gate insulating layer forming step of forming the gate insulating layer;
A semiconductor layer forming step of forming a semiconductor layer of the thin film transistor;
A source / drain electrode forming step of forming a source electrode and a drain electrode of the thin film transistor;
An interlayer insulating film forming step for forming the interlayer insulating film;
A contact hole forming step of etching the interlayer insulating film to form a contact hole for connecting a pixel electrode and a contact hole for connecting the lower conductive layer;
A pixel electrode forming step of forming the pixel electrode,
Furthermore, it has a thinning process for reducing the film thickness by etching the gate insulating layer in the region where the upper electrode and the lower electrode overlap and the region where the contact hole for connecting the lower conductive layer is to be formed. A method of manufacturing an electro-optical device. In the gate insulating layer forming step, a lower gate insulating layer forming step of forming a lower insulating layer composed of one or more insulating films constituting a lower layer side portion of the gate insulating layer; Performing an upper gate insulating layer forming step of forming an upper gate insulating layer composed of one or more insulating films constituting the upper layer portion;
2. The method of manufacturing an electro-optical device according to claim 1, wherein the thinning step is performed after the lower layer side gate insulating layer forming step and before the upper layer side gate insulating layer forming step. 3. The electro-optic according to claim 2, wherein after the upper-layer side gate insulating layer forming step is performed in a vacuum atmosphere, the element substrate is kept in the vacuum atmosphere until the semiconductor layer forming step is started. Device manufacturing method. 4. In the contact hole forming step, etching is continuously performed until the contact hole for connecting the lower conductive layer reaches the lower conductive layer.
The method of manufacturing an electro-optical device according to any one of the above. The dry etching is performed in the contact hole forming step.
The method for manufacturing an electro-optical device according to any one of claims 1 to 4. 6. The pixel electrode forming step, wherein a conductive pattern electrically connected to the lower conductive layer via the lower conductive layer connection contact hole is formed simultaneously with the pixel electrode. The method of manufacturing an electro-optical device according to any one of the above. In the source / drain electrode formation step, an upper conductive layer is formed simultaneously with the source electrode and the drain electrode,
In the contact hole forming step, an upper conductive layer connecting contact hole that penetrates the interlayer insulating film and reaches the upper conductive layer is formed.
7. The electricity according to claim 6, wherein, in the pixel electrode forming step, the conductive pattern is formed so as to be electrically connected to the upper conductive layer via the upper conductive layer connection contact hole. Manufacturing method of optical device. A bonding step of bonding the surface on which the conductive layer of the counter substrate is formed to the element substrate;
In the bonding step, a conductive material is interposed between the element substrate and the counter substrate,
6. The electro-optical device according to claim 1, wherein the lower conductive layer and the conductive layer of the counter substrate are electrically connected in the lower conductive layer connection contact hole. Device manufacturing method. A thin film transistor having a structure in which a gate electrode, a gate insulating layer and a semiconductor layer are formed in order from the lower layer side in each of a plurality of pixel regions on the element substrate, and a pixel electrode connection formed on an interlayer insulating film covering the thin film transistor While having a pixel electrode electrically connected to the drain region of the thin film transistor through a contact hole and a storage capacitor having a lower electrode and an upper electrode facing each other with the gate insulating layer interposed therebetween, Electrical connection is made to a lower conductive layer formed on the lower layer side of the gate insulating layer through a lower conductive layer connecting contact hole that penetrates the gate insulating layer and the interlayer insulating film. In an electro-optical device,
The gate insulating layer is thinner than the region overlapping the lower electrode and the upper electrode, and the region overlapping the gate electrode and the semiconductor layer in the region where the contact hole for connecting the lower conductive layer is formed. Each comprising a first thin film portion and a second thin film portion;
The lower-layer-side conductive layer connection contact hole includes a lower hole that penetrates the second thin film portion and an upper hole that penetrates the interlayer insulating film. The gate insulating layer includes a lower gate insulating layer made of one or more insulating films and an upper gate insulating layer made of one or more insulating films,
10. The electro-optical device according to claim 9, wherein the first thin film portion and the second thin film portion are configured by a removed portion of the lower gate insulating layer.   An electronic apparatus comprising the electro-optical device according to claim 9.

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