JP2005141251A - Array substrate for display apparatus and method for manufacturing array substrate - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an array substrate for a display apparatus on which a scanning line and a pixel electrode are overlapped to form an auxiliary capacitance without decreasing the production yield and a higher aperture ratio can be obtained. <P>SOLUTION: The substrate is equipped with: a scanning line (111); a thin film transistor (112) including a first insulating film (115), (117) on the scanning line, a semiconductor film (120) thereon, and a source electrode (126b) and a drain electrode (126a) electrically connected to the semiconductor (120); a signal line (110) lead from the drain electrode (126a) and almost orthogonally intersecting with the scanning line (111); and a pixel electrode (131) electrically connected to the source electrode (126b). The pixel electrode (131) is electrically connected to the source electrode (126b) via a second insulating film (127) disposed on at least the signal line (110). The pixel electrode (131) overlaps with an extended region (113) of the adjacent line (111) via the first and second insulating films (115), (117), (127). <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to an array substrate for a display device used in a flat display device such as a liquid crystal display device and a method for manufacturing the same.

  2. Description of the Related Art In recent years, flat-type display devices that replace CRT displays have been actively developed, and liquid crystal display devices are particularly attracting attention because of their advantages such as light weight, thinness, and low power consumption.

  For example, a light transmission type active matrix liquid crystal display device in which a switch element is arranged for each display pixel will be described as an example. An active matrix type liquid crystal display device is formed by holding a liquid crystal layer between an array substrate and a counter substrate via an alignment film. The array substrate has a plurality of signal lines and scanning lines arranged in a lattice pattern on a transparent insulating substrate such as glass or quartz, and amorphous silicon (hereinafter abbreviated as a-Si: H) or the like at each intersection. A thin film transistor (hereinafter abbreviated as TFT) using the semiconductor thin film is connected. The gate electrode of the TFT is electrically connected to the scanning line, the drain electrode is electrically connected to the signal line, and the source electrode is electrically connected to a transparent conductive material constituting the pixel electrode, for example, ITO (Indium-Tin-Oxide). Has been.

The counter substrate includes a counter electrode made of ITO on a transparent insulating substrate such as glass, and a color filter layer if a color display is realized.
No. 1-334392 U.S. Pat. No. 4,612,260 JP-A-6-202153 JP-A-6-208137 US Pat. No. 5,483082

  In the liquid crystal display device described above, the potential of the pixel electrode fluctuates due to the parasitic capacitance of the TFT or the leakage current generated between the pixel electrode and the counter electrode. It is known that an auxiliary capacitor (Cs) parallel to the pixel capacitor (CLc) is provided by arranging a capacitor line, thereby suppressing fluctuations in the pixel potential.

  However, this auxiliary capacity line is often made of a light-impermeable material that is the same material as the scanning line material in order to prevent an increase in the number of manufacturing steps, and therefore the area where the auxiliary capacity line is disposed is not light-impermeable. It becomes permeation | transmission and will reduce an aperture ratio.

  For this reason, an auxiliary capacitor is formed between the pixel electrode and a scanning line adjacent to the pixel electrode, and a high opening is achieved while suppressing fluctuations in the pixel potential by devising a scanning pulse applied to the scanning line. It is known to maintain the rate (see, for example, Patent Document 1 and Patent Document 2).

  However, with such a configuration, an interlayer short circuit is likely to occur at the overlapping portion between the scanning line and the pixel electrode, resulting in a decrease in manufacturing yield.

  In addition, according to such a configuration, by devising the shape of the scanning line so as to overlap the peripheral region of the pixel electrode, the pixel region contributing to the display of the pixel electrode can be clearly defined. The auxiliary capacitance (Cs) formed by the overlapping portion with the line increases beyond the capacitance value necessary for suppressing fluctuations in the pixel potential. Therefore, the scanning pulse is delayed, writing to the pixel electrode is insufficient, and the contrast ratio is lowered. Although it is conceivable to increase the scanning line width in order to suppress the delay of the scanning pulse, in this case, the aperture ratio is reduced.

  The present invention has been made in response to the above technical problem, and relates to an array substrate for a display device in which a scanning line and a pixel electrode are overlapped to form an auxiliary capacitor, and has an excellent manufacturing yield and a high aperture ratio. An object of the present invention is to provide an array substrate for a display device and a method for manufacturing the same.

  It is another object of the present invention to provide an array substrate for a display device and a method for manufacturing the same that can ensure high productivity with a small number of masks and without reducing the manufacturing yield.

  On the other hand, an array substrate for a display device and a method for manufacturing the same that can ensure high productivity with a small number of masks without reducing the manufacturing yield have been proposed (for example, Patent Document 3, Patent Document 4, and Patent Document 5). reference). This array substrate has the following structure.

  The gate terminal portion is stacked on the gate terminal lower electrode through contact holes opened in the gate terminal lower electrode and the insulating film and passivation film forming a common layer with the gate insulating film on the gate terminal, and the same material as the pixel electrode The auxiliary capacitor portion is composed of a Cs electrode, a dielectric film composed of an insulating film and an i-type semiconductor layer thereon, and an n + type semiconductor layer and a metal layer thereon. And a counter electrode.

  However, the array substrate having this structure has a problem that it is difficult to apply a voltage to the auxiliary capacitance portion at the same potential.

  Therefore, in view of the above problems, the present invention provides an array substrate having a structure that can be easily applied to each auxiliary capacitance unit at the same potential.

According to a first aspect of the present invention, there are provided a plurality of scanning lines disposed on a substrate and including a gate electrode region, an auxiliary capacitance line substantially parallel to the scanning lines, a first insulating film disposed thereon, and at least the gate A thin film transistor including a semiconductor film disposed on the electrode region, a source electrode and a drain electrode electrically connected to the semiconductor film, a second insulating film disposed on the thin film transistor, and the drain electrode In the array substrate for a display device, which includes a signal line that is connected to the scanning line and substantially orthogonal to the scanning line, and a pixel electrode that is electrically connected to the source electrode, the auxiliary capacitor is interposed through the first insulating film. The conductive layer includes a first contact hole that exposes the storage capacitor line, and is spaced apart from the first contact hole in a plane. The laminated arranged between the bundled second contact hole to expose the wiring, thereby said storage capacitance line said the bundled wire is a display device for an array substrate, characterized in that it is electrically connected.

  The invention according to claim 2 is the array substrate for a display device according to claim 1, wherein the bundle wiring is made of the same material as the signal line, and the conductive layer is made of the same material as the pixel electrode. .

  According to a third aspect of the present invention, a low-resistance semiconductor film is interposed between the semiconductor film and the source electrode and the drain electrode, and the low-resistance semiconductor film is interposed between the signal line and the semiconductor layer in the intersection region. 2. The array substrate for a display device according to claim 1, wherein a low resistance semiconductor layer made of the same material as that of the resistance semiconductor film is interposed.

  The invention according to claim 4 is the array substrate for display device according to claim 1, wherein the semiconductor film is mainly composed of amorphous silicon.

  According to a fifth aspect of the present invention, a plurality of scanning lines including a gate electrode region disposed on a substrate, an auxiliary capacitance line substantially parallel to the scanning line, a gate insulating film disposed thereon, and at least the gate electrode A thin film transistor including a semiconductor film disposed on the region, a source electrode and a drain electrode electrically connected to the semiconductor film, an interlayer insulating film disposed on the thin film transistor, and electrically connected to the drain electrode And a display device array substrate comprising a signal line that is substantially orthogonal to the scanning line and a pixel electrode that is electrically connected to the source electrode, and is substantially the same as the auxiliary capacitance line through the gate insulating film. The conductive layer includes a first contact hole that exposes the storage capacitor line, and is spaced apart in plan from the first contact hole. Is the laminated arranged between the bundled second contact hole to expose the wiring, thereby said storage capacitance line said the bundled wire is a display device for an array substrate, characterized in that it is electrically connected.

  The invention according to claim 6 is the array substrate for a display device according to claim 5, wherein the bundle wiring is made of the same material as the signal line, and the conductive layer is made of the same material as the pixel electrode. .

  According to a seventh aspect of the present invention, a plurality of scanning lines including a gate electrode region disposed on a substrate, an auxiliary capacitance line substantially parallel to the scanning lines, a first insulating film disposed thereon, and at least the gate A thin film transistor including a semiconductor film disposed on the electrode region, a source electrode and a drain electrode electrically connected to the semiconductor film, a second insulating film disposed on the thin film transistor, and the drain electrode In a liquid crystal display device having an array substrate including a signal line that is connected to the scanning line and substantially orthogonal to the scanning line, and a pixel electrode that is electrically connected to the source electrode, the liquid crystal display device has a first insulating film interposed therebetween. The conductive layer includes a bundle wiring that is wired in a direction substantially orthogonal to the storage capacitor line, and the conductive layer is spaced apart in plan from the first contact hole that exposes the storage capacitor line. Are stacked between the second contact hole exposing the bundled wires provided Te, thereby said storage capacitance line said the bundled wire is a liquid crystal display device, characterized in that it is electrically connected.

  The invention according to claim 8 is the liquid crystal display device according to claim 7, wherein the bundled wiring is made of the same material as the signal line, and the conductive layer is made of the same material as the pixel electrode.

  According to a ninth aspect of the present invention, a low-resistance semiconductor film is interposed between the semiconductor film and the source and drain electrodes, and the low-resistance semiconductor film is interposed between the signal line and the semiconductor layer in the intersection region. 8. The liquid crystal display device according to claim 7, wherein a low-resistance semiconductor layer made of the same material as that of the resistance semiconductor film is interposed.

  The invention according to claim 10 is the liquid crystal display device according to claim 7, wherein the semiconductor film is mainly composed of amorphous silicon.

  According to an eleventh aspect of the present invention, there is provided a plurality of scanning lines including a gate electrode region disposed on a substrate, an auxiliary capacitance line substantially parallel to the scanning lines, a gate insulating film disposed thereon, and at least the gate electrode A thin film transistor including a semiconductor film disposed on the region, a source electrode and a drain electrode electrically connected to the semiconductor film, an interlayer insulating film disposed on the thin film transistor, and electrically connected to the drain electrode In addition, in the liquid crystal display device having an array substrate having a signal line substantially orthogonal to the scanning line and a pixel electrode electrically connected to the source electrode, the auxiliary capacitor is interposed via the gate insulating film. The conductive layer includes a first contact hole that exposes the storage capacitor line, and is planar with the first contact hole. A liquid crystal display device, wherein the auxiliary capacitor line and the bundled wiring are electrically connected to each other by being stacked between the second contact holes that are spaced apart and expose the bundled wiring. is there.

  The invention according to claim 12 is the liquid crystal display device according to claim 11, wherein the bundled wiring is made of the same material as the signal line, and the conductive layer is made of the same material as the pixel electrode.

  As described above in detail, according to the array substrate for a display device and the manufacturing method thereof of the present invention, the auxiliary capacitance can be formed by overlapping the scanning line and the pixel electrode without lowering the manufacturing yield. A high aperture ratio can be achieved.

  Moreover, according to the present invention, high productivity can be ensured with a small number of masks without reducing the manufacturing yield.

  Furthermore, according to the array substrate for a display device of the present invention, the scanning line lead portion and the signal line lead portion are not easily disconnected.

[First embodiment]
Hereinafter, a liquid crystal display device (1) according to a first embodiment of the present invention will be described with reference to FIGS.

  This liquid crystal display device (1) is a light transmission type capable of color display, and is composed of a polyimide resin between an array substrate (100) and a counter substrate (200) as shown in FIG. The twisted nematic (TN) liquid crystal is held through the alignment films (141) and (241) that have been subjected to alignment treatment in the direction of the direction. Further, polarizing plates (311) and (313) are attached to the outer surfaces of the array substrate (100) and the counter substrate (200), respectively.

  FIG. 1 shows a schematic plan view of an array substrate (100), with the lower side in the figure being located on the upper side of the screen of the liquid crystal display device (1), from the lower side to the upper side in the figure. Scan lines are sequentially selected.

  The array substrate (100) includes 480 Al-Y alloy scanning lines (111) arranged on the glass substrate (101), and one end of each scanning line (111) is connected to the glass substrate (101). It is drawn out to the one end side (101a) side, and is electrically connected to the scanning line pad (152) through the oblique wiring portion (150). Here, the scanning line (111) is made of an Al—Y alloy, but it may be made of a Mo—Ta alloy, a Mo—W alloy, Al, or an alloy thereof.

The array substrate (100) includes, on the glass substrate (101), signal lines (110) made of 1920 Mo-W alloys substantially orthogonal to the scanning lines (111). Each signal line (110) is a glass substrate (110). 101) is pulled out to the other end side (101b) side, and is electrically connected to the signal line pad (162) through the oblique wiring portion (160). Here, the signal line (110) is made of a Mo—W alloy, but may be made of a Mo—Ta alloy, Al, or an alloy thereof.

  A TFT (112) is arranged in the vicinity of the intersection of the scanning line (111) and the signal line (110). A pixel electrode (131) made of ITO connected to the TFT (112) is disposed on the scanning line (111) and the signal line (110) via an interlayer insulating film (127). The interlayer insulating film (127) can be composed of an inorganic insulating film such as a silicon nitride film or a silicon oxide film or an organic resin film such as an acrylic film. A multilayer film of these inorganic insulating film and organic resin film is used. By comprising, surface smoothness and interlayer insulation are further improved.

(TFT area structure)
The structure of the TFT (112) region will be described.

  Each scanning line (111) has an extended region (113) that extends in a thin line so as to overlap with the edges (131a) and (131b) along the signal line (110) of the adjacent pixel electrode (131). including. The overlapping area (OS) of the pixel electrode (131) and the extending area (113) from the preceding scanning line (111) with respect to the scanning line (111) corresponding to the pixel electrode (131) is shown in FIG. As shown, the first gate insulating film 115, the second gate insulating film 117, and the interlayer insulating film 127 are overlapped with each other, and this overlapping region (OS) forms an auxiliary capacitance (Cs). The Further, in this embodiment, the pixel electrode (131) is connected to the preceding scanning line (111) itself via the first gate insulating film (115), the second gate insulating film (117) and the interlayer insulating film (127). The storage capacitor (Cs) is also formed in this overlapping region.

  A counter substrate (200) facing the array substrate (100) is disposed on the glass substrate (201), and includes a TFT (121) region, a signal line (110), a scanning line (111), a pixel electrode (131), A matrix-like resinous light-shielding film (211) that shields the gap between the two. Further, red (R), green (G) and blue (B) color filters (221) are arranged in regions corresponding to the pixel electrodes (131), respectively, on which counter electrodes (made of a transparent electrode material ( 231) is arranged.

  As described above, according to the array substrate (100) of the liquid crystal display device (1), the interlayer insulating film (127) is interposed between the signal line (110) and the scanning line (111) and the pixel electrode (131). ), Or the first and second gate insulating films (115), (117) and the interlayer insulating film (127) are disposed, so that the pixel electrode (131) is connected to each wiring (110), (111). Can be arranged sufficiently close to each other or overlapped with each other, so that a high aperture ratio can be realized.

  Further, according to this embodiment, the auxiliary capacitor (Cs) is provided between the pixel electrode (131) and the extension region (113) extending from the pixel electrode (131) and the adjacent scanning line (111). Therefore, it is not necessary to separately arrange an auxiliary capacitance line or the like, and a higher aperture ratio can be achieved. In particular, in this embodiment, since the TFT (112) is configured with a region derived from the scanning line (111) along the signal line (110) as a gate electrode, the pixel electrode (131) is formed in the preceding scanning line. (111) can be superimposed on itself. Thereby, securing of sufficient auxiliary capacity (Cs) and high aperture ratio can be achieved at the same time.

  Since three types of insulating films (115), (117), and (127) are stacked between the pixel electrode (131), the scanning line (111), and the extended region (113), respectively. Further, the occurrence of an interlayer short circuit or the like due to the structure of this embodiment is also greatly reduced.

  By the way, in this embodiment, the pixel region is defined not by the light shielding film (211) disposed on the counter substrate (200) but by the scanning line (111) on the array substrate (100) and its extension region (113). The Therefore, the first mask pattern for patterning the scanning line (111) and the fifth mask pattern for patterning the pixel electrode (131), regardless of the alignment accuracy between the array substrate (100) and the counter substrate (200). Since it is determined only by the alignment accuracy, it is not necessary to provide a margin for the width of the light-shielding film (211) in consideration of misalignment between the array substrate (100) and the counter substrate (200). Realization is possible.

  Further, in order to define the pixel region, the extension region (113) of the scanning line (111) extends sufficiently along the edges (131a) and (131b) along the signal line (110) of the pixel electrode (131). However, according to this embodiment, the first gate insulating film (115) and the second gate insulating film (117) are provided between the pixel electrode (131) and the extension region (113) of the scanning line (111). In addition, since the interlayer insulating film (127) is disposed, a large increase in the auxiliary capacitance (Cs) can be suppressed without impairing the productivity.

  Further, as shown in FIG. 5, the contour of the signal line (110) coincides with the contours of the low-resistance semiconductor film (124a) and the semiconductor film (120). More specifically, in addition to the first and second gate insulating films (115) and (117), the low resistance semiconductor film (124a) and the semiconductor are always provided at the intersection of the signal line (110) and the scanning line (111). A film (120) is laminated. For this reason, even if mask misalignment occurs during each patterning, there is no capacitance fluctuation between the signal line (110) and the scanning line (111), and this reduces fluctuations in scanning line capacitance or signal line capacitance between products. The Also, interlayer short-circuits caused by static electricity at the intersection of the signal line (110) and the scanning line (111), dust in the process, or pinholes of the insulating films (115) and (117) can be suppressed. A higher production yield can be secured.

  Further, as shown in FIG. 6, since the contour of the signal line (110) and the contours of the low-resistance semiconductor film (124a) and the semiconductor film (120) coincide with each other, patterning is performed in a separate process as in the prior art. On the other hand, even if a mask shift occurs during each patterning, the capacitance fluctuation generated between the signal line (110) and the extension region (113) of the scanning line (111) can be sufficiently suppressed.

  Further, the signal line (110) and the extension region (113) of the scanning line (111) are overlapped, that is, the extension region (113) arranged adjacently via the signal line (111) in FIG. In addition to the insulating films (115) and (117), a semiconductor is connected between the signal line (110) and the extension region (113) of the scanning line (111). Since the film (120) is always arranged, it is possible to suppress inter-layer shorts caused by static electricity, dust in the process, or pinholes of the insulating films (115) and (117), thereby ensuring a high manufacturing yield. . Thus, the configuration in which the extending region (113) is arranged under the pixel electrode (131) adjacent to the signal line (111), capacitive coupling between the signal line (111) and the pixel electrode (131) is achieved. It is shielded by the extended region (113), and the influence of the potential of the pixel electrode (131) on the potential of the signal line (111) can be reduced. Moreover, the contour lines of the semiconductor film (120) and the low resistance semiconductor film (124a) disposed between the signal line (111) and the insulating films (115) and (117) are the same as the contour line of the signal line (111). Match. For these reasons, the signal line (111) and the pixel electrode (131) can be disposed sufficiently close to each other, thereby achieving a higher aperture ratio.

(Structure near the outer periphery of the scanning line)
The structure near the outer periphery of the scanning line (111) will be described with reference to FIGS.

  A scanning line (111) made of an Al-Y alloy is drawn out to one end side (101a) side of the glass substrate (101) and is led to the oblique wiring part (150) and the scanning line pad (152). ) Is formed.

  In the oblique wiring section (150), two layers of insulating films (115) and (117) are stacked on the lower wiring section (111a) extending from the scanning line (111). Further, on the two insulating films (115) and (117), Mo-W which is the same material in the same process as the semiconductor film (119), the low resistance semiconductor film (123) and the signal line (110). An upper wiring portion (125a) made of an alloy film is laminated, and an interlayer insulating film (127) is disposed on the upper wiring portion (125a).

  At the base of the oblique wiring portion (150), a pair of first contact hole (153) and second contact hole (154) are arranged close to each other in the wiring direction, and the pixel electrode (131 ) And the lower layer wiring part (111a) and the upper layer wiring part (125a) extended from the scanning line (111) by the scanning line connection layer (131) made of ITO which is the same material in the same process as the first contact hole ( 153) and the second contact hole (154). The second contact hole (154) has two layers of insulating films (115), (117), a semiconductor film (119), a low resistance semiconductor so as to expose a part of the main surface of the lower wiring part (111a). The interlayer insulating film (127) is an opening that penetrates the coating (123) and the upper wiring portion (125a), and the first contact hole (153) exposes a part of the main surface of the upper wiring portion (125a). It is an opening which penetrates.

  Further, in the scanning line pad (152), a pair of first contact holes (155) and second contact holes (156) are also arranged close to each other in the wiring direction, and the pixel electrodes (131) and 131 The lower wiring part (111a) and the upper wiring part (125a) of the scanning line (111) are connected to the first contact hole (155) and the second contact by the scanning line connection layer (131) made of ITO of the same material in the same process. It is electrically connected through a hole (156). The second contact hole (156), like the above-described second contact hole (154), has two layers of insulating films (115), 115 so as to expose a part of the main surface of the lower wiring part (111a). (117), an opening penetrating the semiconductor coating (119), the low-resistance semiconductor coating (123), and the upper wiring portion (125a), and the first contact hole (155) is the first contact hole (153) and Similarly, the opening penetrates the interlayer insulating film (127) so as to expose a part of the main surface of the upper wiring part (125a).

  As a result, the oblique wiring portion (150) of the scanning line (111) is formed of the upper layer wiring portion (Mo-W alloy film made of the same material and in the same process as the signal line (110) patterned in a different process). 125a) and a lower layer wiring portion (111a) extending from the scanning line (111) made of an Al—Y alloy film, and the two layers make the base of the oblique wiring portion (150) and the scanning line pad. (152) are electrically connected.

  For this reason, in the diagonal wiring part (150), even if one of the upper layer wiring part (125a) or the lower layer wiring part (111a) is disconnected, the other is connected. Is greatly reduced.

  Further, since the oblique wiring part (150) includes the lower wiring part (111a) made of an Al—Y alloy film, which is a low resistance material mainly composed of Al, a sufficiently low resistance can be achieved.

  In this embodiment, the region of the second contact hole (156), that is, the stacked region of the lower wiring portion (111a) and the scanning line connection layer (131) mainly functions as the connection region of the scanning line pad (152). .

(Structure around the outer periphery of the signal line)
The structure near the outer periphery of the signal line (110) will be described with reference to FIGS.

  The lower wiring part (111b) made of an Al-Y alloy film made of the same material in the same process as the scanning line (111) is connected to one end side (101b) side of the glass substrate (101) corresponding to each signal line (110). The signal line (110) is disposed on the diagonal wiring portion (160) and the signal line pad (162).

  In the oblique wiring section (160), two layers of insulating films (115) and (117) are disposed on the lower wiring section (111b). Further, a Mo-W alloy film extending from the semiconductor film (119), the low resistance semiconductor film (123) and the signal line (110) is formed on the two insulating films (115) and (117). An upper layer wiring portion (125b) (signal line (110)) is laminated, and an interlayer insulating film (127) is disposed on the upper layer wiring portion (125b).

  In the base portion of the oblique wiring portion (160), a pair of first contact hole (163) and second contact hole (164) are arranged close to each other in the wiring direction, and the pixel electrode (131 The upper layer wiring part (125b) and the lower layer wiring part (111b) extending from the signal line (110) are electrically connected by the signal line connection layer (131) made of ITO which is the same material in the same process. ing. The second contact hole (164) has two layers of insulating films (115), (117), a semiconductor film (119), a low resistance semiconductor so as to expose a part of the main surface of the lower wiring part (111b). The interlayer insulating film (127) is an opening that penetrates the coating (123) and the upper wiring portion (125b), and the first contact hole (163) exposes a part of the main surface of the upper wiring portion (125b). It is an opening which penetrates.

  In the signal line pad (162), a pair of first contact hole (165) and second contact hole (166) are arranged close to each other in the wiring direction, and the same process as the pixel electrode (131). The upper wiring portion (125b) and the lower wiring portion (111b) extending from the signal line (110) are electrically connected by the signal line connection layer (131) made of ITO, which is the same material. The second contact hole (166), like the above-described second contact hole (164), has two layers of insulating films (115), 115 so as to expose a part of the main surface of the lower wiring part (111b). (117), an opening penetrating the semiconductor coating (119), the low-resistance semiconductor coating (123), and the upper wiring portion (125b), wherein the first contact hole (165) is the same as the second contact hole (163) described above. Similarly, the opening penetrates the interlayer insulating film (127) so as to expose a part of the main surface of the upper wiring part (125b).

  As a result, in the oblique wiring portion (160), the upper layer wiring portion (125b) extending from the signal line (110) made of the Mo—W alloy film and the scanning line (111) are made of the same material in the same process. A lower wiring portion (111b) made of -Y alloy film is laminated and the base of the oblique wiring portion (160) and the signal line pad (162) are electrically connected by these two layers.

  Therefore, even if one of the upper wiring part (125b) made of Mo-W alloy film or the lower wiring part (111b) made of Al-Y alloy film is disconnected in the oblique wiring part (160), the other is connected. Therefore, the occurrence of disconnection failure in the oblique wiring portion (160) is reduced.

  Further, since the oblique wiring portion (160) includes the lower wiring portion (111b) made of an Al—Y alloy film, which is a low resistance material mainly composed of Al, the resistance can be sufficiently lowered.

  In this embodiment, the region of the second contact hole (166), that is, the stacked region of the lower wiring part (111b) and the scanning line connection layer (131) mainly functions as the connection region of the signal line pad (162). .

  According to the above-described configuration, the bumps of the driving IC, the electrodes of the FPC (flexible printed circuit), the TCP (tape carrier package), etc. are connected to the signal line pad (162) and the scanning line pad (152) with an ACF (differential). Signal line pad (162) and scanning line pad (152) have substantially the same configuration when electrically connected via a connection layer such as an anisotropic conductive film). Even if the connection conditions of the scanning line pads (152) are made equal, the heat, pressure, etc. applied to the connection layer can be made substantially equal, which makes it possible to manufacture under the same conditions. That is, in this embodiment, the connection region of the scanning line pad (152) is made of the same material as the lower wiring part (111a) and the pixel electrode (131) made of an Al—Y alloy film mainly derived from the scanning line (111). The connection region of the signal line connection pad (162) is mainly composed of an Al-Y alloy film formed simultaneously with the scan line (111). The lower layer wiring portion (111b) and the pixel electrode (131) have a laminated structure of a signal line connection layer (131) made of ITO which is the same material, and the structure is substantially the same.

(Array substrate manufacturing process)
Next, the manufacturing process of the array substrate (100) will be described in detail with reference to FIGS.

(1) First Step As shown in FIG. 7, an Al—Y alloy film and a Mo film are continuously deposited on a glass substrate (101) by sputtering to a thickness of 200 nm and 30 nm, respectively, and a first mask pattern is formed. It is exposed and used, followed by development and patterning (first patterning).

  As a result, 480 scanning lines (111) are formed on the glass substrate (101), and at one end (101a) side, the oblique wiring portion (150) of the scanning line (111) and the scanning line pad (152) are formed. The lower wiring part (111a) constituting the signal line, the oblique wiring part (160) of the signal line (110) and the lower wiring part (111b) constituting the signal line pad (162) at the one end side (101b) are prepared simultaneously.

  Further, in the TFT region, a gate electrode that is integrated with the scanning line (111) and led out in a direction orthogonal to the scanning line (111) is manufactured. Further, an extension region (113) for forming an auxiliary capacitor (Cs) derived in a direction orthogonal to the scanning line (111) at the time of patterning of the scanning line (111) is also prepared at the same time (FIG. 1). reference).

(2) Second Step After the first step, as shown in FIG. 8, after depositing a first gate insulating film (115) made of a silicon oxide film having a thickness of 150 nm by plasma CVD, silicon nitride having a thickness of 150 nm is further deposited. A second gate insulating film (117) made of a film, a semiconductor film (119) made of a-Si: H having a thickness of 50 nm, and a channel protective film (121) made of a silicon nitride film having a thickness of 200 nm are continuously exposed to the atmosphere. Without film formation.

(3) Third Step After the second step, as shown in FIG. 9, the channel protective film (121) is patterned in a self-aligned manner on the scanning line (111) by the backside exposure technique using the scanning line (111) as a mask. Further, exposure is performed using a second mask pattern so as to correspond to the TFT region, and development and patterning (second patterning) are performed to form an island-shaped channel protective film (122).

(4) Fourth Step After the third step, as shown in FIG. 10, the exposed semiconductor film (119) surface is treated with hydrofluoric acid (HF) solution so as to obtain a good ohmic contact, and plasma CVD is performed. A low resistance semiconductor film (123) made of n + a-Si: H having a thickness of 30 nm containing phosphorus as an impurity is deposited by the method, and a Mo-W alloy film (125) having a thickness of 300 nm is further deposited by sputtering.

(5) Fifth Step After the fourth step, as shown in FIG. 11, exposure and development are performed using a third mask pattern, and a Mo—W alloy film (125), a low-resistance semiconductor film (123), and a semiconductor The film (119) is plasma etched by controlling the etching selectivity between the first gate insulating film (115) or the second gate insulating film (117) made of a silicon nitride film and the channel protective film (122). (Third patterning).

  Thereby, in the TFT region, the resistance semiconductor film (124a) and the source electrode (126b) are integrally manufactured, and the drain electrode (126a) is manufactured integrally with the low resistance semiconductor film (124b) and the signal line (110). To do.

  At the base of the scanning line pad (152) and the oblique wiring part (150), the Mo-W alloy film (125) is patterned along the lower wiring part (111a) to form the upper wiring part (125a). Then, the low resistance semiconductor film (123) and the semiconductor film (119) are patterned in a lump along the upper wiring portion (125a). At the same time, the openings (154a), (156a) penetrating the upper wiring portion (125a), the low resistance semiconductor film (123), and the semiconductor film (119) corresponding to the second contact holes (154), (156) described above. ).

  Similarly, at the base of the signal line pad (162) and the diagonal wiring part (160), the Mo—W alloy film (125) is patterned along the lower wiring part (111b) to extend from the signal line (110). The existing upper layer wiring part (125b) is formed, and the low resistance semiconductor film (123) and the semiconductor film (119) are collectively patterned along the upper layer wiring part (125b). At the same time, the upper wiring portion (125b) in the region corresponding to the second contact holes (164), (166), the low resistance semiconductor film (123), and the opening (164a), penetrating the semiconductor film (119), (166a) is prepared.

  Here, the Mo—W alloy film (125), the low-resistance semiconductor film (123), and the semiconductor film (119) are patterned by dry etching, but wet etching may also be used.

(6) Sixth Step After the fifth step, an interlayer insulating film (127) made of a silicon nitride film having a thickness of 200 nm is deposited thereon.

  Then, as shown in FIG. 12, exposure and development are performed using the fourth mask pattern, and a part of the interlayer insulating film (127) corresponding to the source electrode (126b) is removed, and contact etching is performed by dry etching. (129a) is formed.

  At the base part of the scanning line pad (152) and the oblique wiring part (150), the interlayer insulating film (127) is bundled together with the first and second gate insulating films (117) corresponding to the openings (154a) and (156a). Forming second contact holes (154), (156) (fourth patterning) and removing the interlayer insulating film (127) in the vicinity of the second contact holes (154), (156) First contact holes (153) and (155) paired with second contact holes (154) and (156) are formed.

  At the same time, at the base of the signal line pad (162) and the oblique wiring part (160), the interlayer insulating film (127) is formed together with the first and second gate insulating films (117) corresponding to the openings (164a) and (166a). The second contact holes (164) and (166) are formed by removing all at once, and at the same time, the interlayer insulating film (127) in the vicinity of the second contact holes (164) and (166) is removed and the second contact hole ( 164) and (166) and first contact holes (163) and (165) which are paired with each other are formed.

(7) Seventh Step After the sixth step, as shown in FIG. 13, an ITO film having a thickness of 100 nm is deposited thereon by sputtering, and patterned by exposure, development, and dry etching using a fifth mask pattern ( Through the fifth patterning, a pixel electrode (131) is produced. The ITO film patterning may also be wet etching instead of dry etching.

  The first contact holes (153) and (155) and the second contact holes (154) and (156) are electrically connected to the bases of the scanning line pad (152) and the oblique wiring part (150), respectively. The scanning line connection layer (131) is formed, and the scanning line (111) and the scanning line pad (152) are formed as an oblique wiring having a two-layer structure of a lower layer wiring part (111a) and an upper layer wiring part (125a). It is electrically connected by the part (150).

  The first contact holes (163) and (165) and the second contact holes (164) and (166) are also electrically connected to each other at the bases of the signal line pad (162) and the oblique wiring part (160). The signal line connection layer (131) is formed at the same time so that the signal line (110) and the signal line connection pad (162) have a two-layer structure of a lower layer wiring part (111b) and an upper layer wiring part (125b). Electrical connection is made by the oblique wiring section (160).

(Effect of the first embodiment)
As described above, according to the array substrate of this embodiment, the array substrate can be manufactured by using five masks as the basic configuration. That is, the pixel electrode is arranged in the uppermost layer, and along with this, together with the signal line, source and drain electrodes, the semiconductor film and the like are patterned all together based on the same mask pattern, and for connecting the source electrode and the pixel electrode. By simultaneously forming the contact holes and the contact holes for exposing the connection ends of the signal lines and the scanning lines, the productivity can be improved with a small number of masks, and the manufacturing yield is not lowered.

  Each oblique wiring portion of the signal line and the scanning line is constituted by two layers of an upper wiring portion made of a Mo—W alloy film forming a signal line and a lower wiring portion made of an Al—Y alloy film forming a scanning line. In addition, the base of each oblique wiring portion and each pad are electrically connected. Therefore, even if one of the upper layer wiring portion or the lower layer wiring portion is disconnected in the oblique wiring portion, the other is connected, so that the oblique wiring portion is not disconnected.

  Furthermore, since the oblique wiring portion includes a wiring layer made of a low resistance material mainly composed of at least Al, a sufficiently low resistance can be achieved.

  Further, since the signal line pad and the scanning line pad for connecting electrodes such as bumps and TCP of the driving IC have substantially the same configuration, it is possible to connect them under the same conditions.

(Other changes)
In this embodiment, the case where the semiconductor film is made of a-Si: H has been described, but it goes without saying that it may be a polycrystalline silicon film or the like. Further, the drive circuit unit may be integrally formed in the peripheral region.

  Further, in the case where the pixel electrode is partially overlapped on the signal line or the scanning line, if the shield electrode is arranged with a metal film or the like through an insulating layer at least between the pixel electrode and the signal line, The influence of the pixel electrode due to the potential from the signal line can be reduced.

(Example of changing the structure near the outer periphery of signal lines and scanning lines)
As shown in FIG. 14, an example of changing the structure near the outer periphery of the signal line (110) will be described.

  The lower wiring part (111b) made of an Al-Y alloy film made of the same material in the same process as the scanning line (111) is connected to one end side (101b) side of the glass substrate (101) corresponding to each signal line (110). The signal line (110) is disposed on the diagonal wiring portion (160) and the signal line pad (162).

  In the oblique wiring section (160), two layers of insulating films (115) and (117) are disposed on the lower wiring section (111b). Further, a Mo-W alloy film extending from the semiconductor film (119), the low resistance semiconductor film (123) and the signal line (110) is formed on the two insulating films (115) and (117). An upper layer wiring portion (125b) (signal line (110)) is laminated, and an interlayer insulating film (127) is disposed on the upper layer wiring portion (125b).

  The base portion of the diagonal wiring portion (160) is the same as that of the above-described embodiment. In the signal line pad (162), a pair of first contact holes (175) and second contact holes (176) and Are arranged in an upper layer wiring part (125b) and a lower layer wiring part (125b) extended from the signal line (110) by the signal line connection layer (131) made of ITO which is the same material in the same process as the pixel electrode (131). 111b) is electrically connected. The first contact hole (175) has two layers of insulating films (115), (117), a semiconductor film (119), a low resistance semiconductor so as to expose a part of the main surface of the lower wiring part (111b). The interlayer insulating film (127) is an opening that penetrates the coating (123) and the upper wiring portion (125b), and the second contact hole (176) exposes a part of the main surface of the upper wiring portion (125b). It is an opening which penetrates.

  Thus, in this modified example, the signal line pad (162) is mainly composed of the lower wiring part (111b), the two insulating films (115) and (117), and the two insulating layers. A semiconductor film (119) disposed on the films (115), (117), a low resistance semiconductor film (123), and an upper wiring portion (125b) made of a Mo-W alloy film extending from the signal line (110). ) (Signal line (110)) and the signal line connection layer (131) made of ITO constituting the pixel electrode (131) are the same as in the above-described embodiment, except that the structure is a laminated structure. is there.

  It should be noted that the structure in the vicinity of the outer periphery of the scanning line (111) is preferably the same as that on the signal line side.

[Second Embodiment]
A light transmission type liquid crystal display device (1) according to a second embodiment of the present invention will be described below with reference to FIGS.

  As shown in FIG. 16, the liquid crystal display device (1) is composed of a polyimide resin between an array substrate (100) and a counter substrate (200), and an alignment film (141) subjected to alignment treatment in directions orthogonal to each other. , (241), the twisted nematic liquid crystal is held. Further, polarizing plates (311) and (313) are attached to the outer surfaces of the array substrate (100) and the counter substrate (200), respectively.

  FIG. 15 is a schematic plan view of the array substrate (100) of this embodiment. The lower side in the figure is located on the upper side of the screen of the liquid crystal display device (1). The scanning lines are sequentially selected from the upper side to the upper side.

  The array substrate (100) includes 480 Al-Y alloy scanning lines (111) arranged on the glass substrate (101), and one end of each scanning line (111) is connected to the glass substrate (101). A scanning line pad (152) is formed through one end side (101a) and passing through an oblique wiring portion (150). The structures of the oblique wiring portion (150) and the scanning line pad (152) are the same as those in the first embodiment, and the manufacturing process can be manufactured in the same manner.

  The array substrate (100) includes, on the glass substrate (101), signal lines (110) made of 1920 Mo-W alloys substantially orthogonal to the scanning lines (111). Each signal line (110) is a glass substrate (110). One end of 101) is drawn to the other end side (101b) side to form a signal line pad (162) through an oblique wiring portion (160). The structures of the oblique wiring portion (160) and the signal line pad (162) are the same as those in the first embodiment, and the manufacturing process can be manufactured in the same manner.

  A TFT (112) is disposed at the intersection of the scanning line (111) and the signal line (110). Further, the pixel electrode (131) of the TFT (112) is disposed on the scanning line (111) and the signal line (110) via an interlayer insulating film (127). This interlayer insulating film (127) can be composed of an inorganic insulating film such as a silicon nitride film, but by constituting a multilayer film of these inorganic insulating film and organic resin film, surface smoothness and interlayer insulation can be achieved. The property is further improved.

(TFT area structure)
The structure of the TFT (112) region will be described.

  Each scanning line (111) has an extended region (113) that extends in a thin line so as to overlap with the edges (131a) and (131b) along the signal line (110) of the adjacent pixel electrode (131). including. As shown in FIG. 4, the overlapping region (OS) between the extending region (113) and the pixel electrode (131) includes a first gate insulating film (115), a second gate insulating film (117), and an interlayer insulating film. The auxiliary capacitors (Cs) are configured to overlap each other via (127).

  Between the position of the upper end side along the scanning line (111) of the pixel electrode (131) and the position across the scanning line (111) other than the TFT region (121), a planar rectangular light shield A layer (170) is provided. The light shielding layer (170) is formed of the same material as the signal line (110).

  A counter substrate (200) facing the array substrate (100) is disposed on the glass substrate (201), and includes a TFT (121) region, a signal line (110), a scanning line (111), a pixel electrode (131), A matrix-like resinous light-shielding film (211) that shields the gap between the two. Further, red (R), green (G) and blue (B) color filters (221) are arranged in regions corresponding to the pixel electrodes (131), respectively, on which counter electrodes (made of a transparent electrode material ( 231) is arranged.

  As described above, according to the array substrate (100) of the liquid crystal display device (1) of this embodiment, interlayer insulation is provided between the signal lines (110) and the scanning lines (111) and the pixel electrodes (131). Since the film (127), or the first and second gate insulating films (115), (117) and the interlayer insulating film (127) are disposed, the pixel electrode (131) is connected to the wirings (110), (111). ) Can be sufficiently close to each other or overlapped with each other, so that a high aperture ratio can be realized.

  In addition, since the auxiliary capacitance (Cs) is formed between the pixel electrode 131 and the extension region 113 extending from the pixel electrode 131 and the adjacent scanning line 111, it is separately provided. It is not necessary to arrange an auxiliary capacity line or the like, and it is possible to further increase the aperture ratio. Further, since three types of insulating films (115), (117), (127) are arranged between the pixel electrode (131) and the extension region (113), this is caused by the structure of this embodiment. Occurrence of the short circuit between the layers is also greatly reduced.

By the way, in this embodiment, the pixel region is defined not by the light shielding film (211) disposed on the counter substrate (200) but by the extended region (113) on the array substrate (100). Further, since the light shielding layer (170) is provided between the upper end side of the pixel electrode (131) and the scanning line (111) corresponding to the pixel electrode (131), the light shielding layer (170) ) Also serves to demarcate the upper edge of the pixel region edge. Therefore, the first mask pattern for patterning the scanning line (111) and the fifth mask pattern for patterning the pixel electrode (131), regardless of the alignment accuracy between the array substrate (100) and the counter substrate (200). Since it is determined only by the alignment accuracy, it is not necessary to provide a margin for the width of the light-shielding film (211) in consideration of misalignment between the array substrate (100) and the counter substrate (200). Can be realized.

  Further, in order to define the pixel region, the extension region (113) of the scanning line (111) extends sufficiently along the edges (131a) and (131b) along the signal line (110) of the pixel electrode (131). However, according to this embodiment, the first gate insulating film (115) and the second gate insulating film (117) are provided between the pixel electrode (131) and the extension region (113) of the scanning line (111). In addition, since the interlayer insulating film (127) is disposed, a large increase in the auxiliary capacitance (Cs) can be suppressed without impairing the productivity.

  Further, according to this embodiment, as shown in FIG. 17, the contour of the signal line (110) coincides with the contours of the low-resistance semiconductor film (124a) and the semiconductor film (120). More specifically, in addition to the first and second gate insulating films (115) and (117), the low resistance semiconductor film (124a) and the semiconductor are always provided at the intersection of the signal line (110) and the scanning line (111). A film (120) is laminated. For this reason, even if mask misalignment occurs during each patterning, there is no capacitance fluctuation between the signal line (110) and the scanning line (111), and this reduces fluctuations in scanning line capacitance or signal line capacitance between products. The It also suppresses interlayer shorts caused by static electricity at the intersection of the signal line (110) and the scanning line (111), dust in the process, or pinholes in the two insulating layers (115) and (117). As a result, a high production yield can be secured.

  Further, according to this embodiment, as shown in FIG. 18, since the contour of the signal line (110) and the contours of the low-resistance semiconductor film (124a) and the semiconductor film (120) coincide, Even if this occurs, the capacitance fluctuation generated between the signal line (110) and the extension region (113) of the scanning line (111) can be sufficiently suppressed.

  Further, the signal line (110) and the extension region (113) of the scanning line (111) are overlapped, that is, the extension region (113) arranged adjacently via the signal line (111) in FIG. In addition to the insulating films (115) and (117), a semiconductor is connected between the signal line (110) and the extension region (113) of the scanning line (111). Since the film (120) is always arranged, it is possible to suppress inter-layer shorts caused by static electricity, dust in the process, or pinholes of the insulating films (115) and (117), thereby ensuring a high manufacturing yield. . Thus, the configuration in which the extending region (113) is arranged under the pixel electrode (131) adjacent to the signal line (111), capacitive coupling between the signal line (111) and the pixel electrode (131) is achieved. It is shielded by the extended region (113), and the influence of the potential of the pixel electrode (131) on the potential of the signal line (111) can be reduced. Moreover, the contour lines of the semiconductor film (120) and the low resistance semiconductor film (124a) disposed between the signal line (111) and the insulating films (115) and (117) are the same as the contour line of the signal line (111). Match. For these reasons, the signal line (111) and the pixel electrode (131) can be disposed sufficiently close to each other, thereby achieving a higher aperture ratio.

(Array substrate manufacturing process)
Next, the manufacturing process of the array substrate (100) will be described in detail with reference to FIGS.

(1) First Step As shown in FIG. 20, at the position of the AA ′ line cross section, a Mo film is formed on the Al—Y alloy film on the glass substrate (101) by sputtering to a thickness of 200 nm and 30 nm, respectively. After deposition, exposure is performed using a first mask pattern, and development and patterning (first patterning) are performed to produce 480 scanning lines (111). An extension region (113) is also formed at the same time when patterning the scanning line (111) (see FIG. 15).

  The scanning line (111) is formed on the glass substrate (101) in the same manner as described above even at the position of the cross section along the line DD '.

(2) Second Step After the first step, as shown in FIG. 21, a first gate insulating film (115) made of a silicon oxide film having a thickness of 150 nm is formed by plasma CVD at the position of the AA ′ line cross section. After depositing, a second gate insulating film (117) made of a silicon nitride film having a thickness of 150 nm, a semiconductor film (119) made of a-Si: H having a thickness of 50 nm, and a channel protective film made of a silicon nitride film having a thickness of 200 nm (121) is continuously deposited without exposure to the atmosphere.

  Also at the position along the line DD ′, the first gate insulating film (115), the second gate insulating film (117), and the channel protective film (121) are formed in the same manner as described above.

(3) Third Step After the second step, as shown in FIG. 22, at the position of the AA ′ line cross section, the scanning line (111) is self-aligned by the backside exposure technique using the scanning line (111) as a mask. The channel protective film (121) is patterned in a consistent manner, further exposed using a second mask pattern so as to correspond to the TFT region, developed, and patterned (second patterning). (122) is produced.

  The channel protective film 121 is removed by patterning at the position along the line DD ′.

(4) Fourth Step After the third step, as shown in FIG. 23, the surface of the semiconductor film (119) exposed so as to obtain a good ohmic contact is formed on the surface of the cross section along the line AA ′. A low resistance semiconductor film (123) made of n + a-Si: H having a thickness of 30 nm containing phosphorus as an impurity is deposited by plasma CVD, and a 300 nm thick Mo-W alloy film (125 ) Is deposited by sputtering.

  Also at the position of the DD ′ line cross section, the Mo—W alloy film (125) is deposited after the low resistance semiconductor film (123) is deposited in the same manner as described above.

(5) Fifth Step After the fourth step, as shown in FIG. 24, at the position of the AA ′ line cross section, exposure and development are performed using the third mask pattern, and the Mo—W alloy film (125 ), By controlling the etching selectivity between the low resistance semiconductor film (123) and the semiconductor film (119) with the second gate insulating film (117) and the channel protective film (122) made of a silicon nitride film. Patterned by plasma etching (third patterning) and integrated with semiconductor film (120), low resistance semiconductor films (124a), (124b), source electrode (126b), signal line (110), and signal line (110) A drain electrode (126a) integral with the connection end (110a) (see FIG. 15) and the signal line (110) is prepared.

  Also at the position along the line DD ′, the semiconductor film (120), the low-resistance semiconductor film (124b), and the Mo—W alloy film (125) are patterned in the shape of islands in the same manner as described above. Thereby, the position of the Mo—W alloy film (125) forms the light shielding layer (170). In this case, the light shielding layer (170) covers a part of the scanning line (111) without covering it.

(6) Sixth Step After the fifth step, an interlayer insulating film (127) made of a silicon nitride film having a thickness of 200 nm is deposited, and as shown in FIG. The mask pattern is exposed and developed, and the interlayer insulating film (127) corresponding to the source electrode (126b) is removed to form a contact hole (129a). Further, the interlayer insulating film (127) corresponding to the connection end (110a) (see FIG. 15) of the signal line (110) is removed to form a contact hole (129c) (fourth patterning).

  An interlayer insulating film (127) is also formed in the same manner as described above at the position along the line DD '.

(7) Seventh Step After the sixth step, as shown in FIG. 26, at the position of the AA ′ line cross section, an ITO film having a thickness of 100 nm is deposited thereon by sputtering, and a fifth mask pattern is formed. A pixel electrode (131) is produced through exposure, development, and patterning (fifth patterning) (see FIG. 15).

  At the position along the line DD ', the pixel electrode (131) is provided on the interlayer insulating film (127) in the same manner as described above. In this case, the light shielding layer (170) extends over the scanning line (111) and the pixel electrode (131).

(Effect of the second embodiment)
As described above, according to the array substrate of this embodiment, the array substrate can be manufactured by using five masks as the basic configuration. That is, the pixel electrode is arranged in the uppermost layer, and along with this, together with the signal line, source and drain electrodes, the semiconductor film and the like are patterned all together based on the same mask pattern, and for connecting the source electrode and the pixel electrode. By simultaneously forming the contact holes and the contact holes for exposing the connection ends of the signal lines and the scanning lines, the productivity can be improved with a small number of masks, and the manufacturing yield is not lowered.

  Further, in the above manufacturing process, the light shielding layer (170) can be simultaneously formed at the position across the pixel electrode (131) and the scanning line (111) corresponding to the pixel electrode (131). In this case, there is no need to increase the manufacturing process.

  In this embodiment, the light shielding layer (170) is disposed at the position across the scanning line (111) corresponding to the pixel electrode (131) and the pixel electrode (131). However, the pixel electrode (131) and the pixel electrode (131) The light shielding layer (170) may be disposed at a position straddling the scanning line (111) preceding or following the scanning line (111) corresponding to).

(Example of changes related to light shielding layer)
FIG. 27 shows a modification of the light shielding layer, which is different from the second embodiment in that the light shielding layer (180) corresponds to the pixel electrode (131) and the pixel electrode (131) and the scanning line (111). The first scanning line (111) and the lower side of the pixel electrode (131) are disposed so as to be electrically insulated from the light shielding layer (170). The light shielding layer (170) and the light shielding layer (180) may be integrated without being insulated.

  According to such a configuration, the opening of the pixel region can be defined on the array substrate, thereby realizing a high aperture ratio.

(Other changes)
In this embodiment, the case where the semiconductor film is made of a-Si: H has been described, but it goes without saying that it may be a polycrystalline silicon film or the like. Further, the drive circuit unit may be integrally formed in the peripheral region.

  Further, in the case where the pixel electrode is partially overlapped on the signal line or the scanning line, if the shield electrode is arranged with a metal film or the like through an insulating layer at least between the pixel electrode and the signal line, The influence of the pixel electrode due to the potential from the signal line can be reduced.

[Third embodiment]
A liquid crystal display device (1) according to a third embodiment of the present invention will be described below with reference to FIGS.

  As shown in FIG. 29, the liquid crystal display device (1) is made of polyimide resin between an array substrate (100) and a counter substrate (200), and an alignment film (141 having undergone alignment treatment in directions orthogonal to each other). ), (241), the liquid crystal layer (400) made of twisted nematic liquid crystal is held. Further, polarizing plates (311) and (313) are attached to the outer surfaces of the array substrate (100) and the counter substrate (200), respectively.

  The array substrate (100) is made of 480 Al-Y alloy scanning lines (111) arranged on the glass substrate (101), the same material as the scanning lines (111), and manufactured in the same process. An auxiliary capacitance line (113) substantially parallel to the scanning line (111), a first gate insulating film (115) made of a silicon oxide film disposed on the scanning line (111) and the auxiliary capacitance line (113), And a second gate insulating film (117) made of a silicon nitride film.

  The array substrate (100) includes 480 Al-Y alloy scanning lines (111) arranged on the glass substrate (101), and one end of each scanning line (111) is connected to the glass substrate (101). One end is pulled out to the side piece (101a) side, and a scanning line pad (152) is formed through an oblique wiring portion (150). The structures of the oblique wiring portion (150) and the scanning line pad (152) are the same as those in the first embodiment, and the manufacturing process can be manufactured in the same manner.

  The array substrate (100) includes, on the glass substrate (101), signal lines (110) made of 1920 Mo-W alloys substantially orthogonal to the scanning lines (111). Each signal line (110) is a glass substrate (110). One end of 101) is drawn to the other end side (101b) side to form a signal line pad (162) through an oblique wiring portion (160). The structures of the oblique wiring portion (160) and the signal line pad (162) are the same as those in the first embodiment, and the manufacturing process can be manufactured in the same manner.

  A TFT (112) is disposed at the intersection of the scanning line (111) and the signal line (110). Further, the pixel electrode (131) of the TFT (112) is disposed on the scanning line (111) and the signal line (110) via an interlayer insulating film (127). This interlayer insulating film (127) can be composed of an inorganic insulating film such as a silicon nitride film, but by constituting a multilayer film of these inorganic insulating film and organic resin film, surface smoothness and interlayer insulation can be achieved. The property is further improved.

  A counter substrate (200) facing the array substrate (100) is disposed on the glass substrate (201), and includes a TFT (121) region, a signal line (110), a scanning line (111), a pixel electrode (131), A matrix-like resinous light-shielding film (211) that shields the gap between the two. Further, red (R), green (G), and blue (B) color filters (221) are arranged in regions corresponding to the pixel electrodes (131), respectively, on which a counter electrode (made of a transparent electrode material ( 231) is arranged.

(TFT area structure)
The structure of the TFT (112) region will be described.

  In the array substrate (100), as shown in FIG. 29, the pixel electrode (131) has a first gate insulating film (115), a second gate insulating film (117), and an interlayer insulating film with respect to the scanning line (111). (127) and also to the signal line (110) via the interlayer insulating film (127). Therefore, even if the pixel electrodes (131) are arranged sufficiently close to the signal lines (110) or the scanning lines (111), they do not cause short-circuit defects with each other, so that a high manufacturing yield, high definition, Enables high aperture ratio design. That is, the pixel electrode (131) may be overlapped on the signal line (110) or the scanning line (111).

  Moreover, as shown in FIG. 30, the contour of the signal line (110) and the contours of the low-resistance semiconductor film (124a) and the semiconductor film (120) coincide. More specifically, in addition to the first and second gate insulating films (115) and (117), the low resistance semiconductor film (124a) and the semiconductor are always provided at the intersection of the signal line (110) and the scanning line (111). A film (120) is laminated. For this reason, even if mask misalignment occurs during each patterning, the step generated in the signal line (110) is sufficiently reduced, and there is no capacitance variation between the signal line (110) and the scanning line (111). Variation in scanning line capacity or signal line capacity between products is reduced. Interlayer shorts caused by static electricity at the intersection of the signal line (110) and the scanning line (111), dust in the process, or pinholes of the insulating films (115), (117), and (127) And a high production yield can be secured. The same is true between the signal line (110) and the auxiliary capacitance line (113).

(Wiring structure of auxiliary capacitance line)
Since it is necessary to apply the same voltage to each auxiliary capacitance line (113), for example, when applied to the counter electrode, this embodiment employs the following configuration. The wiring structure will be described with reference to FIGS.

  As described above, the auxiliary capacitance line (113) is formed of the same material as the scanning line (111) made of an Al—Y alloy, and is arranged substantially parallel to the scanning line (111).

  Therefore, as shown in FIG. 28, the auxiliary capacitance line connecting portion (190) is formed at the end of each auxiliary capacitance line (113) so as to be orthogonal to the auxiliary capacitance line (113). The structure of this auxiliary capacitance line connecting portion (190) is shown in FIG.

  The structure of the auxiliary capacity line connecting portion (190) will be described.

  On the auxiliary capacitance line (113) and the scanning line (111) arranged in parallel to each other, a first gate insulating film (115) made of a silicon oxide film, and a first gate insulating film made of a silicon nitride film deposited thereon. Two gate insulating films (117) are laminated and arranged. On these two insulating films (115) and (117), there are a semiconductor film (119), a low resistance semiconductor film (123) and a signal line which are substantially orthogonal to the storage capacitor line (113) and the scanning line (111). In the same process as (110), bundled wiring (125) made of Mo-W alloy film made of the same material is laminated. The auxiliary capacitor penetrates part of the two layers of insulating films (115), (117), semiconductor film (119), low-resistance semiconductor film (123), bundled wiring (125), and interlayer insulating film (127). A first contact hole (191) exposing a part of the line (113) is formed. The first contact hole is adjacent to the first contact hole (191) in the wiring direction of the bundle wiring (125), and a part of the interlayer insulating film (127) is removed to expose a part of the bundle wiring (125). A second contact hole (192) that is paired with (191) is disposed. An auxiliary capacitance line connection layer (193) made of ITO, which is the same material in the same process as the pixel electrode (131), is laminated between the pair of first contact holes (191) and second contact holes (192). Thus, each auxiliary capacitance line (113) and the bundled wiring (125) are electrically connected by the auxiliary capacitance line connection layer (193).

  Then, the end of this auxiliary capacitance line connecting portion (190) is pulled out to one end side (101a) side of the glass substrate (101) in the same manner as the scanning line pad (152), and the auxiliary capacitance line pad (194) is connected. Form. The structure of the auxiliary capacitance line pad (194) may be the same as that of the scanning line pad (152) or the signal line pad (162).

  When a voltage is applied to the auxiliary capacitance line pad (194), all the auxiliary capacitance lines (113) can be set to the same potential. In addition, since the storage capacitor line connecting portion (190) can be manufactured simultaneously with the manufacturing process of the array substrate (100) shown below, the manufacturing process is not complicated.

  In this embodiment, the auxiliary capacitor line connection layer (193) made of ITO is laminated only between the pair of first contact hole (191) and second contact hole (192). It does not matter even if it is wired along. Thereby, the disconnection failure of the bundled wiring (125) is reduced.

(Array substrate manufacturing process)
Next, the manufacturing process of the array substrate (100) will be described in detail with reference to FIGS.

(1) First Step As shown in FIG. 32, an Al—Y alloy film and a Mo film are deposited on a glass substrate (101) by sputtering to a thickness of 200 nm and 30 nm, respectively. The mask pattern is exposed, developed, and patterned (first patterning), so that 480 scanning lines (111) and 480 auxiliary capacitance lines (113) are produced.

(2) Second Step After the first step, as shown in FIG. 33, after depositing a first gate insulating film (115) made of a silicon oxide film having a thickness of 150 nm by plasma CVD, silicon nitride having a thickness of 150 nm is further deposited. A second gate insulating film (117) made of a film, a semiconductor film (119) made of a-Si: H having a thickness of 50 nm, and a channel protective film (121) made of a silicon nitride film having a thickness of 200 nm are continuously exposed to the atmosphere. Without film formation.

(3) Third Step After the second step, as shown in FIG. 34, a channel protective film (121) is formed on the scanning line (111) in a self-aligning manner by a backside exposure technique using the scanning line (111) as a mask. Patterning is performed, and exposure is performed using a second mask pattern so as to correspond to the TFT region, and development and patterning (second patterning) are performed to form an island-shaped channel protective film (122).

(4) Fourth Step After the third step, as shown in FIG. 35, the exposed semiconductor film (119) surface is treated with hydrofluoric acid (HF) solution so as to obtain good ohmic contact, and plasma CVD is performed. A low resistance semiconductor film (123) made of n + a-Si: H having a thickness of 30 nm containing phosphorus as an impurity is deposited by a method, and a Mo-W alloy film (125) having a thickness of 300 nm is deposited by sputtering.

(5) Fifth Step After the fourth step, as shown in FIG. 36, exposure and development are performed using a third mask pattern to obtain a Mo—W alloy film (125), a low resistance semiconductor film (123), and a semiconductor. The film (119) is patterned by plasma etching all at once (third patterning) by controlling the etching selectivity with the second gate insulating film (117) made of a silicon nitride film and the channel protective film (122). The semiconductor film (120), the low resistance semiconductor films (124a) and (124b), the source electrode (126b), the signal line (110) and the signal line (110) and the connection end (110a) (see FIG. 1) And a drain electrode (126a) integrated with the signal line (110).

  At this time, the first wiring for electrically connecting the auxiliary capacitance line (113) and the bundle wiring (125) at the same time as patterning the bundle wiring (125) constituting the auxiliary capacitance line connecting portion (190). A bundle wiring (125) on the auxiliary capacitance line (113) corresponding to the contact hole (191), the low-resistance semiconductor film (123), and a part of the semiconductor film (119) are removed through and opened (not shown) ).

(6) Sixth step After the fifth step, an interlayer insulating film (127) made of a silicon nitride film having a thickness of 200 nm is deposited and exposed and developed using a fourth mask pattern, as shown in FIG. The interlayer insulating film (127) corresponding to the source electrode (126b) is removed to form a contact hole (129a) (fourth patterning).

  At the same time, the interlayer insulating film (127) corresponding to the above-described opening is removed to expose a part of the auxiliary capacitance line (113) to form the first contact hole (191), and the first contact hole (191). A second contact hole (192) is formed by removing a part of the interlayer insulating film (127) so that a part of the bundled wiring (125) is exposed in the vicinity.

(7) Seventh Step After the sixth step, as shown in FIG. 38, an ITO film having a thickness of 100 nm is deposited thereon by sputtering, and exposure, development, and patterning (fifth mask pattern) are performed using a fifth mask pattern. Through the patterning process, the pixel electrode 131 is manufactured.

  At the same time, an auxiliary capacitance line connection layer (193) for connecting the auxiliary capacitance line (113) and the bundled wiring (125) through the first contact hole (191) and the second contact hole (192) is formed.

(Effect of the third embodiment)
As described above, according to the array substrate of this embodiment, the array substrate can be manufactured by using five masks as the basic configuration. That is, the pixel electrode is arranged on the uppermost layer, and along with this, together with the signal line, source and drain electrodes, the semiconductor film and the like are collectively patterned based on the same mask pattern, and for connecting the source electrode and the pixel electrode. The contact hole for exposing the connection end of the signal line and the scanning line is simultaneously created together with the production of the contact hole, thereby reducing the step generated in the wiring to prevent the production yield from being reduced and producing with a small number of masks. This is an optimal process in which different requirements for improving the performance are simultaneously achieved.

(Other changes)
In this embodiment, the case where the semiconductor film is made of a-Si: H has been described, but it goes without saying that the semiconductor film may be a microcrystalline silicon film, a polycrystalline silicon film, a single crystal silicon film, or the like. Further, the drive circuit unit may be integrally formed in the peripheral region.

  Further, in the case where the pixel electrode is partially overlapped on the signal line or the scanning line, if the shield electrode is arranged with a metal film or the like through an insulating layer at least between the pixel electrode and the signal line, The influence of the pixel electrode due to the potential from the signal line can be reduced.

  In the above-described embodiments, the light transmission type liquid crystal display device is used, and the pixel electrode is formed of a transparent conductive film, for example, ITO. For this reason, the lower layer wiring portion and the upper layer wiring portion are all electrically connected via a connection layer made of ITO arranged through a pair of contact holes. Since this ITO has a relatively high resistance, it is desirable that the gap between the pair of contact holes be short, for example, 20 microns or less, and further 15 microns or less. Note that a low-resistance material can also be used if the connection layer is formed in a separate process from the pixel electrode. In addition, since the pixel electrode can be made of a low-resistance material such as aluminum if it is constituted by a reflection type, the gap between the pair of contact holes is not largely restricted.

  In addition to the TN liquid crystal, various materials such as a polymer dispersed liquid crystal, a ferroelectric liquid crystal, and an antiferroelectric liquid crystal can be used for the liquid crystal layer.

FIG. 1 is a partial schematic plan view of an array substrate according to an embodiment of the present invention. FIG. 2 is a schematic cross-sectional view of the liquid crystal display device taken along line A-A ′ in FIG. 1. FIG. 3 is a schematic cross-sectional view of the liquid crystal display device taken along line B-B ′ in FIG. 1. 4 is a schematic cross-sectional view of the liquid crystal display device taken along line C-C ′ in FIG. 1. FIG. 5 is a schematic cross-sectional view of the liquid crystal display device taken along the line D-D ′ in FIG. 1. FIG. 6 is a schematic cross-sectional view of the liquid crystal display device taken along line E-E ′ in FIG. 1. FIG. 7 is a diagram for explaining a first step of manufacturing the array substrate in FIG. FIG. 8 is a diagram for explaining a second step of manufacturing the array substrate in FIG. FIG. 9 is a diagram for explaining a third step of manufacturing the array substrate in FIG. FIG. 10 is a diagram for explaining a fourth step of manufacturing the array substrate in FIG. FIG. 11 is a diagram for explaining a fifth step of manufacturing the array substrate in FIG. FIG. 12 is a view for explaining a sixth step of manufacturing the array substrate in FIG. FIG. 13 is a diagram for explaining a seventh step of manufacturing the array substrate in FIG. FIG. 14 is a diagram illustrating a modification example of the structure near the outer periphery of the signal line. FIG. 15 is a partial schematic plan view of an array substrate according to the second embodiment of the present invention. FIG. 16 is a schematic cross-sectional view of the liquid crystal display device taken along the line A-A ′ in FIG. 15. FIG. 17 is a schematic cross-sectional view of the liquid crystal display device taken along line B-B ′ in FIG. 15. FIG. 18 is a schematic cross-sectional view of the liquid crystal display device taken along line C-C ′ in FIG. 15. FIG. 19 is a schematic cross-sectional view of the liquid crystal display device taken along the line D-D ′ in FIG. 15. FIG. 20 is a diagram for explaining a first step of manufacturing the array substrate in FIG. FIG. 21 is a diagram for explaining a second step of manufacturing the array substrate in FIG. FIG. 22 is a diagram for explaining a third step of manufacturing the array substrate in FIG. FIG. 23 is a diagram for explaining a fourth step of manufacturing the array substrate in FIG. FIG. 24 is a diagram for explaining a fifth step of manufacturing the array substrate in FIG. FIG. 25 is a view for explaining a sixth step of manufacturing the array substrate in FIG. FIG. 26 is a diagram for explaining a seventh step of manufacturing the array substrate in FIG. FIG. 27 is a partial schematic plan view of an array substrate according to a modification of the second embodiment. FIG. 28 is a partial schematic plan view of the array substrate according to the third embodiment of the present invention. FIG. 29 is a schematic cross-sectional view of the liquid crystal display device taken along line A-A ′ in FIG. 28. 30 is a schematic cross-sectional view of the liquid crystal display device taken along line B-B ′ in FIG. 28. FIG. 31 is a schematic cross-sectional view of the liquid crystal display device taken along line C-C ′ in FIG. 28. FIG. 32 is a diagram for explaining a first step of manufacturing the array substrate in FIG. FIG. 33 is a diagram for explaining a second step of manufacturing the array substrate in FIG. FIG. 34 is a diagram for explaining a third step of manufacturing the array substrate in FIG. FIG. 35 is a diagram for explaining a fourth step of manufacturing the array substrate in FIG. FIG. 36 is a diagram for explaining a fifth step of manufacturing the array substrate in FIG. FIG. 37 is a diagram for explaining a sixth step of manufacturing the array substrate in FIG. FIG. 38 is a diagram for explaining a seventh step of manufacturing the array substrate in FIG.

Explanation of symbols

110 signal line 111 scanning line 112 thin film transistor 113 extension region 115 first insulating film 117 first insulating film 120 semiconductor film 126a drain electrode 126b source electrode 131 pixel electrode

Claims (12)

A plurality of scanning lines including a gate electrode region disposed on the substrate, a storage capacitor line substantially parallel to the scanning line, a first insulating film disposed thereon, and a semiconductor disposed at least on the gate electrode region A thin film transistor including a source electrode and a drain electrode electrically connected to the semiconductor film; a second insulating film disposed on the thin film transistor; and the scan line electrically connected to the drain electrode In a display device array substrate comprising a signal line substantially orthogonal to the pixel electrode and a pixel electrode electrically connected to the source electrode,
Including bundled wiring wired in a direction substantially orthogonal to the auxiliary capacitance line via the first insulating film;
The conductive layer is stacked between a first contact hole that exposes the storage capacitor line and a second contact hole that is spaced apart from the first contact hole and that exposes the bundled wiring. The array substrate for a display device, wherein the auxiliary capacitance line and the bundled wiring are electrically connected. The bundled wiring is made of the same material as the signal line,
The array substrate for a display device according to claim 1, wherein the conductive layer is made of the same material as the pixel electrode. A low-resistance semiconductor film is interposed between the semiconductor film and the source and drain electrodes, and the signal line and the semiconductor layer in the intersection region are made of the same material as the low-resistance semiconductor film. The array substrate for a display device according to claim 1, wherein a low-resistance semiconductor layer is interposed. The array substrate for a display device according to claim 1, wherein the semiconductor film is mainly composed of amorphous silicon. A plurality of scanning lines including a gate electrode region disposed on a substrate, an auxiliary capacitance line substantially parallel to the scanning line, a gate insulating film disposed on the scanning line, and a semiconductor film disposed on at least the gate electrode region A thin film transistor including a source electrode and a drain electrode electrically connected to the semiconductor film; an interlayer insulating film disposed on the thin film transistor; and an electrical connection to the drain electrode and substantially the same as the scanning line. In an array substrate for a display device comprising orthogonal signal lines and a pixel electrode electrically connected to the source electrode,
Including bundled wiring wired in a direction substantially orthogonal to the auxiliary capacitance line through the gate insulating film;
The conductive layer is stacked between a first contact hole that exposes the storage capacitor line and a second contact hole that is spaced apart from the first contact hole and that exposes the bundled wiring. The array substrate for a display device, wherein the auxiliary capacitance line and the bundled wiring are electrically connected. The bundled wiring is made of the same material as the signal line,
The array substrate for a display device according to claim 5, wherein the conductive layer is made of the same material as the pixel electrode. A plurality of scanning lines including a gate electrode region disposed on the substrate, a storage capacitor line substantially parallel to the scanning line, a first insulating film disposed thereon, and a semiconductor disposed at least on the gate electrode region A thin film transistor including a source electrode and a drain electrode electrically connected to the semiconductor film; a second insulating film disposed on the thin film transistor; and the scan line electrically connected to the drain electrode In a liquid crystal display device having an array substrate including a signal line substantially orthogonal to the pixel electrode and a pixel electrode electrically connected to the source electrode,
Including bundled wiring wired in a direction substantially orthogonal to the auxiliary capacitance line via the first insulating film;
The conductive layer is stacked between a first contact hole that exposes the storage capacitor line and a second contact hole that is spaced apart from the first contact hole and that exposes the bundled wiring. The liquid crystal display device, wherein the auxiliary capacitance line and the bundled wiring are electrically connected. The bundled wiring is made of the same material as the signal line,
The liquid crystal display device according to claim 7, wherein the conductive layer is made of the same material as the pixel electrode. A low-resistance semiconductor film is interposed between the semiconductor film and the source and drain electrodes, and the signal line and the semiconductor layer in the intersection region are made of the same material as the low-resistance semiconductor film. The liquid crystal display device according to claim 7, wherein a low-resistance semiconductor layer is interposed. The liquid crystal display device according to claim 7, wherein the semiconductor film is mainly composed of amorphous silicon. A plurality of scanning lines including a gate electrode region disposed on a substrate, an auxiliary capacitance line substantially parallel to the scanning line, a gate insulating film disposed on the scanning line, and a semiconductor film disposed on at least the gate electrode region A thin film transistor including a source electrode and a drain electrode electrically connected to the semiconductor film; an interlayer insulating film disposed on the thin film transistor; and an electrical connection to the drain electrode and substantially the same as the scanning line. In a liquid crystal display device having an array substrate having orthogonal signal lines and pixel electrodes electrically connected to the source electrodes,
Including bundled wiring wired in a direction substantially orthogonal to the auxiliary capacitance line through the gate insulating film;
The conductive layer is stacked between a first contact hole that exposes the storage capacitor line and a second contact hole that is spaced apart from the first contact hole and that exposes the bundled wiring. The liquid crystal display device, wherein the auxiliary capacitance line and the bundled wiring are electrically connected. The bundled wiring is made of the same material as the signal line,
The liquid crystal display device according to claim 11, wherein the conductive layer is made of the same material as the pixel electrode.

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