JP2012204398A - Thin film transistor and manufacturing method therefor, and image display device using thin film transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a high quality bottom gate type thin film transistor provided on a resin substrate at a low cost by simplifying the manufacturing process, and to provide an image display device.SOLUTION: The bottom gate type thin film transistor comprises at least a resin substrate, a gate electrode and an insulating adhesion layer provided on the same surface of the resin substrate, and a gate insulation layer provided on the gate electrode and the insulating adhesion layer. The gate electrode contains a metal. The insulating adhesion layer contains an oxyhydroxide of the metal contained in the gate electrode. The metal contains Al, and the thickness of the gate electrode is 10-100 nm.

Description

  The present invention relates to a thin film transistor, a manufacturing method thereof, and an image display device using the thin film transistor.

  At present, a general flat panel display (FPD) is driven by an active matrix of a field effect transistor using amorphous silicon or polycrystalline silicon as an active layer.

  On the other hand, in recent years, attempts have been made to use a resin substrate instead of a glass substrate in order to further reduce the thickness, weight, and breakage resistance of an FPD.

  However, the manufacture of the transistor using the above-described silicon thin film requires a relatively high temperature thermal process and is generally difficult to form directly on a resin substrate having low heat resistance.

  Therefore, development of a thin film transistor using an oxide semiconductor that can be formed at a low temperature as an active layer has been actively performed (for example, Patent Document 1).

  As the gate insulating layer of the thin film transistor using the above-described oxide semiconductor as an active layer, for example, a single film of silicon oxide, silicon nitride, or the like formed by plasma CVD or magnetron sputtering is used, or a film in which these are laminated. (For example, Patent Document 2).

JP 2006-165532 A Japanese Patent Laid-Open No. 2007-73697

  However, a gate insulating layer formed on a resin substrate at a low temperature by a plasma CVD method or a magnetron sputtering method has low adhesion to the substrate, so that the gate insulating layer is easily peeled off from the substrate, and a highly reliable thin film transistor cannot be obtained. There was a problem.

  Therefore, although it is necessary to provide an adhesion layer between the substrate and the gate insulating layer, there is a concern about an increase in manufacturing cost due to an increase in one process for providing the adhesion layer.

  Therefore, in the present invention, in order to solve the above-described requirements, a high-quality and low-cost thin film transistor and a method for manufacturing the same are formed by forming an adhesion layer between the substrate and the gate insulating layer without increasing the number of steps, and An object is to provide an image display device using the thin film transistor.

  The present invention employs the following configuration in order to solve the above problems.

  The first invention is a bottom-gate thin film transistor. The bottom-gate thin film transistor includes a resin substrate, a gate electrode and an insulating adhesive layer provided on the same surface of the resin substrate, and a gate insulating layer provided on the gate electrode and the insulating adhesive layer. At least. The gate electrode includes a metal. The insulating adhesive layer includes a metal oxyhydroxide contained in the gate electrode.

  According to a second aspect, in the first aspect, the metal is a metal containing Al.

  According to a third invention, in the first or second invention, the thickness of the gate electrode is 10 nm or more and 100 nm or less.

  According to a fourth invention, in the first or second invention, the gate insulating layer contains at least one compound of silicon oxide, silicon nitride, and silicon oxynitride.

  According to a fifth invention, in the first or second invention, a metal oxide semiconductor layer is further provided on the gate insulating layer. The metal oxide semiconductor layer includes at least one element of In, Zn, and Ga.

  The sixth invention comprises at least a resin substrate, a gate electrode provided on the same surface of the resin substrate, an insulating adhesive layer, and a gate insulating layer provided on the gate electrode and the insulating adhesive layer. This is a method for manufacturing a bottom-gate thin film transistor. The manufacturing method includes a metal film forming step for forming a film containing a metal on a resin substrate, a resist coating step for covering a portion to be a gate electrode on the resin substrate with a resist, and a high temperature for treating the resin substrate with high-temperature water. A water treatment step, and an oxyhydration step of oxyhydrating a film containing a metal on a resin substrate not covered with a resist.

  In a seventh aspect based on the sixth aspect, the metal is a metal containing Al.

  In an eighth aspect based on the sixth or seventh aspect, in the high temperature water treatment step, a gate electrode is formed in a portion covered with a resist and an insulating adhesive layer is formed in a portion not covered with the resist. It is characterized by that.

  According to a ninth invention, in the sixth or seventh invention, the temperature during the high-temperature water treatment in the high-temperature water treatment step is from 100 ° C. to 180 ° C.

  A tenth invention is an image display device. The image display device includes the bottom-gate thin film transistor array described in any one of the first to fifth aspects and an image display medium.

  In an eleventh aspect based on the tenth aspect, the image display medium is an electrophoretic method.

  According to the present invention, it is possible to provide a high-quality and low-cost thin film transistor, a manufacturing method thereof, and an image display device using the thin film transistor. In other words, the gate electrode is made of metal and the insulating adhesion layer contains the metal oxyhydroxide contained in the gate electrode, thereby providing high adhesion to the gate electrode having sufficient conductivity and the substrate and the gate insulation layer. A thin film transistor having an insulating adhesive layer can be obtained.

  Further, by setting the thickness of the gate electrode to 10 nm or more and 100 nm or less, it is possible to obtain a gate electrode having sufficient conductivity and an adhesion layer having sufficient insulation. If the thickness is less than 10 nm, there may occur a problem that a portion in which no film is formed is generated in the film due to island growth. On the other hand, when the thickness exceeds 100 nm, it is difficult to completely oxyhydroxide a metal material containing Al to the inside of the film, and an adhesion layer having sufficient insulation cannot be obtained.

  In addition, by forming the gate insulating layer using a material containing any one compound of silicon oxide, silicon nitride, silicon oxynitride, and aluminum oxide, the gate insulating layer can have sufficient withstand voltage. it can.

  In addition, by forming the metal oxide semiconductor layer with a material containing any one of In, Zn, and Ga, a high-quality thin film transistor can be formed over a resin substrate at a low temperature.

  Also, a step of forming a metal-containing film on the substrate, a step of covering the portion to be the gate electrode with a resist, a step of treating the substrate with high-temperature water and oxyhydrating the film containing the metal in the non-resist coating portion By including the insulating adhesive layer in the non-resist coating portion and the metal gate electrode is formed in the resist coating portion, the gate electrode and the adhesive layer can be formed simultaneously. That is, the gate insulating layer and the insulating adhesion layer can be formed on the resin substrate without increasing the number of steps.

  Moreover, it becomes possible to fully oxyhydroxide the area | region used as an adhesion layer by the temperature at the time of the high temperature water treatment to the metal material containing Al being 100 degreeC or more. In addition, when the temperature is set to 180 ° C. or lower, even if an inexpensive resin substrate is used, processing can be performed without damaging the substrate.

1 is a schematic cross-sectional view illustrating a structure of a thin film transistor according to an embodiment of the present invention. Schematic sectional view showing the structure of a thin film transistor according to another embodiment of the present invention Schematic sectional view showing the structure of the thin film transistor according to Examples 1 and 2 and Comparative Examples 2 and 3 Schematic sectional view showing one element of a thin film transistor array substrate according to Examples 1 and 2 and Comparative Examples 2 and 3 Schematic sectional view showing one pixel of an image display device using thin film transistors according to Examples 1 and 2 and Comparative Examples 2 and 3 Schematic sectional view showing the structure of a thin film transistor according to Comparative Example 1

  Hereinafter, a thin film transistor according to an embodiment of the present invention, a method for manufacturing the same, and an image display device using the thin film transistor will be described with reference to the drawings. Hereinafter, after describing the thin film transistor and the manufacturing method thereof according to an embodiment of the present invention, an image display device using the thin film transistor will be described.

<Thin film transistor>
First, a thin film transistor according to an embodiment of the present invention will be described. In the following description, the same components are denoted by the same reference numerals, and redundant descriptions are omitted. The structure of the thin film transistor described below is an example, and the thin film transistor according to the present invention is not limited to this structure.

  FIG. 1 shows an example of a thin film transistor according to an embodiment of the present invention. The thin film transistor according to this embodiment includes a gate electrode 11, an insulating adhesive layer 12 (sometimes referred to as an insulating adhesive layer 12), a gate insulating layer 13, a metal oxide semiconductor layer 14, and a source electrode on a resin substrate 10. 15 and a bottom gate-top contact type thin film transistor including a drain electrode 16.

  FIG. 2 shows an example of a schematic sectional view of a thin film transistor according to another embodiment of the present invention. The thin film transistor according to this embodiment includes a gate electrode 11, an insulating adhesive layer 12 (sometimes referred to as an insulating adhesive layer 12), a gate insulating layer 13, a metal oxide semiconductor layer 14, and a source electrode on a resin substrate 10. 15 is a bottom gate-bottom contact type thin film transistor including 15 and a drain electrode 16.

  Examples of the resin substrate 10 include polymethyl methacrylate, polyacrylate, polycarbonate, polystyrene, polyethylene sulfide, polyethersulfone (PES), polyolefin, polyethylene terephthalate, polyethylene naphthalate (PEN), cycloolefin polymer, and polyethersulfene. , Triacetyl cellulose, polyvinyl fluoride film, ethylene-tetrafluoroethylene copolymer resin, weather resistant polyethylene terephthalate, weather resistant polypropylene, glass fiber reinforced acrylic resin film, glass fiber reinforced polycarbonate, transparent polyimide, fluororesin, cyclic polyolefin Series resins and the like can be used. These substrates can be used alone, or a composite substrate in which two or more kinds are laminated can be used. A substrate in which a color filter is formed on the resin substrate 10 can also be used.

  A metal containing Al is used for the gate electrode 11. Specifically, Al, Al—Nd, Al—Ni, and the like can be given. These electrodes can be formed by sputtering, vacuum deposition, or the like, but are not limited to these methods. Note that the thickness of the gate electrode 11 is preferably 10 nm to 100 nm.

The insulating adhesive layer 12 is made of the same metal as the metal contained in the gate electrode 11, in this embodiment, a metal oxyhydroxide containing Al. The insulating adhesion layer 12 is formed by oxyhydrating a metal material containing Al constituting the gate electrode 11 using high-temperature water treatment. The resistivity of the insulating adhesive layer 12 is 1.0 × 10 ⁻¹¹ Ω · cm or less, preferably 1.0 × 10 ⁻¹³ Ω · cm or less. The insulating adhesive layer 12 is on the same plane as the gate electrode 11 provided on the resin substrate 10 and on the resin substrate 10 (see, for example, FIG. 1).

  The gate insulating layer 13 is preferably made of silicon oxide, silicon nitride, silicon oxynitride, or the like. By using these materials, the adhesiveness with the insulating adhesive layer 12 described above is enhanced, and an inexpensive film having sufficient insulating properties can be obtained. Note that the gate insulating layer 13 is preferably formed by a sputtering method, a plasma CVD (Chemical Vapor Deposition) method, or an atomic layer deposition method, but is not limited thereto.

  Examples of the metal oxide semiconductor layer 14 include an oxide containing at least one element selected from zinc, indium, and gallium. Specific examples of the oxide include known materials such as zinc oxide, indium oxide, indium zinc oxide, and zinc gallium indium oxide (In—Ga—Zn—O), but are not limited thereto. Absent. The film thickness of the metal oxide semiconductor layer 14 is desirably at least 10 nm. If the thickness is less than 10 nm, a problem may occur that a portion where no semiconductor is formed in the film is generated due to island growth.

For the source electrode 15 and the drain electrode 16, a low resistance metal material such as Au, Ag, Cu, Cr, Al, Mg, Li, or Mo is preferably used. Indium oxide (In ₂ O ₃ ), tin oxide (SnO ₂ ), zinc oxide (ZnO), cadmium oxide (CdO), indium cadmium oxide (CdIn ₂ O ₄ ), cadmium tin oxide (Cd ₂ SnO ₄ ), oxide Oxide materials such as zinc tin (Zn ₂ SnO ₄ ) and indium zinc oxide (In—Zn—O) are also preferably used.

  It is also preferable to add impurities to these oxide materials in order to increase conductivity. For example, indium oxide is doped with tin, molybdenum, or titanium, tin oxide is doped with antimony or fluorine, and zinc oxide is doped with indium, aluminum, or gallium. Among these, indium tin oxide (commonly called ITO) in which tin is doped in indium oxide is particularly preferably used because of its low resistivity. An organic conductive material such as polyethylenedioxythiophene (PEDOT) can also be used suitably.

  Note that the gate electrode 11, the source electrode 15, and the drain electrode 16 may all be made of the same material, or may be made of different materials. However, in order to reduce the number of steps in manufacturing the thin film transistor, it is more desirable that the source electrode 15 and the drain electrode 16 are made of the same material. These electrodes are formed by a vacuum deposition method, a sputtering method, a laser ablation method, a plasma CVD (Chemical Vapor Deposition) method, a photo CVD method, a hot wire CVD method, or the like. In addition, the conductive material described above in an ink form or a paste form can be applied by screen printing, letterpress printing, an ink jet method or the like, and baked, but is not limited thereto.

<Method for Manufacturing Thin Film Transistor>
Next, an example of a method for manufacturing a thin film transistor according to an embodiment of the present invention will be described.

  First, an Al film is formed on the resin substrate 10 by sputtering (film thickness is 80 nm), a resist pattern is formed by photolithography, and then high-temperature water treatment is performed. Then, after the treatment, the resist is peeled off, and the gate electrode 11 and the insulating adhesion layer 12 are formed.

Next, SiN _x is formed by a plasma CVD method (thickness: 500 nm) to form a gate insulating layer 13, and then a metal oxide semiconductor layer 14 made of InGaZnO is formed at room temperature by a sputtering method.

  Finally, Mo is formed by sputtering and a resist pattern is formed by photolithography, and then dry etching and peeling are performed to form the source electrode 15 and the drain electrode 16.

  The above is an example of a method for manufacturing a thin film transistor according to an embodiment of the present invention.

<Image display device using thin film transistor>
Next, an image display device using a thin film transistor will be described.

In the image display device, an electrophoretic medium 22 is sandwiched between a thin film transistor array substrate 21 and a counter electrode 23 (see FIG. 5). The thin film transistor array substrate 21 is formed by forming a sealing layer 18 made of SiO _x , an interlayer insulating layer 19 made of polymer, and a pixel electrode 20 made of ITO on the source electrode 15 and the drain electrode 16 of the thin film transistor. Yes (see FIG. 4).

  Hereinafter, the present invention will be described based on Examples 1 and 2 and Comparative Examples 1 to 3.

Example 1
In Example 1, a thin film transistor as shown in FIG. 3, a thin film transistor array substrate as shown in FIG. 4, and an image display device as shown in FIG. 5 were produced.

  First, a PEN substrate (with a film thickness of 125 μm) is used as the resin substrate 10, Al is formed on the PEN substrate at a room temperature (with a film thickness of 80 nm) using a DC magnetron sputtering apparatus, and a photolithography method is used. After forming the resist pattern, high-temperature water treatment was performed at 100 ° C. for 10 minutes. After the treatment, the resist was peeled off to form the gate electrode 11, the capacitor electrode 17, and the insulating adhesion layer 12. Note that the input power during the Al film formation was 200 W, the gas flow rate was Ar = 50 SCCM, and the film formation pressure was 1.0 Pa.

Next, SiN _x was formed using a plasma CVD apparatus (film thickness: 500 nm) to form the gate insulating layer 13. In forming the gate insulating layer 13, SiH ₄ = 50 SCCM and NH ₃ = 50 SCCM were allowed to flow as source gases, the input power was 300 W, the deposition pressure was 3.0 Pa, and the substrate temperature was 150 ° C.

Next, a metal oxide semiconductor layer 14 made of InGaZnO was formed at room temperature (film thickness: 40 nm) using a DC magnetron sputtering apparatus. In the formation of the metal oxide semiconductor layer 14, the input power during the film formation was 100 W, the gas flow rate was Ar = 100 SCCM, O ₂ = ₂ SCCM, and the film formation pressure was 1.0 Pa.

  Finally, a film of Mo is formed at room temperature (film thickness: 80 nm) using a DC magnetron sputtering apparatus, a resist pattern is formed using a photolithography method, dry etching and peeling are performed, and the source electrode 15 and the drain electrode 16 are formed. And a thin film transistor was obtained (see FIG. 3). The input power during the Mo film formation was 200 W, the gas flow rate was Ar = 50 SCCM, and the film formation pressure was 1.0 Pa. The length between the source / drain electrodes is 20 μm, and the width between the source / drain electrodes is 5 μm.

  The adhesion between the resin substrate 10 and the gate insulating layer 13 through the insulating adhesion layer 12 of the thin film transistor thus manufactured is determined according to JIS-K-5600 (1999) 5-6 adhesion (cross-cut method). Evaluation was performed according to the test. As a result, it showed good adhesion applicable to classification 0 (the edge of the cut was completely smooth and there was no peeling of any lattice eye).

In addition, the cross cut was performed using a 1 mm gap cutter guide. In addition, measurement was performed using a semiconductor parameter analyzer (SCS4200 manufactured by Keithley) with a gate voltage of −10 V to +20 V and a drain voltage of 5 V. As a result, the transistor characteristics of the thin film transistor are as follows: the mobility is 8 cm ² / Vs, the ON / OFF ratio when the voltage of 10 V is applied between the source / drain electrodes is 6 digits, and the gate leakage current at the gate voltage of 20 V is 4. 2 × 10 ⁻¹¹ A, showing good transistor characteristics.

Next, the source / drain electrodes are formed by the above-described manufacturing method, and the sealing layer 18 made of SiO _x , the interlayer insulating layer 19 made of polymer, and the pixel electrode 20 made of ITO are formed on the thin film transistor. A thin film transistor array substrate 21 as shown in FIG.

  The thin film transistor array substrate 21 has a size of one pixel of 125 μm × 125 μm and 480 × 640 pixels.

  Next, when an image display device as shown in FIG. 5 was produced by driving the electrophoretic medium 22 between the transistor array substrate 21 and the counter electrode 23 and driven, a good display was obtained.

(Example 2)
In Example 2, a thin film transistor as shown in FIG. 3, a thin film transistor array substrate as shown in FIG. 4, and an image display device as shown in FIG. 5 were produced.

  First, an Al—Nd alloy film is formed on a PEN substrate (thickness: 125 μm) as a resin substrate 10 at room temperature using a DC magnetron sputtering apparatus (film thickness: 100 nm), and a resist pattern is formed using a photolithography method. After forming, high temperature water treatment was performed at 100 ° C. for 20 minutes. After the treatment, the resist was peeled off to form the gate electrode 11, the capacitor electrode 17, and the insulating adhesion layer 12. Note that the input power during the deposition of Al—Nd was 200 W, the gas flow rate was Ar = 50 SCCM, and the deposition pressure was 1.0 Pa.

Next, SiO ₂ was deposited (film thickness 300 nm) using a magnetron sputtering apparatus to form the gate insulating layer 13. In forming the gate insulating layer 13, the input power during film formation was 500 W, the film formation pressure was 1.0 Pa, and the substrate temperature was room temperature.

Next, a metal oxide semiconductor layer 14 made of InGaZnO was formed at room temperature (film thickness: 40 nm) by sputtering. In the formation of the metal oxide semiconductor layer 14, the input power at the time of film formation was 100 W, the gas flow rate was Ar = 100 SCCM, O ₂ = 1 SCCM, and the film formation pressure was 1.0 Pa.

  Finally, Mo is formed at room temperature (film thickness: 80 nm) using a DC magnetron sputtering apparatus, a resist pattern is formed using a photolithography method, dry etching and peeling are performed, and the source electrode 15 and the drain electrode are formed. 16 to form a thin film transistor (see FIG. 3). The input power during the Mo film formation was 200 W, the gas flow rate was Ar = 50 SCCM, and the film formation pressure was 1.0 Pa. The length between the source / drain electrodes is 20 μm, and the width between the source / drain electrodes is 5 μm.

  The adhesion between the resin substrate 10 and the gate insulating layer 13 through the insulating adhesion layer 12 of the thin film transistor thus manufactured is determined according to JIS-K-5600 (1999) 5-6 adhesion (cross-cut method). Evaluation was performed according to the test. As a result, it showed good adhesion applicable to classification 0 (the edge of the cut was completely smooth and there was no peeling of any lattice eye).

In addition, the cross cut was performed using a 1 mm gap cutter guide. The transistor characteristics of a thin film transistor measured using a semiconductor parameter analyzer (SCS4200 manufactured by Keithley) with a gate voltage of −10 V to +20 V and a drain voltage of 5 V are as follows: mobility 7 cm ² / Vs When the voltage was applied, the ON / OFF ratio was 6 digits, and the gate leakage current at a gate voltage of 20 V was 2.2 × 10 ⁻¹¹ A, indicating good transistor characteristics.

Next, the source / drain electrodes are formed by the manufacturing method described above, and the sealing layer 18 made of SiO _x , the interlayer insulating layer 19 made of polymer, and the pixel electrode 20 made of ITO are formed on the thin film transistor, and FIG. A thin film transistor array substrate 21 as shown was obtained.

  The thin film transistor array substrate 21 has a size of one pixel of 125 μm × 125 μm and 480 × 640 pixels.

  Next, when an image display device as shown in FIG. 5 was produced by driving the electrophoretic medium 22 between the transistor array substrate 21 and the counter electrode 23 and driven, a good display was obtained.

(Comparative Example 1)
In Comparative Example 1, a thin film transistor as shown in FIG.

  First, an Al—Nd alloy film is formed at room temperature (100 nm) using a DC magnetron sputtering apparatus on a PEN substrate (thickness: 125 μm) as a resin substrate 10, and a resist pattern is formed using a photolithography method. Then, the non-resist coating portion was removed using a wet etching method, and finally the resist was peeled off to form the gate electrode 11 and the capacitor electrode 17. Note that the input power during the deposition of Al—Nd was 200 W, the gas flow rate was Ar = 50 SCCM, and the deposition pressure was 1.0 Pa.

Next, SiO ₂ was formed (300 nm) using a magnetron sputtering apparatus, and the gate insulating layer 13 was formed. In forming the gate insulating layer 13, the input power during film formation was 500 W, the film formation pressure was 1.0 Pa, and the substrate temperature was room temperature.

Next, a metal oxide semiconductor layer 14 made of InGaZnO was formed at room temperature (40 nm) by sputtering. In the formation of the metal oxide semiconductor layer 14, the input power at the time of film formation was 100 W, the gas flow rate was Ar = 100 SCCM, O ₂ = 1 SCCM, and the film formation pressure was 1.0 Pa.

  Finally, after forming a film of Mo at room temperature (80 nm) using a DC magnetron sputtering apparatus and forming a resist pattern using a photolithography method, dry etching and peeling are performed, and the source electrode 15 and the drain electrode 16 As a result, a thin film transistor was obtained (see FIG. 6). The input power during the Mo film formation was 200 W, the gas flow rate was Ar = 50 SCCM, and the film formation pressure was 1.0 Pa. The length between the source / drain electrodes is 20 μm, and the width between the source / drain electrodes is 5 μm.

  In the thin film transistor thus manufactured, peeling between a part of the substrate 10 and the gate insulating layer 13 was visually observed. Further, the adhesion between the resin substrate 10 of the thin film transistor thus manufactured and the gate insulating layer 13 was evaluated according to a JIS-K-5600 (1999) 5-6 adhesion (cross-cut method) test. . As a result, classification 5 [the degree of peeling is classification 4 (the coating film is partially or completely peeled along the edge of the cut, and / or several eyes are partially or completely removed). It was confirmed that the cross-cut portion was clearly affected by over 35% but not over 65%.

Moreover, as a result of measuring the transistor characteristics of the thin film transistor measured using a semiconductor parameter analyzer (SCS4200 manufactured by Keithley), the gate leakage current was 5.0 × 10 ⁻⁵ A, and the transistor characteristics could not be obtained.

(Comparative Example 2)
In Comparative Example 2, a thin film transistor element as shown in FIG. 3, a transistor array substrate as shown in FIG. 4, and an image display device as shown in FIG. 5 were produced.

  First, after forming a Al film on a PEN substrate (thickness 125 μm) as a resin substrate 10 at room temperature using a DC magnetron sputtering apparatus (film thickness 120 nm) and forming a resist pattern using a photolithography method And high temperature water treatment at 100 ° C. for 30 minutes. After the treatment, the resist was peeled off to form the gate electrode 11, the capacitor electrode 17, and the insulating adhesion layer 12. Note that the input power during the Al film formation was 200 W, the gas flow rate was Ar = 50 SCCM, and the film formation pressure was 1.0 Pa.

Next, SiN _x was formed using a plasma CVD apparatus (film thickness: 500 nm) to form the gate insulating layer 13. In forming the gate insulating layer 13, SiH ₄ = 50 SCCM and NH ₃ = 50 SCCM were allowed to flow as source gases, the input power was 300 W, the deposition pressure was 3.0 Pa, and the substrate temperature was 150 ° C.

Next, a metal oxide semiconductor layer 14 made of InGaZnO was formed at room temperature (film thickness 40 nm) using a DC magnetron sputtering apparatus. In the formation of the metal oxide semiconductor layer 14, the input power during the film formation was 100 W, the gas flow rate was Ar = 100 SCCM, O ₂ = ₂ SCCM, and the film formation pressure was 1.0 Pa.

  Finally, Mo is formed at room temperature (film thickness: 80 nm) using a DC magnetron sputtering apparatus, a resist pattern is formed using a photolithography method, dry etching and peeling are performed, and the source electrode 15 and the drain electrode are formed. 16 to form a thin film transistor (see FIG. 3). The input power during the Mo film formation was 200 W, the gas flow rate was Ar = 50 SCCM, and the film formation pressure was 1.0 Pa. The length between the source / drain electrodes is 20 μm, and the width between the source / drain electrodes is 5 μm.

  The adhesion between the resin substrate 10 and the gate insulating layer 13 through the insulating adhesion layer 12 of the thin film transistor thus manufactured is determined according to JIS-K-5600 (1999) 5-6 adhesion (cross-cut method). According to the test, the adhesion between the gate insulating layer 13 and the resin substrate 10 was evaluated. As a result, it showed good adhesion applicable to classification 0 (the edge of the cut was completely smooth and there was no peeling of any lattice eye).

In addition, the cross cut was performed using a 1 mm gap cutter guide. The transistor characteristics of a thin film transistor measured using a semiconductor parameter analyzer (SCS4200 manufactured by Keithley) with a gate voltage of −10 V to +20 V and a drain voltage of 5 V are as follows: mobility 7 cm ² / Vs When the voltage was applied, the ON / OFF ratio was 5 digits, and the gate leakage current at a gate voltage of 20 V was 3.8 × 10 ⁻¹⁰ A, indicating good transistor characteristics.

Next, the source / drain electrodes are formed by the manufacturing method described above, and the sealing layer 18 made of SiO _x , the interlayer insulating layer 19 made of polymer, and the pixel electrode 20 made of ITO are formed on the thin film transistor, and FIG. A thin film transistor array substrate 21 as shown was obtained.

  The thin film transistor array substrate 21 has a size of one pixel of 125 μm × 125 μm and 480 × 640 pixels.

  Next, when an image display device as shown in FIG. 5 is manufactured with the electrophoretic medium 22 sandwiched between the transistor array substrate 21 and the counter electrode 23 and driven, electrical mutual between adjacent pixels is achieved. An effect occurred, and good driving was not possible.

(Comparative Example 3)
In Comparative Example 3, a thin film transistor as shown in FIG. 3, a thin film transistor array substrate as shown in FIG. 4, and an image display device as shown in FIG. 5 were produced.

  First, after forming a Al film on a PEN substrate (thickness: 125 μm) as a resin substrate 10 at room temperature using a DC magnetron sputtering apparatus (film thickness: 100 nm) and forming a resist pattern using a photolithography method And high temperature water treatment at 80 ° C. for 30 minutes. After the treatment, the resist was peeled off to form the gate electrode 11, the capacitor electrode 17, and the insulating adhesion layer 12. Note that the input power during the Al film formation was 200 W, the gas flow rate was Ar = 50 SCCM, and the film formation pressure was 1.0 Pa.

Next, SiN _x was formed using a plasma CVD apparatus (film thickness: 500 nm) to form the gate insulating layer 13. In forming the gate insulating layer 13, SiH ₄ = 50 SCCM and NH ₃ = 50 SCCM were supplied as source gases, the input power was 300 W, the deposition pressure was 3.0 Pa, and the substrate temperature was 150 ° C.

Next, a metal oxide semiconductor layer 14 made of InGaZnO was formed at room temperature (40 nm) using a DC magnetron sputtering apparatus. In the formation of the metal oxide semiconductor layer 14, the input power during the film formation was 100 W, the gas flow rate was Ar = 100 SCCM, O ₂ = ₂ SCCM, and the film formation pressure was 1.0 Pa.

  Finally, Mo is formed at room temperature (film thickness: 80 nm) using a DC magnetron sputtering apparatus, a resist pattern is formed using a photolithography method, dry etching and peeling are performed, and the source electrode 15 and the drain electrode are formed. 16 to form a thin film transistor (see FIG. 3). The input power during the Mo film formation was 200 W, the gas flow rate was Ar = 50 SCCM, and the film formation pressure was 1.0 Pa. The length between the source / drain electrodes is 20 μm, and the width between the source / drain electrodes is 5 μm.

  The adhesion between the resin substrate 10 and the gate insulating layer 13 through the insulating adhesion layer 12 of the thin film transistor thus manufactured is determined according to JIS-K-5600 (1999) 5-6 adhesion (cross-cut method). Evaluation was performed according to the test. As a result, it showed good adhesion applicable to classification 0 (the edge of the cut was completely smooth and there was no peeling of any lattice eye).

In addition, the cross cut was performed using a 1 mm gap cutter guide. The transistor characteristics of the thin film transistor measured using a semiconductor parameter analyzer (SCS4200 manufactured by Keithley) with a gate voltage of −10 V to +20 V and a drain voltage of 5 V are as follows: mobility 6 cm ² / Vs When the voltage was applied, the ON / OFF ratio was 5 digits, and the gate leakage current at a gate voltage of 20 V was 3.6 × 10 ⁻¹⁰ A, indicating good transistor characteristics.

Next, the source / drain electrodes are formed by the manufacturing method described above, and the sealing layer 18 made of SiO _x , the interlayer insulating layer 19 made of polymer, and the pixel electrode 20 made of ITO are formed on the thin film transistor, and FIG. A thin film transistor array substrate 21 as shown was obtained.

  The thin film transistor array substrate 21 has a size of one pixel of 125 μm × 125 μm and 480 × 640 pixels.

  Next, when an image display device as shown in FIG. 5 is manufactured with the electrophoretic medium 22 sandwiched between the transistor array substrate 21 and the counter electrode 23 and driven, electrical mutual between adjacent pixels is achieved. An effect occurred, and good driving was not possible.

  The thin film transistor and the manufacturing method thereof according to the present invention and the image display device using the thin film transistor can be used as a switching element for flexible electronic paper, LCD, organic EL display, IC tag and the like.

DESCRIPTION OF SYMBOLS 10 Resin substrate 11 Gate electrode 12 Insulating adhesion layer 13 Gate insulating layer 14 Metal oxide semiconductor layer 15 Source electrode 16 Drain electrode 17 Capacitor electrode 18 Sealing layer 19 Interlayer insulating layer 20 Pixel electrode 21 Transistor array substrate 22 Electrophoretic medium 23 Counter electrode

Claims (11)

A bottom gate type thin film transistor,
A resin substrate;
A gate electrode and an insulating adhesion layer provided on the same surface of the resin substrate;
A gate insulating layer provided on the gate electrode and the insulating adhesion layer, at least,
The gate electrode includes a metal;
The thin film transistor according to claim 1, wherein the insulating adhesion layer includes a metal oxyhydroxide contained in the gate electrode.   The thin film transistor according to claim 1, wherein the metal is a metal containing Al.   The thin film transistor according to claim 1 or 2, wherein the gate electrode has a thickness of 10 nm to 100 nm.   3. The thin film transistor according to claim 1, wherein the gate insulating layer includes at least one compound of silicon oxide, silicon nitride, and silicon oxynitride. A metal oxide semiconductor layer on the gate insulating layer;
The thin film transistor according to claim 1, wherein the metal oxide semiconductor layer includes at least one element of In, Zn, and Ga. A method of manufacturing a bottom-gate thin film transistor,
The thin film transistor
A resin substrate;
A gate electrode and an insulating adhesion layer provided on the same surface of the resin substrate;
A gate insulating layer provided on the gate electrode and the insulating adhesion layer, at least,
The manufacturing method includes:
A metal film forming step of forming a film containing a metal on the resin substrate;
A resist coating step of covering a portion to be the gate electrode on the resin substrate with a resist;
A high-temperature water treatment step of treating the resin substrate with high-temperature water;
And a oxyhydration step of oxyhydrating a film containing the metal on the resin substrate that is not covered with the resist.   The method of manufacturing a thin film transistor according to claim 6, wherein the metal is a metal containing Al.   8. The high temperature water treatment process according to claim 6 or 7, wherein the gate electrode is formed in a portion covered with the resist and the insulating adhesive layer is formed in a portion not covered with the resist. The manufacturing method of the thin-film transistor of description.   8. The method of manufacturing a thin film transistor according to claim 6, wherein a temperature at the time of the high temperature water treatment in the high temperature water treatment step is 100 ° C. or more and 180 ° C. or less.   6. An image display device comprising the thin film transistor array according to claim 1 and an image display medium.   The image display device according to claim 10, wherein the image display medium is an electrophoretic type.

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