KR20090012136A - 반도체 장치 - Google Patents
반도체 장치 Download PDFInfo
- Publication number
- KR20090012136A KR20090012136A KR1020080072364A KR20080072364A KR20090012136A KR 20090012136 A KR20090012136 A KR 20090012136A KR 1020080072364 A KR1020080072364 A KR 1020080072364A KR 20080072364 A KR20080072364 A KR 20080072364A KR 20090012136 A KR20090012136 A KR 20090012136A
- Authority
- KR
- South Korea
- Prior art keywords
- wiring
- layer
- standard cell
- power supply
- region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JPJP-P-2007-00193580 | 2007-07-25 | ||
| JP2007193580 | 2007-07-25 | ||
| JPJP-P-2008-00137063 | 2008-05-26 | ||
| JP2008137063A JP5293939B2 (ja) | 2007-07-25 | 2008-05-26 | 半導体装置 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR20090012136A true KR20090012136A (ko) | 2009-02-02 |
Family
ID=40477685
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020080072364A Ceased KR20090012136A (ko) | 2007-07-25 | 2008-07-24 | 반도체 장치 |
Country Status (4)
| Country | Link |
|---|---|
| JP (1) | JP5293939B2 (enExample) |
| KR (1) | KR20090012136A (enExample) |
| CN (1) | CN101388391B (enExample) |
| TW (1) | TWI437665B (enExample) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101429396B1 (ko) * | 2013-01-28 | 2014-08-11 | 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 | 표준 셀 디자인 레이아웃 |
| KR20150145178A (ko) * | 2014-06-18 | 2015-12-29 | 에이알엠 리미티드 | 집적회로 내부의 전력망 도체 배치 |
| KR20150145181A (ko) * | 2014-06-18 | 2015-12-29 | 에이알엠 리미티드 | 집적회로 내부의 비아 배치 |
Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5552775B2 (ja) | 2009-08-28 | 2014-07-16 | ソニー株式会社 | 半導体集積回路 |
| JP5685457B2 (ja) | 2010-04-02 | 2015-03-18 | ルネサスエレクトロニクス株式会社 | 半導体集積回路装置 |
| WO2013018589A1 (ja) * | 2011-08-01 | 2013-02-07 | 国立大学法人電気通信大学 | 半導体集積回路装置 |
| CN103546146B (zh) * | 2013-09-24 | 2016-03-02 | 中国科学院微电子研究所 | 抗单粒子瞬态脉冲cmos电路 |
| JP5776802B2 (ja) * | 2014-02-14 | 2015-09-09 | ソニー株式会社 | 半導体集積回路 |
| US11120190B2 (en) * | 2017-11-21 | 2021-09-14 | Advanced Micro Devices, Inc. | Metal zero power ground stub route to reduce cell area and improve cell placement at the chip level |
| WO2020044438A1 (ja) * | 2018-08-28 | 2020-03-05 | 株式会社ソシオネクスト | 半導体集積回路装置 |
| CN112771655B (zh) * | 2018-09-28 | 2024-08-20 | 株式会社索思未来 | 半导体集成电路装置以及半导体封装件构造 |
| US11488947B2 (en) * | 2019-07-29 | 2022-11-01 | Tokyo Electron Limited | Highly regular logic design for efficient 3D integration |
| JP7525802B2 (ja) * | 2020-03-27 | 2024-07-31 | 株式会社ソシオネクスト | 半導体集積回路装置 |
| CN114492283B (zh) * | 2020-11-11 | 2025-08-01 | Oppo广东移动通信有限公司 | 配置芯片的方法及装置、设备、存储介质 |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5923060A (en) * | 1996-09-27 | 1999-07-13 | In-Chip Systems, Inc. | Reduced area gate array cell design based on shifted placement of alternate rows of cells |
| JP3672788B2 (ja) * | 2000-02-24 | 2005-07-20 | 松下電器産業株式会社 | 半導体装置のセルレイアウト構造およびレイアウト設計方法 |
| JP3718687B2 (ja) * | 2002-07-09 | 2005-11-24 | 独立行政法人 宇宙航空研究開発機構 | インバータ、半導体論理回路、スタティックランダムアクセスメモリ、及びデータラッチ回路 |
| JP4820542B2 (ja) * | 2004-09-30 | 2011-11-24 | パナソニック株式会社 | 半導体集積回路 |
-
2008
- 2008-05-26 JP JP2008137063A patent/JP5293939B2/ja not_active Expired - Fee Related
- 2008-07-14 TW TW097126596A patent/TWI437665B/zh not_active IP Right Cessation
- 2008-07-24 KR KR1020080072364A patent/KR20090012136A/ko not_active Ceased
- 2008-07-25 CN CN2008101769097A patent/CN101388391B/zh active Active
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101429396B1 (ko) * | 2013-01-28 | 2014-08-11 | 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 | 표준 셀 디자인 레이아웃 |
| US8813016B1 (en) | 2013-01-28 | 2014-08-19 | Taiwan Semiconductor Manufacturing Company Limited | Multiple via connections using connectivity rings |
| US9213795B2 (en) | 2013-01-28 | 2015-12-15 | Taiwan Semiconductor Manufacturing Company Limited | Multiple via connections using connectivity rings |
| KR20150145178A (ko) * | 2014-06-18 | 2015-12-29 | 에이알엠 리미티드 | 집적회로 내부의 전력망 도체 배치 |
| KR20150145181A (ko) * | 2014-06-18 | 2015-12-29 | 에이알엠 리미티드 | 집적회로 내부의 비아 배치 |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2009049370A (ja) | 2009-03-05 |
| JP5293939B2 (ja) | 2013-09-18 |
| TW200915488A (en) | 2009-04-01 |
| CN101388391A (zh) | 2009-03-18 |
| CN101388391B (zh) | 2012-07-11 |
| TWI437665B (zh) | 2014-05-11 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PA0109 | Patent application |
Patent event code: PA01091R01D Comment text: Patent Application Patent event date: 20080724 |
|
| PG1501 | Laying open of application | ||
| N231 | Notification of change of applicant | ||
| PN2301 | Change of applicant |
Patent event date: 20100927 Comment text: Notification of Change of Applicant Patent event code: PN23011R01D |
|
| A201 | Request for examination | ||
| PA0201 | Request for examination |
Patent event code: PA02012R01D Patent event date: 20130719 Comment text: Request for Examination of Application Patent event code: PA02011R01I Patent event date: 20080724 Comment text: Patent Application |
|
| E902 | Notification of reason for refusal | ||
| PE0902 | Notice of grounds for rejection |
Comment text: Notification of reason for refusal Patent event date: 20140512 Patent event code: PE09021S01D |
|
| E601 | Decision to refuse application | ||
| PE0601 | Decision on rejection of patent |
Patent event date: 20140819 Comment text: Decision to Refuse Application Patent event code: PE06012S01D Patent event date: 20140512 Comment text: Notification of reason for refusal Patent event code: PE06011S01I |