TWI437665B - 半導體裝置 - Google Patents
半導體裝置 Download PDFInfo
- Publication number
- TWI437665B TWI437665B TW097126596A TW97126596A TWI437665B TW I437665 B TWI437665 B TW I437665B TW 097126596 A TW097126596 A TW 097126596A TW 97126596 A TW97126596 A TW 97126596A TW I437665 B TWI437665 B TW I437665B
- Authority
- TW
- Taiwan
- Prior art keywords
- wiring
- layer
- layer wiring
- lower layer
- upper layer
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2007193580 | 2007-07-25 | ||
| JP2008137063A JP5293939B2 (ja) | 2007-07-25 | 2008-05-26 | 半導体装置 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW200915488A TW200915488A (en) | 2009-04-01 |
| TWI437665B true TWI437665B (zh) | 2014-05-11 |
Family
ID=40477685
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW097126596A TWI437665B (zh) | 2007-07-25 | 2008-07-14 | 半導體裝置 |
Country Status (4)
| Country | Link |
|---|---|
| JP (1) | JP5293939B2 (enExample) |
| KR (1) | KR20090012136A (enExample) |
| CN (1) | CN101388391B (enExample) |
| TW (1) | TWI437665B (enExample) |
Families Citing this family (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5552775B2 (ja) | 2009-08-28 | 2014-07-16 | ソニー株式会社 | 半導体集積回路 |
| JP5685457B2 (ja) | 2010-04-02 | 2015-03-18 | ルネサスエレクトロニクス株式会社 | 半導体集積回路装置 |
| JPWO2013018589A1 (ja) * | 2011-08-01 | 2015-03-05 | 国立大学法人電気通信大学 | 半導体集積回路装置 |
| US8813016B1 (en) | 2013-01-28 | 2014-08-19 | Taiwan Semiconductor Manufacturing Company Limited | Multiple via connections using connectivity rings |
| CN103546146B (zh) * | 2013-09-24 | 2016-03-02 | 中国科学院微电子研究所 | 抗单粒子瞬态脉冲cmos电路 |
| JP5776802B2 (ja) * | 2014-02-14 | 2015-09-09 | ソニー株式会社 | 半導体集積回路 |
| US9454633B2 (en) * | 2014-06-18 | 2016-09-27 | Arm Limited | Via placement within an integrated circuit |
| US9653413B2 (en) * | 2014-06-18 | 2017-05-16 | Arm Limited | Power grid conductor placement within an integrated circuit |
| US11120190B2 (en) * | 2017-11-21 | 2021-09-14 | Advanced Micro Devices, Inc. | Metal zero power ground stub route to reduce cell area and improve cell placement at the chip level |
| CN112567507B (zh) | 2018-08-28 | 2024-07-05 | 株式会社索思未来 | 半导体集成电路装置 |
| JP7307355B2 (ja) * | 2018-09-28 | 2023-07-12 | 株式会社ソシオネクスト | 半導体集積回路装置および半導体パッケージ構造 |
| US11488947B2 (en) * | 2019-07-29 | 2022-11-01 | Tokyo Electron Limited | Highly regular logic design for efficient 3D integration |
| JP7525802B2 (ja) * | 2020-03-27 | 2024-07-31 | 株式会社ソシオネクスト | 半導体集積回路装置 |
| CN114492283B (zh) * | 2020-11-11 | 2025-08-01 | Oppo广东移动通信有限公司 | 配置芯片的方法及装置、设备、存储介质 |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5923060A (en) * | 1996-09-27 | 1999-07-13 | In-Chip Systems, Inc. | Reduced area gate array cell design based on shifted placement of alternate rows of cells |
| JP3672788B2 (ja) * | 2000-02-24 | 2005-07-20 | 松下電器産業株式会社 | 半導体装置のセルレイアウト構造およびレイアウト設計方法 |
| JP3718687B2 (ja) * | 2002-07-09 | 2005-11-24 | 独立行政法人 宇宙航空研究開発機構 | インバータ、半導体論理回路、スタティックランダムアクセスメモリ、及びデータラッチ回路 |
| JP4820542B2 (ja) * | 2004-09-30 | 2011-11-24 | パナソニック株式会社 | 半導体集積回路 |
-
2008
- 2008-05-26 JP JP2008137063A patent/JP5293939B2/ja not_active Expired - Fee Related
- 2008-07-14 TW TW097126596A patent/TWI437665B/zh not_active IP Right Cessation
- 2008-07-24 KR KR1020080072364A patent/KR20090012136A/ko not_active Ceased
- 2008-07-25 CN CN2008101769097A patent/CN101388391B/zh active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN101388391A (zh) | 2009-03-18 |
| JP5293939B2 (ja) | 2013-09-18 |
| KR20090012136A (ko) | 2009-02-02 |
| JP2009049370A (ja) | 2009-03-05 |
| TW200915488A (en) | 2009-04-01 |
| CN101388391B (zh) | 2012-07-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI437665B (zh) | 半導體裝置 | |
| US8063415B2 (en) | Semiconductor device | |
| US11195794B2 (en) | Stacked integrated circuit devices including a routing wire | |
| JP7415176B2 (ja) | 半導体集積回路装置 | |
| US11205645B2 (en) | Semiconductor device | |
| US10943923B2 (en) | Integrated circuits and semiconductor device including standard cell | |
| TWI835908B (zh) | 標準單元 | |
| JP7529121B2 (ja) | 半導体装置 | |
| JP7639871B2 (ja) | 半導体装置 | |
| JP7315016B2 (ja) | 半導体装置 | |
| CN110634860B (zh) | 半导体装置 | |
| US20240274510A1 (en) | Stacked integrated circuit devices | |
| CN114586144A (zh) | 半导体装置 | |
| JP2017069513A (ja) | 半導体装置およびその製造方法 | |
| KR102650199B1 (ko) | 반도체 소자 | |
| KR20240124160A (ko) | 후면 배선 패턴을 포함하는 집적 회로 | |
| WO2025169464A1 (ja) | 半導体装置 | |
| WO2025169463A1 (ja) | 半導体装置 | |
| WO2025181960A1 (ja) | 半導体装置 | |
| JP2009158728A (ja) | 半導体装置 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MM4A | Annulment or lapse of patent due to non-payment of fees |