CN101388391B - 半导体装置 - Google Patents

半导体装置 Download PDF

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Publication number
CN101388391B
CN101388391B CN2008101769097A CN200810176909A CN101388391B CN 101388391 B CN101388391 B CN 101388391B CN 2008101769097 A CN2008101769097 A CN 2008101769097A CN 200810176909 A CN200810176909 A CN 200810176909A CN 101388391 B CN101388391 B CN 101388391B
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CN
China
Prior art keywords
wiring
layer
layer wiring
boundary
electrically connected
Prior art date
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Active
Application number
CN2008101769097A
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English (en)
Chinese (zh)
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CN101388391A (zh
Inventor
津田信浩
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Electronics Corp
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Renesas Electronics Corp
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Publication date
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Publication of CN101388391A publication Critical patent/CN101388391A/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
CN2008101769097A 2007-07-25 2008-07-25 半导体装置 Active CN101388391B (zh)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
JP2007193580 2007-07-25
JP2007-193580 2007-07-25
JP2007193580 2007-07-25
JP2008-137063 2008-05-26
JP2008137063A JP5293939B2 (ja) 2007-07-25 2008-05-26 半導体装置
JP2008137063 2008-05-26

Publications (2)

Publication Number Publication Date
CN101388391A CN101388391A (zh) 2009-03-18
CN101388391B true CN101388391B (zh) 2012-07-11

Family

ID=40477685

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2008101769097A Active CN101388391B (zh) 2007-07-25 2008-07-25 半导体装置

Country Status (4)

Country Link
JP (1) JP5293939B2 (enExample)
KR (1) KR20090012136A (enExample)
CN (1) CN101388391B (enExample)
TW (1) TWI437665B (enExample)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5552775B2 (ja) 2009-08-28 2014-07-16 ソニー株式会社 半導体集積回路
JP5685457B2 (ja) 2010-04-02 2015-03-18 ルネサスエレクトロニクス株式会社 半導体集積回路装置
WO2013018589A1 (ja) * 2011-08-01 2013-02-07 国立大学法人電気通信大学 半導体集積回路装置
US8813016B1 (en) 2013-01-28 2014-08-19 Taiwan Semiconductor Manufacturing Company Limited Multiple via connections using connectivity rings
CN103546146B (zh) * 2013-09-24 2016-03-02 中国科学院微电子研究所 抗单粒子瞬态脉冲cmos电路
JP5776802B2 (ja) * 2014-02-14 2015-09-09 ソニー株式会社 半導体集積回路
US9653413B2 (en) * 2014-06-18 2017-05-16 Arm Limited Power grid conductor placement within an integrated circuit
US9454633B2 (en) * 2014-06-18 2016-09-27 Arm Limited Via placement within an integrated circuit
US11120190B2 (en) * 2017-11-21 2021-09-14 Advanced Micro Devices, Inc. Metal zero power ground stub route to reduce cell area and improve cell placement at the chip level
WO2020044438A1 (ja) * 2018-08-28 2020-03-05 株式会社ソシオネクスト 半導体集積回路装置
CN112771655B (zh) * 2018-09-28 2024-08-20 株式会社索思未来 半导体集成电路装置以及半导体封装件构造
US11488947B2 (en) * 2019-07-29 2022-11-01 Tokyo Electron Limited Highly regular logic design for efficient 3D integration
JP7525802B2 (ja) * 2020-03-27 2024-07-31 株式会社ソシオネクスト 半導体集積回路装置
CN114492283B (zh) * 2020-11-11 2025-08-01 Oppo广东移动通信有限公司 配置芯片的方法及装置、设备、存储介质

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5923060A (en) * 1996-09-27 1999-07-13 In-Chip Systems, Inc. Reduced area gate array cell design based on shifted placement of alternate rows of cells

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3672788B2 (ja) * 2000-02-24 2005-07-20 松下電器産業株式会社 半導体装置のセルレイアウト構造およびレイアウト設計方法
JP3718687B2 (ja) * 2002-07-09 2005-11-24 独立行政法人 宇宙航空研究開発機構 インバータ、半導体論理回路、スタティックランダムアクセスメモリ、及びデータラッチ回路
JP4820542B2 (ja) * 2004-09-30 2011-11-24 パナソニック株式会社 半導体集積回路

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5923060A (en) * 1996-09-27 1999-07-13 In-Chip Systems, Inc. Reduced area gate array cell design based on shifted placement of alternate rows of cells

Also Published As

Publication number Publication date
JP2009049370A (ja) 2009-03-05
JP5293939B2 (ja) 2013-09-18
TW200915488A (en) 2009-04-01
CN101388391A (zh) 2009-03-18
TWI437665B (zh) 2014-05-11
KR20090012136A (ko) 2009-02-02

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C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
ASS Succession or assignment of patent right

Owner name: RENESAS ELECTRONICS CORPORATION

Free format text: FORMER OWNER: RENESAS TECHNOLOGY CORP.

Effective date: 20101019

C41 Transfer of patent application or patent right or utility model
COR Change of bibliographic data

Free format text: CORRECT: ADDRESS; FROM: TOKYO TO, JAPAN TO: KAWASAKI CITY, KANAGAWA PREFECTURE, JAPAN

TA01 Transfer of patent application right

Effective date of registration: 20101019

Address after: Kawasaki, Kanagawa, Japan

Applicant after: Renesas Electronics Corporation

Address before: Tokyo, Japan, Japan

Applicant before: Renesas Technology Corp.

C14 Grant of patent or utility model
GR01 Patent grant
CP02 Change in the address of a patent holder
CP02 Change in the address of a patent holder

Address after: Tokyo, Japan, Japan

Patentee after: Renesas Electronics Corporation

Address before: Kawasaki, Kanagawa, Japan

Patentee before: Renesas Electronics Corporation