TW200915488A - Semiconductor device - Google Patents

Abstract

CMOS inverters are included in a standard cell. Power supply lines are electrically connected to CMOS inverters, and include lower layer interconnects and upper layer interconnect. Lower layer interconnects extend along a boundary of standard cells adjacent to each other and on the boundary. Upper layer interconnects are positioned more inside in standard cell than lower layer interconnects, as viewed from a plane. CMOS inverters are electrically connected through upper layer interconnects to lower layer interconnects. Thus, a semiconductor device is obtained that can achieve both higher speeds and higher integration.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a plurality of standard cells arranged in series. [Prior Art] In recent years, in the SOC (System On Chip), the layout of the standard ceU library is generally used due to the large-scale circuit design. In addition, with the high functionality and high performance of s〇c, the standard single-pair library is required to be highly integrated and high-speed. On the other hand, as the speed increases, the current consumption increases. Therefore, since IR — Dr〇p (current 丨 flows in a certain path 'when the path is the resistance value R, it is generated at both ends of the path by (10). Deterioration of characteristics caused by power supply noise such as potential difference may become a big problem. In the construction of the prior art, the standard unit of the standard unit database is formed as a component of the force month b. For example, cM〇S (Complementary Metal Oxide)

Semiconductor, Complementary Metal Oxide Semiconductor Inverter. In this configuration, a P-channel MOS transistor (hereinafter referred to as a pMOS electric B-body) is formed on the surface of the n-type well region, and an n-channel transistor (hereinafter referred to as an nMOS transistor) is formed on the surface of the p-type well region. . Electromagnets (_wiring, GND wiring) are connected to each of the pM〇s transistor and the nM〇s transistor. Each of the n-lines is in contact with the substrate, and (4) the substrate has a fixed potential and is commonly provided in the functional elements of each standard cell. Because the current consumption of the standard unit is increased with the speed of the standard unit database, the current flowing through the power line is also increased. In addition, the power lines shared by the standard cells flow into the currents of a plurality of standard cells. Therefore, since the current value flowing in the power supply line becomes large, it is necessary to consider the influence of IR-Drop. , the power line 1R-Dr〇P is related to the resistance value of the power line, and the smaller the resistance value is IR—

The drop of f is 彳 彳. The countermeasure against the prior art is to make the line width of the power line larger. On the other hand, with the high integration of the standard cell database, two CMOS transistors having different B-nodes are arranged in i standard cells. In this case, the prior art has been carried out by arranging four transistors in a top view and arranging them in a vertical direction to achieve a high integration of standard cells. In such a method, the wiring between the connection transistors and the wiring for connecting the transistor and the power supply line become large, and the wiring arrangement tends to become complicated. Further, the prior art configuration has a plurality of standard unit arrangements, for example, disclosed in Japanese Laid-Open Patent Publication No. 2000-223575. In this publication, it is disclosed that a ti 1st power supply line (3VDD1, 3VSS1) and a third layer power supply line (3VDD3, 3VSS3) parallel thereto are provided, and a signal line (3S2) is passed through the second layer for use in the third layer. The power line reinforces the first layer power line without placing a limit on the configuration of the second layer. - However, in the standard cell structure of the prior art in the above-described manner, in order to realize a high-integrated and high-speed standard cell, it is necessary to simultaneously achieve a power supply for speeding up: a structure that is thickened, and a structure that is high-integrated. It is difficult to configure a plurality of transistors in the longitudinal direction. The reason is that since the power supply line is made thicker, it is necessary to secure the connection fabric 97126596 c 200915488 line constituting the respective NMOS of the inverter and the _S transistor, and to connect the power supply line to the electric crystal [invention Content] It is difficult to separate the wiring parts of the body. SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and it is an integrated semiconductor device. It is to provide a standard that can be both high-speed and high-speed at the same time, and (four) is arranged in multiples. 2, it has a wealthy component and an electric tree. Wei components are included in the standard. The power cord is electrically connected to the functional components and has the underlying wiring and the upper wiring. The lower layer has a portion extending along the standard unit boundary adjacent to each other and extending in the realm. The upper layer wiring is in the top view w + and has a portion located in the standard cell _ than the lower layer wiring. The Wei component is connected to the lower wiring via the feed line Wei. According to the semiconductor device of the embodiment of the present invention, the power supply line is separated into the lower layer wiring and the upper layer wiring, and when compared with the case where the power source line is a single layer, the current path can be increased, so that the speed can be increased. In addition, since the line width of the power supply line does not need to be increased, the electric path can be increased, so that high integration can be achieved. In addition, the lower layer wiring extends along the boundary of the standard unit, so the lower layer wiring can be shared between adjacent standard cells. In this way, since the lower layer wiring is formed in each of the adjacent standard cells, high integration can be achieved. In addition, since the functional element is connected to the lower layer wiring via the upper layer wiring, it is not necessary to extend the layer wiring under the standard cell boundary toward the central portion of the standard unit of the position of the Wei element 97126596 200915488. In this manner, since a space is formed in a portion where the lower layer wiring is extended toward the central portion of the standard cell, other wirings and the like can be disposed in the space (4), and high integration can be achieved. By using this financial model, you can get a high-speed and high-level semiconductor device. The above and other objects, features, aspects and advantages of the present invention will become apparent from (Embodiment) Hereinafter, embodiments of the present invention will be described based on the drawings. (Embodiment 1) Referring to Fig. 1, a semiconductor device (e.g., a semiconductor wafer) 50 mainly has a standard cell region 51 on its surface; I/0 (I_t/0utput, input/round-out) cell region 52, which is disposed in the standard The periphery of the unit area 51; and a spacer (not shown) are used for input and output with the outside. 〇 The standard cell area 51 has a plurality of standard cells 51a arranged in a matrix (array). In the standard cell area 51, a cPU (Central Processing Unit), a RAM (Random Access Memory), and a 'FIF0 (First) are formed in the standard cell area 51. In First — Out, first in, first out, scSI (Small Computer System Interface), s〇G (Sea Of)

Gate 'standard brake electronic components) and so on. Referring to Fig. 2, the circuit of the functional elements formed in the standard unit 51a has, for example, 97126596 7 200915488

TriState (three-state) uses a part of the circuit of the buffer, with an output section and a driver section. The output section is composed of, for example, a CMOS inverter composed of a pMOS transistor PT1 and an nMOS transistor NT1. The driver portion includes, for example, a CMOS inverter composed of a pm〇s transistor PT2 and an nMOS transistor NT2, and a CMOS inverter composed of a pMOS transistor PT3 and an nMOS transistor NT3. The output of the CMOS inverter composed of the pMOS transistor PT2 and the nMOS transistor NT2 is input to the nMOS transistor NT1 of the output section. Further, the output of the CMOS inverter composed of the pMOS transistor PT3 and the nMOS transistor NT3 is input to the pMOS transistor PT1 of the output section. When the circuit inputs "High" to the two CMOS inverters of the driver section, "High" is output from the CMOS inverter of the output section. Further, when "Low" is input to the two CMOS inverters of the driver section, "Low" is output from the CM 〇 S inverter of the output section. In addition, when a "Low" is input to a CMOS inverter composed of a pMOS transistor PT3 and an nM〇S transistor NT3, a CMOS composed of a 〇pMOS electrocardiograph DTn^ body PT2 and an nM〇S transistor NT2 is formed. When the inverter inputs "High", the output of the CMOS inverter of the output section becomes a floating sorrow. It becomes the high impedance (high impedance) of the U. u. 丨明. , FIG. 3 and FIG. 4, forming a P-type well region 1 on the surface of the semiconductor substrate, and a surface in the ^P-type well region ,, selectively forming an n-type well region 2. In the ρ-type well ^ p 士七The surface of °° or 1 'forms nMOS transistors m, ΝΤ2, ΝΤ3. On the surface of the n-type well ^ field ^, pMOS transistors ΡΤ1, ΡΤ2, ΡΤ3 are formed. 卜 along the longitudinal direction of the standard cell 51a (Fig. In the boundary of the Y-direction of the 3rd direction, the surface of the lower side of the Y-direction is the surface of the cavity in the mouth-shaped well region, and the + region 15 extending in the lateral direction (the X direction in Fig. 3) is formed. In addition, along the other side of the realm of the standard unit 51a (the gamma direction in Fig. 3) - the Y direction in . On the surface in the n-type well region 2, the n+ region 25 extending in the lateral direction (X direction in Fig. 3) is formed. To form a region of a plurality of MOS transistors, p+ region 15 and Each of the regions 25 is electrically isolated from each other, and an element isolation region 3 composed of, for example, 〇STI (Shall〇w Trench Isolation) is formed on the surface of the semiconductor substrate. The STI is formed by a trench provided on the surface of the semiconductor substrate, and It is filled with an insulating filler filled in the groove. Each of the nMOS transistors ΝΠ, ΝΤ2, ΝΤ3 has a drain region Ua and a source region lib, a gate insulating layer 12', and a gate electrode layer 13. The source region lib is composed of impurity regions of the n-type, and is formed at a distance from each other in the p-type well region. The gate electrode layer 13 is formed in the gated region 11a and the source region lib via the gate insulating layer 12. On the region of the clip, each of the PM0S transistors PT, PT2, PT3 has a non-polar region 21 & and a source region 21b 'gate insulating layer 22' and a gate electrode layer 23. The gate region ... and the source region 211) are P Type of impurity region, in the n-type well region 2 The surface 'forms a distance from each other.' The pole layer 23 is formed on the region sandwiched by the gate region 21a and the source region 21b via the gate insulating layer 22. The gate electrode layer 13 of the nMOS transistor NT2 and the _s transistor pm The electrode layer 23 is formed of a common conductive layer and electrically connected to each other. In addition, the gate electrode layer 13 of the crystal NT3 and the gate electrode layer 23 of the pMOS transistor PT3 are formed by a common conductive layer and electrically connected to each other. . The laminated interlayer insulating layers 31A and 31B formed on the surface of the semiconductor substrate are covered so as to cover the respective MOS transistors NT1 to NT3 and PT1 to PT3. The interlayer insulating layer 31A is formed, for example, of a TEOS (Tetra_Ethyl - 〇rth〇~& gamma, tetraethoxy decane) oxide film, and the interlayer insulating layer 31B is, for example, Si〇c, MSQ (Methyl Silses - Quioxane, 曱 倍 倍Oxane or the like is formed. 〇 In the interlayer insulating layer _, the wiring trench 31b which reaches the interlayer insulating layer 31A from the upper surface thereof is formed, and the interlayer insulating layer 3531A is formed with a contact hole 31a which reaches the semiconductor substrate from the bottom of the wiring trench. Each of the wiring layers 32a to 32h which is made of, for example, a CuAl alloy (the A1 content is, for example, about 1%) is formed in each of the above-described wiring trenches. Further, inside each of the contact holes 31a described above, a plug layer made of, for example, a crane (w) is embedded. A barrier metal layer (not shown) is formed on the side and the bottom surface of the contact hole 31a. The barrier metal layer is located between the plug layer and the interlayer insulating layer W, and between the plug layer and the semi-conducting plate. The wall metal has a laminated structure of an example (Τι) and titanium nitride (TiN). A barrier metal layer (not shown) is also formed on the side surface and the bottom surface of the wiring trench 31b. The barrier metal layer is located between the wiring layer 32_ and the interlayer insulating layer, between the wiring layers 32a to 32h and the plug layer, and between the wiring layers 32a to 32h and the interlayer insulating layer 31A. The barrier metal layer is composed, for example, of the group 97) 97126596, 200915488. An #etch barrier layer (not shown) made of, for example, SiCN is formed between the interlayer insulating layer 31A and the interlayer insulating layer 31B. The drain region 1 la of the _S transistor NT1 and the drain region 21a of the pMOS transistor PT1 are electrically connected to each other by the wiring layer 32e. Further, the drain region 32 of the nMOS transistor NT2 and the pm?S transistor PT2 are made by the wiring layer 32c.

The drain regions 21a are electrically connected to each other and electrically connected to the gate electrode layer 13 of the nM〇s transistor NT1. Further, the drain region 21a of the nMOS transistor NT3 and the drain region 21a of the pMOS transistor PT3 are electrically connected to each other by the wiring layer 32d, and are electrically connected to the gate electrode layer 23 of the pMOS transistor PT1. These wiring layers 32c and 32d correspond to signal lines for transmitting signals from the driver unit to the output section. Further, the wiring layer 32a extends along one of the vertical direction boundaries of the standard cell 51a (the boundary of the lower side in the γ direction in Fig. 3), and extends in the lateral direction (X direction in Fig. 3) in this boundary. Further, the wiring layer 32b extends along the other side of the standard cell (the upper side of the gamma direction in Fig. 3), and extends in the horizontal direction (X direction in Fig. 3). The power supply potentials (10), gnd) may be applied to each of the wiring layers 32a, 32b extending along the boundary of the standard cell, and correspond to the underlying wiring of the power supply line. Body. A GND potential can be applied to the wiring layer 32a, and a VDD potential can be applied to the wiring layer. The wiring layer 32a of the boundary of the P-type well region 1 in the Y direction of Fig. 3 is electrically connected to the p+ region 15, and is fixed. Further, the wiring layer 32a is branched from a portion extending in a straight line along the longitudinal direction (the state of the lower side in the Y direction in FIG. 3), and has a source region 11b in each of the nMOS transistors ΝΤ2, ΝΤ3. The upper extension portion electrically connects the source regions 11b to the portion. The wiring layer 32b is electrically connected to the n+ region 25 to fix the potential of the n-type well region 2. Further, the wiring layer 32b is longitudinally The direction (the gamma direction in Fig. 3) is branched by a straight line extending from the other side (the boundary of the upper side in the gamma direction of Fig. 3), and has a portion extending in the source region of the PM0S transistor pp2 , Γί is electrically connected to the source region 21b in part 4. In addition, in the source region lib of the nM0S transistor, the source region 21b of the PM〇s transistor PT1 and the source region 21b of the _S transistor PT3. Each of the wiring layers 32a, 32h, and 32f is electrically connected to each other. The connection between each of the wiring layers 32a to 32h and the impurity region forming the surface of the semiconductor substrate is via a plug layer formed in the contact hole 31a of the interlayer insulating layer 31A. Covering the wiring layer 32a In the embodiment, an interlayer insulating layer 33 made of SiOC or MSQ is formed on the interlayer insulating layer. A wiring trench 33b is formed on the interlayer insulating layer, and a bottom portion is formed from the bottom of the wiring trench 3 to the lower layer. The wiring layer 33a of each of the reticle layers is formed by, for example, a (10) alloy (amount of A1 is, for example, 〇.1 to 1. 〇%), so as to be embedded in the trench and the wiring trench 33b. Each of 34a to 34d is provided with a barrier metal layer (not shown) on the side surface and the bottom surface of the through hole 33a and the wiring (4) b. The barrier metal layer is located in each of the decorative layer layers ～34d and the interlayer insulating layer of 97126596 12 200915488 Between 33, between each of the through grooves 33a and the interlayer insulating layer 33, and between the respective layers of the through grooves 33a and the underlying wiring layer, the barrier metal layer has a stack of, for example, tantalum (Ta) and nitride (TaN) buttons. Further, under the interlayer insulating layer 33, an etching resist layer (not shown) made of, for example, siCN is formed. The source region 11b (wiring layer 32g) of the nMOS transistor NT1 and the nMOS are made by the wiring layer 34c. The source region lib of the transistor NT3 is electrically connected to each other. And C is electrically connected to the wiring layer 32a to which the GND potential can be applied. Further, the source region 21b (wiring layer 32h) of the pMOS transistor PT1 and the source region 21b (wiring layer 32f) of the pMOS transistor PT3 are made by the wiring layer 34d. The source regions 21b of the pMOS transistor PT2 are electrically connected to each other, and are electrically connected to the wiring layer 32b to which the Vj)D potential can be applied. In the plan view shown in Fig. 3, the wiring layer 34c is disposed on the inner side (center side) of the standard unit 51a as compared with the lower layer wiring layer 32a of the power supply line. Further, in the plan view shown in Fig. 3, the wiring layer 34d is disposed on the inner side (center side) of the standard cell 51a as compared with the lower layer wiring layer 32b of the power supply line. Further, the wiring layer 34a extends along one of the boundaries of the longitudinal direction of the standard cell 5ia (the Y direction in Fig. 3) (the boundary of the lower side in the Y direction in Fig. 3), and the horizontal direction in the boundary (Fig. 3) The middle X direction) extends. Further, the wiring layer 3牝 extends in the horizontal direction (the boundary of the upper side in the Y direction in FIG. 3) along the vertical direction (the Y direction in FIG. 3) of the standard cell 51a' in the horizontal direction (Fig. 3 Direction) Extension. The wiring layer 34a is connected to the wiring layer 32a extending in parallel in the lower layer thereof, and the wiring layer 34b is connected to the wiring layer extending in parallel in the lower layer thereof. Further, the wiring layer 34a has a line width W2a larger than the wiring layer 3 extending in parallel with the lower layer thereof, such as the line width Wla. Further, the wiring layer 34b has a line width W2b which is larger than the line width Wlb of the wiring layer 32b extending in parallel with the lower layer. In this manner, all of the wiring layers 34b, 34c, and 34d in the standard cell 51a are equivalent to the power supply potential of either of VDD and GND, and thus correspond to the upper layer wiring of the power supply line. Further, the electrical connection between each of the wiring layers 34a to 34d and the wiring layers 32a, 32b, 32e to 32h is a portion which is buried in the through trench 33a of each of the wiring layers 34a to 34d. According to the above manner, the source region of the _S transistor NT1 is connected to the lower layer wiring 32a of the power supply line of the G N D potential via the upper layer wiring 3 4 c f of the power supply line of the _ potential. Further, the source region 21b of each of the pM0S transistors m and ρτ3 is connected to the power line lower layer wiring 32b of the _ electric C/bit via the power line upper layer wiring 34d of the _ potential. Further, the signal line 32c is arranged in a plan view shown in Fig. 3, a line connecting the upper layer wiring 34c of the power supply line to the wiring layer (through hole), and a line along the boundary of the standard unit 51a of the lower layer wiring 32a. Between the extended parts. The signal line 32d is arranged in a top view shown in FIG. 3, and is located at a connection portion (via) of the upper layer wiring 34d and the wiring layer 32h on the power supply line, and a straight line extending along the boundary of the standard unit 51a of the lower layer light 32b. Between the parts. According to the present embodiment, the power supply line of the GND potential is separated into the lower layer wiring 97126596 14 200915488 32a and the upper layer wiring and the line 34a, and the power supply line of the lion potential is separated into the lower layer wiring 32b and the upper layer wiring 34b. Therefore, when the power line is a single layer, the speed is increased because the current path is increased. In addition, since it is not necessary to increase the line width of the power supply line, the current path can be increased, so that high integration can be achieved. Further, the upper layer wirings 34a, 34b have a line width wider than the lower layer wirings 32a, 32b.

Wla, Wlb $ large line width W2a, W2b ' so you can reduce the resistance (') value of the power line. Further, the lower layer wirings 32a and 32b have a line width W2a and a smaller line width Wla and Wlb than the upper layer cloth and the line 34a, so that the space for the wiring arrangement of the portion can be made large. Therefore, it is easy to arrange other wirings (e.g., signal lines 32c, 32d) and the like in the same layer as the lower wiring, and it is possible to improve the degree of freedom in the planar arrangement of other wirings. Further, each of the lower layer wirings 32a, 32b extends along the boundary of the standard unit 51a. Therefore, the lower layer wirings 32a, 32b can be shared by the adjacent standard cells 51. In this manner, the lower layer wirings 32a and 32b are not separately formed in the adjacent standard cells 51 & respectively, so that high integration can be achieved. Further, each of the upper layer wirings 34a, 34b extends along the boundary of the standard unit 51a. Therefore, in the same manner as described above, the upper layer wirings 34a and 34b are not separately formed in each of the adjacent standard cells 51a, so that high integration can be achieved. Further, the source region 11b of the nMOS transistor NT1 is electrically connected to the power supply line under the GND potential via the power supply line upper layer wiring 34c of the GND potential, 97126596 15 200915488 32a. In addition, the source regions of each of the pM0S transistors m and ρτ3 are connected to the upper layer wiring 32b of the power line of the _ | bit via the upper layer of the power line of the VDD potential and the line 34d f gas. Therefore, it is not necessary to extend each of the layer wirings 32b below the boundary of the standard cell, and to extend toward the central portion of the standard cell 51a at the position where the transistor is located. In this way, since each of the lower layer wirings 32a and 32b is extended toward the central portion of the standard single..., an empty space is generated. Therefore, a signal line plate, a curry, or the like can be disposed in the empty space. Other wiring can achieve high integration. In this manner, as a result of arranging the signal lines 32c, 32d in the empty space, the obtained configuration is that the signal line 32c is in the plan view shown in Fig. 3, and is located at the connection portion between the upper layer wiring 34c and the persimmon layer 32g of the power supply line. And between the extended portions of the standard cell 5la of the lower layer wiring 32a. In addition, the configuration of the signal line 32d is in the top view shown in FIG. 3, at the connection portion of the upper layer wiring 34d and the wiring layer 32h of the power supply line, and the extension of the boundary between the standard unit Ο 51a of the lower layer wiring between. According to the above method, a semiconductor device in which both high speed and high integrated body can be obtained can be obtained. (Embodiment 2) Referring to Fig. 5 and Fig. 6, in the present embodiment, the structure described is a CMOS inverter composed of a buckwheat transistor m and a transistor PT1 in each of a plurality of standard cells 51a. . A P-type light domain 形成 is formed on the surface of the semiconductor substrate, and the β well region 2 is selectively formed on the surface in the p-type well region 97126596 16 200915488. in? The surface in the well region 1 forms a _s transistor_. A _s transistor PT1 is formed on the surface in the n-type well region 2. The side along the boundary of the standard unit 51a (the Y direction in FIG. 5) (the boundary of the lower side in the Y direction in FIG. 5) 'the surface in the P-type well region 1' is formed in the lateral direction (FIG. 5). The P+ region 15 extends in the middle X direction. Further, along the other side of the vertical direction (Y direction in FIG. 5) of the standard unit 51a (the boundary of the upper side in the Y direction in FIG. 5 (the _., the upper side in the Y direction), the surface in the n-type well region 2 is formed in the horizontal direction. η+ region 25 extending in the direction (X direction in Fig. 5). Each of the formation regions ρ region 15 and η + region 25 of the MOS transistor is electrically isolated from each other on the surface of the semiconductor substrate for the month t* For example, the element isolation region 3 composed of STI is composed of a trench provided on the surface of the semiconductor substrate and an insulating filler filled in the trench. The nM〇S transistor NT1 has a drain region 11a and a source. The region lib, the gate insulating G layer 12' and the gate electrode layer 13. The non-polar region and the source region are formed by the impurity regions of the n-type impurity region forming a distance from each other on the surface of the p-type well region. 2. The gate insulating layer 12 is formed on the region of the source region of the region to be gated by the drain region • Hb. The pMOS device has a immersed region and a source region, and the insulating layer is 22 ^°. The drain layer 23. The gate region 21a and the source region 21b are p-type bay regions Forming a distance from each other on the surface of the n-type well region 2. The insulating layer 22 is formed on the region of the insufficiency region 21a and the source region 97126596 17 200915488 21b. nMOS transistor NT2 The gate electrode layer 13 and the gate electrode layer 23 of the _s transistor pT2 are formed by a common conductive layer and are electrically connected to each other. The MOSFETs 1 and ΡΤ1 are formed on the surface of the semiconductor substrate by covering the respective MOS transistors ΝΤ1 and ΡΤ1. The interlayer insulating layers 31A and 31β are laminated, and the interlayer insulating layer 31A is formed of, for example, a TEOS oxide film, and the interlayer insulating layer 31B is formed of, for example, a party, etc. The interlayer insulating layer 31B is formed with a wiring from the upper surface thereof to the interlayer insulating layer 31A. In the trench 31b, the contact hole 31a which reaches the semiconductor substrate from the wiring trench can be formed in the interlayer insulating layer 31A. The CuA1 alloy is embedded in each of the wiring trenches 31b (the A1 content is, for example, 〇). M. 0%) Each of the wiring layers 32a, 32b, 32e, 32g, and 32h is formed. Further, in each of the contact holes 31a, a plug layer made of, for example, tungsten (W) is formed. . Further, a barrier metal layer is formed on the side surface and the bottom surface of the contact hole 31a (not shown). The transition metal layer is located between the plug layer and the layer affinity layer 31A, and between the plug layer and the semiconductor substrate. The metal layer has a laminated structure of, for example, titanium (Ti) and titanium nitride (TiN). A barrier metal layer (not shown) is also formed on the side surface and the bottom surface of the wiring trench 31b. The barrier metal layer is located on the wiring layer. Between each of 32a, 32b, 32e, 32g, and 32h and the interlayer insulating layer 31B, between each of the wiring layers 32a, 32b, 32e, 32g, and 32h and the plug layer, and the wiring layers 32a, 32b, and 32e, Between each of 32g and 32h and the interlayer insulating layer 31A. The barrier metal layer 97126596 18 200915488 is composed of, for example, a button (Ta). Further, a surname blocking layer (not shown) made of, for example, SiCN is formed between the interlayer insulating layer 31A and the interlayer insulating layer 31B. The drain region 丨丨a of the nMOS transistor NT1 and the drain region 21a of the pM 〇s transistor PT1 are electrically connected to each other by the wiring layer 32e. Further, the wiring layer 32 & extends to one side of the boundary of the vertical direction of the standard cell 51a (the γ direction in FIG. 5) (the boundary of the lower side in the Y direction in FIG. 5), and the horizontal direction in the boundary (in FIG. 5 Direction) extends. Further, the wiring layer 32b extends along the other side of the boundary of the standard unit 51a (the Y direction in FIG. 5) (the boundary of the upper side in the γ direction in FIG. 5) in the horizontal direction (X in FIG. 5). Direction) extends. The wiring layer is electrically connected to the n+ region 25 of its lower layer, by which the potential of the n-type well region 2 is fixed. Each of the wiring layers 32a, 32b extending along the boundary line of the standard cell 51a can apply a power supply potential of either of VDD and GND, and corresponds to the underlying wiring of the power supply line. Specifically, a GND potential can be applied to the wiring layer 32a, and a VDD potential can be applied to the wiring layer 32b. The wiring layer 32a is electrically connected to the p+ region 15 of the lower layer thereof, by which the potential of the p-type well region 1 is fixed. Further, the wiring layer 32a is branched from a portion extending in a straight line along one of the vertical direction (the Y direction in Fig. 5) (the boundary of the lower side in the Y direction in Fig. 5), and has a CM0S inversion which is not formed. The extension of the standard unit 51a of the functional component of the device or the like. The wiring layer 32b is electrically connected to the n+ region 25, with which the potential of the n-type well region 2 97126596 19 200915488 is fixed. In addition, the wiring layer Na is extended from the straight line of the other side of the boundary in the longitudinal direction (the γ direction in FIG. 5) (the boundary of the upper side in the γ direction in FIG. 5): and branches, having the (10)s not formed. A portion of the standard unit 51a of the functional element such as the reverse ohm. Further, each of the source region 丨丨b of the nMOS transistor NT1 and the source region 21b of the pM〇s transistor is electrically connected to each of the wiring layers for 32 hours. Further, the connection of each of the wiring layers 32a, 32b, 32e, 32g, 32h and the impurity region formed on the surface of the semiconductor substrate is a via layer formed in the contact hole 31a formed in the interlayer insulating layer. An interlayer insulating layer 33 made of, for example, Si〇C and MSQ is formed on the interlayer insulating layer 318 so as to cover the wiring layers 32a, 32b, 32e' 32g, and 32h. A wiring trench 3 is formed on the upper surface of the interlayer insulating layer 33, and a trench 3 is formed, for example, from the bottom of the wiring trench 33b to the respective wiring layers of the lower layer. Each of the wiring layers 34c and 34d made of a CuM alloy (J (A1 content is, for example, about 0.1 to 1.0%) is formed, for example, so as to be buried in the through-grooves 33a and the wiring grooves 33b. A barrier gold layer (not shown) is formed on the side surface and the bottom surface of the wiring trench 33b. The barrier metal layer is located between each of the wiring layers 34c and 34d and the interlayer insulating layer 33, and each of the vias 33a and the interlayer Between the insulating layers 33, and between the respective trenches 33a and the underlying wiring layer. The barrier metal layer has a laminated structure such as a button (Ta) and a nitride button (TaN). Further under the interlayer insulating layer 33 An etching layer 97126596 20 200915488 (not shown) made of, for example, SiCN is formed. The source regions 11b (wiring layers 32g) of the crystal cells m of the respective standard cells 51a are electrically connected to each other by the wiring layer 34c. Further, the wiring layer (10) is electrically connected to the branch portion of the lower layer wiring 32a of the power supply line in the standard cell 51a which is not formed with the CM〇S inverter. Further, each of the standard cells is formed by the wiring layer 34d. Source region 21b of PT1 (wiring layer 32h) The wiring layer 34d is electrically connected to the branch portion of the lower layer wiring 32b of the power supply line in a standard unit 51aa in which the (10) S is not formed. The wiring layer 34c is in the plan view shown in FIG. The wiring layer 34d is disposed on the inner side (center side) of the standard unit 51a as compared with the lower layer wiring layer 32a of the power supply line. The wiring layer 34d is compared with the lower wiring layer 32b of the power supply line in the plan view shown in FIG. It is disposed on the inner side (center side) of the standard unit 5ia. The electrical connection between each of the wiring layers 34c and 34d and the wiring layers 32a, 32b, 32g, and 3 is immersed in each of the wiring layers 34c and 34d. The part inside the channel 33a.

According to the above-described manner, the source region lib of the nMOS transistor NT1 is electrically connected to the lower layer wiring 32a of the power supply line of the GND potential via the GND. power supply line upper layer wiring 34c. Further, the source region 21b of the pMOS transistor PT1 is electrically connected to the lower layer wiring 32b of the power supply line of the V D D potential via the power line upper layer wiring 34 d of the VDD potential. According to the present embodiment, each of the lower layer wirings 32a, 32b extends along the boundary of the standard sheet 97126596 200915488, 51a. Therefore, the lower layer wirings 32a, 32b can be used between the adjacent standard cells 51 & In this manner, in the adjacent standard cells, since it is not necessary to form the lower layer wirings 32a and 32b individually, it is possible to achieve high integration. Further, each of the upper layer wirings 34a, 34b extends along the boundary of the standard unit 51a. Therefore, in the same manner as described above, since each of the adjacent standard cells 51a does not need to be individually formed with the upper layer wirings 34a and 34b, it is possible to achieve a high integrated structure. Further, the source region lib of the nMOS transistor ΝΤ1 is electrically connected to the power line lower layer wiring 32a of the GND potential via the power line upper layer wiring 34c of the gnd potential. Further, the source region 2ib of the PMOS transistor PT1 is electrically connected to the power line lower layer wiring 32b of the VDD potential via the power line upper layer wiring 34d of the VDD potential. Therefore, it is not necessary to extend each of the layer wirings 32a and 32b located under the standard cell 51&; toward the central portion of the standard cell 5^ where the respective transistors are located. In this manner, since the empty space is generated in a portion where the lower layer wirings 32a and 32b are to be extended toward the central portion of the standard unit 51a, the signal lines 32c, 32d and the like can be disposed in the empty space. • Wiring, and high integration can be achieved. According to the above aspect, it is possible to obtain a semiconductor device which is both high speed and high in integration. Further, in the second embodiment, the standard unit 51a in which the functional element (e.g., CMOS inverter) is not formed in Fig. 5 may be arranged as shown in Fig. 7 by the fuse 97126596 22 200915488. A plurality of standard cells η in which such fuses are arranged may also be present in the semiconductor device. The fuse 4 can be disposed, for example, in the path of the branch portion of the power line lower layer wirings 32a, 32b. The configuration of Fig. 7 is substantially the same as that of Figs. 5 and 6 described above, and the same reference numerals will be given to the same elements, and the description thereof will not be repeated. In FIG. 5, the configuration is such that the power line upper layer wiring 34c is electrically connected to the lower layer wiring coffee in the standard unit 51a' where the functional elements are not formed, and the power line upper layer wiring 34d is electrically connected to the lower layer wiring 3 this. However, in the second embodiment, as shown in Fig. 8, in the standard unit 51a in which the functional elements are not formed, the upper layer wiring 3 of the power supply line may be electrically connected to the lower layer wiring 32a' and the upper layer of the power supply line. The wiring 34d is not electrically connected to the lower wiring 32b, and the column composed of the plurality of standard cells 51a is more present in the semiconductor device. The configuration of Fig. 8 is substantially the same as that of Figs. 5 and 6 described above, and the same reference numerals are given to the same elements, and the description thereof will not be repeated. As shown in Fig. 5 of Fig. 2, in the standard unit 51a in which the Wei element is not formed, the upper layer wiring 3 of the power supply line is electrically connected to the lower layer wiring, and the upper layer wiring 34df of the power supply line is connected to the lower layer wiring. The form becomes A. Further, as shown in FIG. 8, the standard unit 97126596 23 200915488 51a 'the power line upper layer wiring 34c is not electrically connected to the lower layer wiring, and the power line upper layer wiring 34 (1 is not electrically connected to the lower layer). The form of the wiring coffee is in the form of B. In the semiconductor device stage, it is possible to design a plurality of standard cell arrays having the A form as a unit column capable of high-speed operation by alternately changing the shape and the β form. And can be designed to use a plurality of standard cells 51a having a B form as a cell column capable of low power consumption operation. ° In a standard cell 51a column having a plurality of states, since power lines are utilized from multiple layers In addition, in the standard cell 51 & column having a B form, the potential relationship is the lower layer wiring 32a < the upper layer wiring 34c < the upper layer cloth, the line 34d < the lower layer cloth, the line coffee. a method of supplying a potential voltage different from a substrate potential and a source potential of the _S transistor NT1 or the _ transistor m, and using a substrate effect to make the transistor The threshold value (V ratio) becomes larger, which can be used to reduce the waiting current of the circuit including the standard unit, and can be operated with low power consumption. The A form and the B form of j, because the size of the unit is not f Similar, it is possible to simply alternate, and it is possible to simply alternate the column of cells capable of high-speed operation and the column of cells capable of low-power operation. $External as shown in Fig. 7 'Configure the standard cell 51a in which functional elements are not formed The form of the line 40 is in the form of G. By having the c form, the test step of the product can be alternated with the high-speed operation of the above-described method according to the presence or absence of cutting of the line, and the operation of the semiconductor processing can be repeated. The wafer of the product is 97126596 24 200915488. The problem of the characteristic change after completion is increased. However, in the test step, the standard variation unit 51a is guided by the high-speed operation or the low-power consumption operation, so that the characteristic variation can be made small. The situation is considered to make the threshold voltage of the transistor shift toward the lower direction, so that the action speed is much larger than the target speed, and the power consumption can be made at the same time. In this case, the fuse is cut, and the potential relationship between the plurality of standard cells 51a having the B form is used, and the power consumption can be suppressed by reducing the power consumption generated by the substrate effect. (Embodiment 3) The present embodiment is configured to realize the circuit structure shown in Fig. 2 via the structure of the second embodiment. Referring to Fig. 9 and Fig. 10, for example, in the structure of the present embodiment, for example In the three side-by-side standard cells 5ia having inverters, the nMOS transistor NT1 and the pMOS transistor 内 in the central standard cell 5la correspond to the 〇CMOS inverter of the output section of Fig. 2. In addition, the standard from the center a CMOS inverter composed of a nMOS transistor NT2 and a pMOS transistor PT2 of a standard cell 5ia on the right side of the cell 51a, and a nMOS transistor NT3 and a pMOS transistor PT3 of a standard cell 51a on the left side of the figure. The CMOS inverter corresponds to the driver of Figure 2. The gate electrode layer 13 of the nMOS transistor NT1 in the central standard cell 51a and the gate electrode layer 23 of the pMOS transistor PT1 are electrically isolated. The wiring layer 32e of the standard unit 51a on the right side is electrically connected to the gate unit of the standard unit 5丨a of the center, 97126596 25 200915488, and corresponds to the signal line 32c in the first embodiment. The wiring layer 32ei is electrically connected to the drain region 丨la of the riMOS transistor NT2 and the gate region 21a of the pM〇s transistor. Further, the wiring layer 32ez of the standard cell 5a on the left side is electrically connected to the gate electrode layer 23 of the standard cell 51a in the center, corresponding to the signal line 32d in the first embodiment. The wiring layer 32e2 is electrically connected to the drain region i la of the nMOS transistor NT3 and the drain region 21a of the PMOS transistor PT3. The upper power line upper layer wiring 34c has a line width W2a larger than the line width W1 of the layer wiring 32a extending in parallel with the lower layer thereof, and the upper layer wiring 34d has a larger line width W1 than the layer wiring 32b extending in parallel with the lower layer thereof. Line width W2b. In this manner, the upper layer wiring 34c has a portion located inside the standard cell 51a as compared with the lower wiring layer 32a in the plan view shown in Fig. 9. The upper layer wiring 34c is located on the inner side of the lower layer wiring 32a, is planarly repeated on the wiring layer, and is electrically connected to the wiring layer 3 via the via hole 33a. 1/ In addition, the power line upper layer wiring 34d has a portion located inside the standard unit 51a as compared with the lower wiring layer 32b in the plan view shown in FIG. The portion of the upper layer wiring 34d located further inside than the lower layer wiring 32b is planarly repeated in the wiring layer 32h, and is electrically connected to the wiring layer 3 via the via hole 33a. Each of the power line lower layer wirings 32a, 32b linearly extends along the boundary line of the standard unit 51a, and does not have a branch portion extending from the boundary portion toward the inner side of the standard unit 51a. According to the above manner, the source region 11b of the nMOS transistor NT1 is electrically connected to the power line lower layer wiring 32a of the _ potential via the layer wiring and the line 34c of the power supply line of the GND potential of 97126596 26 200915488. Further, the source region of the PMOS transistor PT1 is electrically connected to the lower layer wiring 32b of the power supply line via the power supply line upper layer wiring 34d. Further, in the plan view shown in Fig. 9, the signal layer 32ei is disposed between the connection portion (via hole 33a) of the power line upper layer wiring 34c and the wiring layer 32g and the lower layer wiring 32a. In the plan view shown in Fig. 9, the signal line 32ez is disposed so as to be located between the connection portion (via hole 33a) and the lower layer wiring 32b of the power line upper layer wiring 34d and the wiring layer 32h. It is to be noted that the same components as those of the second embodiment shown in Fig. 5 and Fig. 6 are denoted by the same reference numerals, and the description thereof will not be repeated. According to the present embodiment, the power supply line of the G N D potential is separated into the lower layer wiring 32a and the upper layer wiring 34c, and the power supply line of the VDD potential is separated into the lower layer wiring 32b and the upper layer wiring 34d. Therefore, when the power line is a single layer, the speed is increased because the current path is increased. In addition, since it is not necessary to increase the line width of the power supply line to increase the current path, it is also possible to achieve high integration. Further, the upper layer wirings 34c, 34d have a line width wider than the lower layer wirings 32a, 32b.

Wla and Wlb are the line widths W2a and W2b, so the resistance of the power line can be reduced. Further, the lower layer wirings 32a and 32b have a line width of 97126596 27 200915488 W2a and W2b which are smaller than the line widths of the upper layer wirings 34c and 34d. Therefore, the space for the wiring of the portion can be made larger. Therefore, it is easy to arrange other wirings (e.g., signal lines 32ei, 32e2) in the same layer as the lower wiring, and to improve the degree of freedom in the layout of other wirings. Further, each of the lower layer trimming lines 32a, 32b is bitten along the boundary of the standard unit. Therefore, the lower fabric edges 32a, 32b can be shared between adjacent standard cells 51a. In this manner, the lower layer wirings 32a and the coffee are formed separately in the adjacent standard cells 51 & 0, so that high integration can be achieved. Further, each of the upper layer wirings 34c and 34d extends along the boundary of the standard unit. Therefore, as in the above, the upper layer wirings 34c and 34d are not separately formed in the adjacent standard cells (10), so that high integration can be achieved. Further, the source region of each of the secret crystals NT1 to NT3 is connected to the lower layer wiring 32a of the power line of the _ potential via the upper layer wiring 34c of the _ potential. Further, each of the source regions of the pM0S transistors m to pT3 is electrically connected to the lower layer wiring 32b of the power supply line via the potential power line upper layer wiring 34d. Therefore, it is not necessary to extend the layer wiring 32a and the coffee which are located below the boundary of the standard early 51a, and to extend toward the central portion of the standard unit 51a at the position of each of the transistors. In this manner, since an empty space is generated in a portion where each of the lower layer wirings 32a and 32b is to be extended toward the central portion of the standard unit 51a, the signal lines 32ei, 32, etc. can be disposed in the empty space. The wiring can be achieved with high integration. In this manner, as a result of arranging the signal lines 32ei, 32& in the empty space, the configuration obtained by 97126596 28 200915488 is that the signal line 32ei is in the top view shown in FIG. 9, and is located above the power line upper layer wiring 34c and the wiring layer 32g. Between the connection portion 'and the lower layer wiring 32a. Further, the obtained configuration is that the money line 32e2 is located between the upper portion of the power line upper layer wiring 34d and the wiring layer 32h and the lower layer wiring 32b in the plan view of Fig. 9. According to the above aspect, it is possible to obtain a semiconductor device which is both high speed and high in integration. Further, in the first to third embodiments described above, an element having a CMOS inverter as a functional element is described. However, the present invention is not limited to this, and may be applied to a CMOS NAND or NOR circuit, or the like. Functional components. (Embodiment 4) Referring to Fig. 11 and Fig. 12, the circuit of this embodiment has two input nmd gates M1, NA2' buffers BUI, BU2, BU3 and an inverter IN. The 2-input NAND gate NA1 has the pM〇s transistors ό11, ΡΤ12 and nMOS transistors ΝΤ11, ΝΤ12 shown in Fig. 12. A terminal a is electrically connected to each gate of the pM〇S transistor ΡΤ11 and the nMOS transistor NT11, and a terminal B 〇-buffer BU1 is electrically connected to each gate of the pM〇s transistor PT12 and the nMOS transistor NT12. A CMOS inverter composed of a pMOS transistor ρτΐ3 and an nMOS transistor NT13, and a CMOS inverter composed of a pMOS transistor ρτΐ4 and an nMOS transistor NT14 are included. The buffer βυΐ is constructed to be input with the output of the NAND gate NA1. 97126596 29 200915488 The configuration of the buffer BU2 includes a CMOS inverter composed of a pM〇S transistor ρτΐ5 and an nMOS transistor NT15, and a CMOS inverter composed of a pMOS transistor ρτΐ6 and an nMOS transistor NT16. The buffer 2 is constructed to be input with the output of the buffer BU1. The buffer BU3 is composed of a CMOS inverter composed of a pM〇S transistor ρτΐ7 and an nMOS transistor NT17, and a CMOS inverter composed of a pMOS transistor ρτΐ8 and an nMOS transistor NT18. A terminal C is electrically connected to each of the gates of the pMOS transistor ρτΐ7 and the nMOS () transistor NT17. The 2-input NAND gate M2 has the connected transistor PT19, PT20 and nMOS transistors NT19, NT20 as shown in FIG. The gate of each of the PM0S transistor PT19 and the nMOS transistor NT19 is electrically connected to the output of the buffer bu2. The outputs of the buffer BU3 are electrically connected to the respective gates of the pMOS transistor PT20 and the nMOS transistor NT20. The configuration of the inverter IN includes a CMOS inverter composed of a pM 〇s transistor PT21 and an nMOS transistor 〇 NT21. An output of the NAND gate NA2 is electrically connected to each of the gates of the pMOS transistor PT21 and the nMOS transistor NT21. In addition, the output of the inverter IN is electrically connected to the terminal γ. Next, a plan layout configuration of the semiconductor device constituting the circuit shown in Fig. 12 and Fig. 12 will be described. Fig. 13 shows a polycrystalline germanium layer formed in a diffusion region and an element isolation region of a semi-conducting plate, and a gate electrode layer formed on a semiconductor substrate. Fig. 14 mainly shows the above polycrystalline germanium layer and the metal layer of the first layer thereon. In addition, Fig. 15 97126596 30 200915488 represents the metal layer of the first rhinoceros described above. The metal layer of the stomach metal layer and the second layer and the third layer thereon are as shown in FIG. 13, and the NAND gate forming region ΝΑΙ, M2 is formed on the surface of the semi-conducting pot 1 _ conductor substrate SUB, and the buffer forming region is formed.刖1, muscle 2, 8113, the formation of the inverter is the domain IN and the non-circuit structure. The non-circuit regi〇n N0N. The respective leveling units of the forming regions. The buffer/t buffer region 蜮_, the non-circuit configuration region NON ’ and the inverter Γ region 1N are arranged such that the _ column is in the X direction. Further, the second region: the region NA1, the buffer formation region, and the buffer formation region S彳_D gate formation region NA2 are arranged in the X direction in the order. The above-described pMOS transistor ρτΐ 1 , coffee and crystal cell (4) are formed in the formation region NA1 of the face gate. In the formation area of the bumper

L is formed with the above-mentioned _S transistors PT13, PT14 and _S transistors NT13, NT14° in the formation region of the buffer, that is, 2, the above-mentioned pM〇s transistor; 15 PT16 and nM〇s transistor NT15, NT16. The above-mentioned home crystals m9, ρτ2 〇 and the crystals ΝΤ19 and ΝΤ20 are formed in the formation region NA2 of the _D. In the formation region β缓冲3 of the buffer state, the above-mentioned pM〇s transistor snoring, ΡΠ8, and the crystal expansion and deletion are formed. The above-described PM〇s transistor PT21 and nM〇s transistor 21 are formed in the formation region of the inverter. In the region along the formation of the buffer, the non-circuit-forming region brain and the reverse phase of the Y-direction of the region IN, in the direction of the upper side of the Y-direction in the figure, extend the surface in the semiconductor substrate SUB. A Ρ+region pri is formed. In addition, the formation region NA1 of the NAND gate, the boundary region of the γ direction in the region of the formation region M2 of the buffer BU 丨, BU2 # NAND gate, and the manner of extending in the X direction in the figure 'in the semiconductor substrate The inner surface forms a p+ region PR2. . In addition, in the buffer forming region _, the non-circuit forming region, and the Γ 成 forming region IN of the 巾 γ direction, that is, along the MND gate forming region ,1, the buffer forming region brain, The boundary between the upper side of the Y direction and the area of the formation region M2 of the face gate forms an n+ region NR. The n + region NR is also formed on the surface of the semiconductor substrate SUB in such a manner as to extend along the boundary in the X direction in the drawing. Referring to Fig. 14, a patterned metal layer of a first layer is formed on an MOS transistor via an interlayer insulating layer (not shown). The metal layer of the second layer has a power line under the power line GNDU, 眺2, a potential line below the power line VDDL, and other signal lines su. The lower layer wiring GNDL1 extends along the region where the buffer is formed, the non-circuit forming region, and the boundary region between the domain and the forming region of the inverter in the gamma direction, extending in the X direction in the figure. The lower layer wiring GNDL1 is electrically connected to the P+ region PR1 of the lower layer via a plurality of contact holes ch. The lower layer wiring·2 is along the area where the coffee is formed, and the formation area of the buffer, the formation area of the BU2 and the _ idle, and the lower side of the γ direction in the figure are 97126596 32 200915488, which extends in the X direction in the figure. . The lower layer wiring is electrically connected to the ρ+ region pR2 of the lower layer via a plurality of contact holes CH. The lower layer wiring VDDL is in the buffer formation region BU3, the non-circuit formation region ._ and the reverse ϋ formation region 1N in the lower side of the γ direction, that is, the formation region of the MNAND gate formation region NA1 'buffer In the graph of the formation region NA2 of the sum gate and the gate, the boundary of the upper side in the γ direction, in the figure, the L direction L extends the layer, and the line VDDL is electrically connected to the n+ region NR of the lower layer via the plurality of contact holes CH. Referring to Fig. 15', a metal layer of the second layer of the first layer is formed on the metal layer of the first layer via an interlayer insulating layer (not shown). The metal layer of the second layer has a GND potential power line upper layer wiring GNDU1, GNDU2, a potential power line above the layer trim line VDDU and other signal lines. The upper layer wiring G_ extends along the buffer forming region BU3, the non-circuit forming region NON and the inverter forming region IN in the upper side in the γ direction, and extends in the X direction in the drawing. The upper layer wiring GNDU1 is electrically connected to the lower layer wiring GNDL1 via a plurality of via holes VH1. Further, the upper layer wiring GNDU1 has a line width W2ai larger than the line width Wlai of the lower layer wiring GNDL1. The upper layer wiring GNDU2 is formed along the gate formation region NA1, the shape of the buffer, and the boundary between the region BU1, BU2 and the NAND gate formation region NA2 in the Y direction lower side, and extends in the X direction in the drawing. The upper layer wiring GNDU2 is electrically connected to the lower layer lower layer wiring GNDL2 via a plurality of via holes VH1. Further, the upper layer wiring GNDU2 has a line width W2a2 which is larger than the line width Wla2 of the lower layer wiring GNDL2. 97126596 33 200915488 The upper layer wiring VDDU is in the buffer forming region BU3, the circuit forming region NON and the forming region IN of the inverter are in the lower boundary of the ¥ direction, that is, along the NAND gate forming region NA1 'buffer The boundary between the formation region Βυ^2 and the gate formation region M2 in the upper side in the γ direction extends in the χ direction in the drawing. The upper layer wiring VDDU is raised by one via a plurality of via holes, and is electrically connected to the lower layer T wiring wiring L. The upper layer wiring VDDU has a line width W2b larger than the line width Wlb of the lower layer wiring VDDL. A metal layer of the third layer produced by the pattern is formed on the metal layer of the second layer via an interlayer insulating layer (not shown). The metal layer of the third layer has a reinforcing wiring GNDS for reinforcing the potential of the power supply line of the GND potential, a reinforcing wiring VDDS for the potential of the power supply line for reinforcing the potential, and other signal lines 乩3. Each of the reinforcing wiring GNDS and the reinforcing wiring VDDS is extended by θ in the orthogonal direction (i.e., the γ direction in the figure) in the upper layer wiring G, GNDU2, and the top surface wiring GNDS. In the plan view, the reinforcing cloth and the line GNDS are electrically connected to the upper layer wiring G_ and the second layer by the plurality of (for example, four) through holes VH2 at the parent point of the upper layer wiring _ surface and (four) 2 . each. In addition, in the top view, the reinforcing wiring is crossed with the upper wiring side, and is electrically connected to the upper wiring via the plurality of (for example, four) through holes VH2 at one intersection. Further, the signal lines SLb and SL3 of the respective layers are electrically connected to each of the simple transistors, and become the circuit configuration shown in Figs. 11 and 12 . Further, in Fig. 13, the portion indicated by the oblique line is a polysilicon layer formed on the gate electrode layer or the like on the semiconductor substrate, and the portion indicated by the dot pattern is a diffusion region formed on the semiconductor substrate 97126596 34 200915488. The plurality of layers or diffusion regions are electrically connected to each of the MOS transistors to form the circuit configuration shown in FIGS. 11 and 12. Further, the arrangement pitch Pv of the plurality of holes TM of the lower layer wiring GNDL1 and the upper layer wiring GNDU1 of the connection pattern +# + β 斤 is the same as the arrangement gate distance ρτ of the transistor shown in Fig. 13 . In addition, the arrangement _ ν of the plurality of via holes VH1 connecting the lower layer wiring read and the upper layer wiring G_2, and the arrangement pitch A of the plurality of via holes connecting the lower layer wiring ancestor and the upper layer wiring VDDU also become the same as those of FIG. The crystals are matched (4) and (4) into phase spacing. In this way, the resistance value of the power supply line can be reduced, and the potentials of the lower layer wiring and the upper layer wiring can be enhanced. Referring to Fig. 16, a plurality of reinforcing wirings and a plurality of upper layer wirings GNDU and VDDU are arranged in a plan view to form a lattice. Each of the plurality of reinforcing wirings is electrically connected to a plurality of upper layer wirings G_ (including G planes, _2) via via holes. In addition, each of the plurality of reinforcing wires is electrically connected to a plurality of upper layer wirings VDDU via via holes (4). According to the present embodiment, the power supply line of the GND potential is separated into the lower layer wirings GNDL1, GNDL2 and the upper layer wiring GNDUb GNDU2, and the power supply line of the VDD potential is separated into the lower layer wiring VDDL and the upper layer wiring VDDU. Therefore, when compared with the case where the power supply line is a single-layer, the speed is increased, so that the speed can be increased. Further, since it is not necessary to increase the power supply line width, the current path can be increased, so that high integration can be achieved. 97126596 35 200915488 In addition, the line widths W2ai, W2az, and W2b of the upper layer wiring GNDU1, GNDU2, and VDDU are smaller than the line widths of the lower layer wirings GNDU, GNDL2, and VDDL, and Wla2 and Wlb, so that the resistance value of the power line can be reduced. . In addition, the line widths Wla丨, Wla2 of the lower layer wirings GNDL1, GNDL2, and VDDL

Since each of Wlb is smaller than the line widths W2ai, W2az, and W2b' of the upper layer wiring (3) dirty, G_2, and VDDU, the space for arranging the partial wiring becomes large. Therefore, it is easy to arrange other C wirings and the like in the same layer as the lower layer wirings GNDL1, GNDL2, and VDDL, and it is possible to improve the degree of freedom in the planar arrangement of other wirings. Further, the lower layer wirings GNDL1, GNDL2, VDDL and the upper layer wirings GNDU1, GNDU2, VDDU extend along the boundary of the standard cell, respectively. Therefore, the power lines can be shared among the adjacent standard units. In this way, since it is not necessary to form the power lines individually in each standard cell, high integration can be achieved. Further, the signal line SLi of the metal layer of the first layer is used as a standard cell (J wiring. The signal line SL2 of the metal layer of the second layer extends in the direction of the χ in the figure to be the lower layer GNDL1, GNDL2 The wiring pattern of the VDDL power supply is used as the wiring between the standard cells to be connected. In addition, the k-line SL3 of the third metal layer extends along the Υ direction in the figure to cross the lower layer 'GNDL1' The wiring of the power supply system of GNDL2 and VDDL is used as the wiring between the standard cells. In this way, the wiring design of P&R (Place and R〇ute) is made easy. In this way, it is possible to obtain a semiconductor device that is both high-speed and high-integrated at the same time. (Embodiment 5) In the present embodiment, a device having a high material element and a high accumulation material element is used. 17, the SOC wafer SOC has, for example, a high-integral-priority logic region muscle, a high-performance-priority logic region HRL, and a region other than logic. The high-integral-priority logic region HIL is a high-speed unit suitable for a high-motion operation. In addition, in the high-performance-priority logic region, it is formed by a high-integral unit suitable for a high-product body. FIG. 18 shows a diffusion-integration region formed in a semi-conducting plate, and is formed on a semiconductor substrate. a plurality of layers of the gate electrode layer, etc. The target mainly indicates the above-mentioned multi-deformation layer and the metal layer of the second layer thereon. Further, FIG. 2A mainly shows the metal layer of the first layer and the above The metal layer of the second layer. Referring to Fig. 18, both the high-speed unit and the high-integral unit are formed by a CM〇s inverter composed of a storage cell ρτ and an nMOS transistor 。. In the high-speed unit and the high (four) unit- Side, side transistor ρτ and i have a P-type source A-pole region SD, _ edge film (phase phantom, and inter-electrode layer 诎. The i-to (four) source/no-polar region is formed in half The surface of the impurity-conducting substrate SUB is formed on the surface of the semiconductor substrate of the P-type: pole: drain region SD package by the gate insulating film at the same speed and the high-speed integrated unit Either _S transistor Ντ has 1 97126596 37 200915488 η type source/wave region S D, a gate insulating film (not shown), and a gate electrode layer GE. The pair of n-type source/wave regions are formed on the surface of the semiconductor substrate SUB. The gate electrode layer GE is formed via a gate insulating film. The surface of the semiconductor substrate SUB of the n-type source/drain region is sandwiched between the high-speed cell and the high-concentration element, and the p(tetra) transistor is struck between the electrode layer GE and the nM0S transistor NT. The gate electrode layers GE are integrally formed and electrically connected to each other. % f, in the diagram of the m standard cell region of the high and high accumulation elements, the upper boundary of the γ direction, in the manner of extending in the x direction in the figure, A region NIR is formed on the surface in the semiconductor substrate SUB. Further, a p+ region pir is formed on the surface of the semiconductor substrate SUB so as to extend in the X direction in the figure along the boundary of the standard cell region in the lower side in the Y direction. The planar arrangement of the CMOS inverter of the high speed unit here and the planar arrangement of the CMOS inverter of the high integrated unit are the same. Further, the plane arrangement of each of the C field NIR and the P+ area PIR of the 高速+ zone of the high speed unit is the same as the plane arrangement of each of the n+ area NIR and the p+ area PIR of the high integrated unit. Referring to Fig. 19, a patterned metal layer of the first layer is formed on the MOS transistors PT and NT via an interlayer insulating film (not shown). The metal layer of the first layer. The power line lower layer wirings gnd and GNDL having the GND potential, the power line lower layer wirings VDD and VDDL of the VDD potential, and the other signal lines SLL1 and SLL2. The lower layer wiring GNDL extends in the X direction in the γ direction of the high-speed unit along the figure of the standard cell area. The lower layer wiring GNDL is electrically connected to the lower p+ region piR via a plurality of contact holes CH of 97,126, 596, 38, 2009. Further, the lower layer wiring GNDL is electrically connected to one of the source/drain regions SD of the _s transistor Ντ via a plurality of contact holes CH. The lower layer wiring VDDL extends in the X direction in the figure in the upper side of the γ direction in the figure of the high-speed unit along the standard cell area. The lower layer wiring lion L passes through a plurality of contact holes CH electrical axis to the lower layer n+ region _. Inferior wiring

The left side of the VDDL is electrically connected to a plurality of contact holes CH to one of the source/no-polar region SD of the 电 电 transistor. 4. The line SLL1, the left contact hole cjj is electrically connected to the source of the nM〇s transistor Ντ, the other of the source/recording area SD, and the source of the _ transistor ρτ/the other of the products or SD. The signal line rainbow 2 is electrically connected to the gate electrode layer GE via the contact hole 〇η. Here, the planar arrangement of each of the lower layer wiring GNDL and the lower layer wiring VDDL of the high-speed unit is the same as that of the lower layer wiring GND and the lower layer wiring_. Further, the planar arrangement of the letter sLU of the high speed unit and the signal line SLL2 and the plane arrangement of the signal line SLL1 and the signal line SLL2 of the high integrated unit are the same. _", Fig. 2 〇 on the metal layer of the first layer, through the interlayer insulating layer (not shown), the metal layer of the second layer formed by _ is formed. The metal layer of the second layer has a power supply of GND potential The upper layer of the line is rounded, the power line of the potential is above the wiring side, and the other signal lines are ~~ legs. The upper layer wiring GNDU is along the standard cell area of the high-speed unit in the γ direction 97126596 39 200915488 The lower side of the realm, in the figure The upper layer wiring GNDU is electrically connected to the lower layer lower layer wiring GNDL via the plurality of via holes VH1. The upper layer wiring GNDU has a line width W2a larger than the line width Wla of the lower layer wiring GNDL. The upper layer wiring VDDU is along The upper boundary of the γ direction in the figure of the standard cell area of the high speed unit extends in the X direction in the figure. The upper layer wiring is electrically connected to the lower layer wiring vm)L via the plurality of via holes VH1. The upper layer wiring VDDU has The line width Wlb is larger than the lower layer wiring VDDL by the line width w2b.

Further, each of the signal lines SLU3, SLU4 is formed in a standard unit of the high speed unit. Each of the signal lines SLU3 and SUJ4 extends in the χ direction of the figure (that is, in the same direction as the direction in which the upper layer wirings G_ and v are extended in the top view), the boundary of the fresh unit area of the '1⁄4 speed single TL' . The wire SLU3 is electrically connected to the signal line SLU via the through hole VH1. Further, the signal line (4) is electrically connected to the signal line SLL2 via the via hole VH1. Further, in the standard cell β of the south integrated body unit, each of the signal lines (4) and (4) extends in the Y direction in the drawing (i.e., in the plan view, in the direction orthogonal to the extending direction of the lower layer wiring G·, 卿). The signal line SLU1 is electrically connected to the t-line SLL via the through-hole TM. In addition, the signal line is electrically connected to the signal line SLL2 via the through-hole leg. Further, each of the signal lines SLU1 and SLU2 + L - LL ^ also extends in the Y direction in the figure, and traverses the boundary of the standard cell area of the entangled unit. The long-term δ 儿 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 97126596 200915488 Figure 21 shows the metal layer of the i-th layer. Fig. 22 shows the metal layer of the second layer of the first layer. Fig. 2 The genus of genus and its ...... The metal of the first and second layers is shown on the metal layer of the third layer and the fourth metal layer above it. And the genus layer, referring to FIG. 2, even in the case of the quasi-units of the plurality of standard cells, the metal layer of the 】 layer and the 2^^ ticket plane layout structure are in the high-speed unit and the high-integral unit. -^=2^23 of the same layer, even in the multiple units of the county, and the single "Feng mb off the plot, the second layer of metal =: a _ one speed list:

C In the high-speed unit, the upper layer wiring _, drawn by the metal layer of the second layer, is smaller than the line width of the lower layer wiring GNDL and the fox line, and forms a boundary extending along the boundary of the standard cell. Further, the signal line SLU composed of the metal layer of the second layer extends in the same direction as the lower layer wiring and the extending direction of the ship. Further, in the high-integration unit, the upper layer wiring G_ and the metal layer of the second layer are not provided. The signal line SLU composed of the layers of the two layers of the fourth layer extends in a direction orthogonal to the extending direction of the lower layer wirings GNDL and VDDL: In the high-speed unit, as shown in FIG. 22, the upper layer wiring is formed of the metal layer of the second layer. GNDU, VDDU. Therefore, the signal line SLU composed of the metal layer of the second layer cannot be extended to the boundary between the standard cell on the upper side in the Y direction and the temple display cell on the lower side in the figure. Therefore, in the high-speed unit, as shown in FIG. 23, when the metal layer of the third layer and the metal layer of the fourth layer are not used, the elements in the adjacent standard cells in the figure γ 97 97126596 41 200915488 cannot be made to each other. The elements in the standard cell adjacent to the name and the X direction in the figure are 'electrically connected to each other'. (4) By arranging the signal lines constituting the metal layer of the third layer so as to span the boundary between the standard cells above and below the Y direction in the figure, the components in the standard cells adjacent to each other in the γ direction in the figure can be electrically connected to each other. . Further, by arranging the signal line SL4 composed of the metal layer of the fourth layer so as to straddle the boundary between the standard cells on the left and right in the χ direction in the drawing, it is possible to cause the standard cells adjacent to each other in the χ direction in the drawing (the components in the ' On the other hand, in the high-integral unit, as shown in Fig. 22, the upper layer wirings GNDU and VDDU are not provided by the metal layer of the second layer. Therefore, the metal layer of the second layer can be formed.彳§ 5 The tiger line SLU extends to the boundary between the standard cells that are adjacent to each other in the γ direction in the figure. Therefore, in the high integrated unit, as shown in Fig. 23, even if the metal layer of the fourth layer is not used, the second layer is used. The metal layer of the layer and the metal layer of the third layer can also make electrical connection between the components CJ in the standard cell adjacent in the Υ direction in the figure and the components in the standard cell adjacent to the χ direction in the figure. That is, by arranging the signal line SLU composed of the metal layer of the second layer so as to span the boundary between the standard cells above and below the Y direction in the figure, the elements in the standard cell adjacent to the γ-direction in the figure can be made to each other. Production Further, by arranging the signal line SL3 composed of the metal layer of the third layer so as to straddle the boundary between the standard cells in the X direction in the drawing, the elements in the standard cells adjacent to each other in the X direction in the drawing can be made to each other. In the meantime, an electrical connection is made. 97126596 42 200915488 In accordance with this embodiment, the _ potential is made in the standard unit of the high speed unit.

The power supply line is separated into the lower layer wiring GNDL and the upper layer wiring GNDU, and the VDD is electrically recorded as the lower layer wiring ancestor and the upper layer wiring VDDU. Therefore, when compared with the case where the power supply line is a single-layer, since the current path is increased, the speed can be increased. In addition, since it is not necessary to increase the line width of the power supply line, the current path can be increased, so that high integration can be achieved. Further, since each of the line widths f2a and W2b of the upper layer wirings GNDU and VDDU is larger than the lower layer wiring GNDL and the line widths Wla and Wlb of the foxes, the resistance value of the power supply line can be reduced. Further, since each of the line widths wia and Wlb of the lower layer wirings GNDL and VDDL is smaller than the line width W2a of the upper layer wirings GNDU and VDDU, the space for arranging the portion of the wiring is increased. Therefore, it is easy to arrange other wirings and the like in the same layer as the lower layer wiring, and it is possible to improve the degree of freedom in layout of other wirings. 〇 In addition, each of the lower layer wirings GNDL and VDDL and the upper layer wirings GNDU and VDDU extend along the boundary of the standard cell. Therefore, a distant power line can be shared by each of the adjacent standard cells. In this way, since it is not necessary to form the power lines individually in each standard cell, it is possible to achieve high integration. According to the above method, it is possible to obtain a semiconductor device which is both high-speed and high-integrated at the same time. Further, according to the present embodiment, the metal layer of the second layer and the plane of the lower layer thereof are arranged in a high-speed unit and a high-integral unit. Therefore, the #叶叶 of the flat decoration becomes easy. The P&R (PlaceandR〇ute) configuration of this design is as follows. First, the plane of the metal layer of the first layer and the lower layer thereof are arranged to be a common arrangement of the speech rate unit and the high integration unit, and are registered in the standard unit database. On the other hand, the technical file of the through hole for accessing the terminal of the high speed unit and the through hole for accessing the terminal of the high integrated unit are prepared. In the p-news process, from the common arrangement of the registration in the standard unit database, the registration data of the P-technical file is added to design the high-speed unit and the high-integration unit. In this way, since the plane of the metal layer of the first layer and the plane of the lower layer are arranged to be common to the high-speed unit and the high-integral unit, it is not necessary to prepare a plurality of different unit configurations of the high-speed unit and the high-integral unit. The database makes design easy. 〇 In addition, as long as the metal layer of the second layer and the pattern of the upper layer are changed, a high-speed cell is formed in the high-product priority logic region HIL, and a high-integral cell is formed in the high-performance priority logic region HRL. In this manner, since the planar pattern of the metal layer of the second layer and the lower layer can be made the same in the high-speed cell* and the high-integral cell, the pattern of the semiconductor device capable of both high speed and high integration can be obtained. Design becomes easy. Further, in the present embodiment, the high-speed unit is formed in the high-product priority logic region HIL, and the high-product unit is formed in the high-performance-priority logic region HRL. 97126596 44 200915488 In the high-speed unit, the power line (10) wiring and GND wiring are allocated to the lower layer wiring, the ancestor and the upper layer wiring circle, and deleted. When compared with the single layer of the power supply material, the current path can be increased because of the increase of the current path. In addition, the high-speed integrated single s is because the power supply line (10) wiring, G·cloth:): is a single-layer, and it is expected to achieve a high integration of the # layer direction. Since the power supply line (VD D wiring, G ND wiring) is formed of a single layer, the 彳 reading line composed of the metal layer of the second layer can be freely arranged (4). For example, as shown in FIG. 2A, the signal line formed of the metal layer of the second layer can be made to cross the standard of the standard cell in which the lower layer wiring GND and VDD extend in the orthogonal direction in the plan view. The degree of freedom in forming the metal layer of the second layer is increased. τ (Embodiment 6) Referring to Fig. 24', the structure of this embodiment is different from the structure of the embodiment 5 of Fig. d, and the difference is that it has a high 矜 抑 _, 、, arrangement pair Planar arrangement of high-speed unit (4) Rotating 9" The plane of the structure of the structure is formed by the metal layer of the third layer = the extension direction of the line 0 of the 0 line, which can be used in both the high-speed unit and the high-integral unit In addition, in the structure other than the above-described embodiment of the present embodiment, the structure of the fifth embodiment shown by α is substantially the same, and therefore, Fig. 21 and Fig. 23 are the same components, and Netac is the same. According to this embodiment, the element-added phase is composed of the metal layer of the third layer, and the direction of extension ' can be the same direction in the high-speed unit and the high-product unit _ line %3, 97126596 45 200915488 For the sake of ease. In this way, it is possible to achieve an increase in the degree of integration and a reduction in the convergence time of the automatic wiring. It is to be noted that the planar arrangement of the functional elements and the wiring in the standard cells adjacent to each other in the above-mentioned Embodiments 1 to 6 t ′ can also be hidden by the boundary line of the standard cells. It is a ground wiring and power wiring that is placed between standard cells in a variety of standard cells, and is a line-symmetric structure at the cell boundary. In this way, the ground wiring and the power supply wire can be made common by using the standard unit existing above and below the unit boundary, and the unit is configured in the reduction of the arrangement or P&R (P1 and R:) Design becomes easy. Further, in the above-described fourth to sixth embodiments, the function tree described above is an element having CMOS inverted n, _D, etc., but the present invention is not limited to this, and can be applied to a CMOS discussion or calendar circuit. A counter circuit, a tri-state buffer circuit, and other functional components other than the counter circuit. The present invention is particularly advantageous for use in a body device having a plurality of standard cells arranged in series. The implementation of the Miscellaneous Treasury as disclosed herein is not considered to be used as a restrictor. The scope of the present invention is defined by the scope of the claims BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a plan view schematically showing the configuration of a semiconductor device of a semiconductor guide of the embodiment i of the present invention. Fig. 2 is a circuit diagram showing an example of a circuit configuration of functional elements formed in one of the standard cells 51a shown in Fig. 1. Fig. 3 is a plan view schematically showing the configuration of a standard unit in which one of the circuits shown in Fig. 2 is formed. Fig. 4 is a schematic cross-sectional view taken along line IV-IV of Fig. 3. Fig. 5 is a plan view schematically showing a state in which a plurality of standard cells are arranged in a semiconductor device according to a second embodiment of the present invention. Fig. 6 is a schematic cross-sectional view taken along line VI-VI of Fig. 5; Fig. 7 is a plan view showing a structure in which a fuse is formed in a standard unit in which a functional element is not formed in the structure of Fig. 5; Fig. 2 is a plan view of the structure of Fig. 5, and the upper layer wiring and the lower layer wiring of the standard unit' without the two-turn power supply line are not connected to the body multifilament, and the third embodiment of the present invention is schematically shown. The semi-conductor has a number of standard cells. Figure 10 is a schematic cross-sectional view of the X-X line of "VL" _ jgj θ 9 . Figure i 1 电路 Electrical jump circuit configuration. ·, Shi Siben (four) of the new job 4 half of the guide Figure 13 is the pepper 畋 + + 表 表 表 表 表 表 表 表 表 表 表 表 表 表 表 表The semiconductor device of the circuit is used to indicate that the electric surface structure of the electric circuit 97126596 shown in FIG. 11 and FIG. 12 is formed in the diffusion region and the element isolation region formed on the rotating substrate 47 200915488, and the gate formed on the semiconductor substrate. The electrode layer is specially designed for polycrystalline hair layers. Fig. 14 is a schematic plan view showing the planar arrangement of the semiconductor device constituting the circuit shown in Figs. 9 and 12, and mainly shows the polysilicon layer and the metal layer of the first layer thereon. Figure 15 is a schematic plan view showing the planar arrangement of the semiconductor device constituting the circuit shown in Figures u and 12, showing the metal layer of the first layer and the metal layer of the second layer of the C? 3 layers of metal. Fig. 16 is a schematic plan view showing the arrangement of the reinforcing wiring GNDS and the reinforcing wiring VDDS shown in Fig. 15. The drawing is a plan view schematically showing the structure of the SOC wafer as the semiconductor device of the fifth embodiment of the present invention. Figure 18 is a schematic plan view showing the logic region formed in the high product priority

a south-speed unit of the domain HIL, and a planar arrangement structure of the integrated unit of the high-performance-priority logic region hRL ϋ 1 , which is formed on the semiconductor substrate and the isolation region of the semiconductor substrate, and is formed on the semiconductor substrate A polycrystalline layer between the electrode layers and the like.

/ 19 π 俯 俯 用来 用来 概略 概略 概略 概略 概略 概略 概略 概略 概略 概略 概略 概略 概略 概略 概略 概略 概略 概略 概略 概略 概略 概略 概略 概略 概略 概略 概略 概略 概略 概略 概略 概略 概略 概略 概略 概略 概略 概略 概略 概略 概略 概略 概略 概略 概略 概略 概略A polycrystalline layer and a metal layer of the first layer thereon. ® 20 top view 'wire' indicates the formation of the high-product priority logic area 97126596 48 200915488, and the planar arrangement of the back-body TL formed in the high-performance priority logical region hrl, the figure shows the i a metal layer of the layer and a metal layer of the second layer thereon. Figure 21 is a schematic plan view showing that a plurality of standard cells are formed at a high speed in the logic region HIL at a high speed, and a plurality of standard cells are formed in a high performance priority logic region 戍HRL. In the case of a unit, the planar arrangement is constructed, and the towel represents the metal layer of the first layer. 1 is a schematic diagram showing, in order from the lower layer, a plurality of standard cells are formed in a high-speed-preferred region HIL in a high-speed cell, and a high-performance-priority logical region HRL is formed in a high-integral cell. In the case of a standard unit, the planar arrangement is shown in the figure, which shows the metal layer of the first layer and the metal layer of the second layer of the second layer. FIG. 23 is a schematic plan view of the standard unit in which a plurality of high-speed unit-priority regions HIL are formed in a high-speed unit from the lower layer, and the high-performance/priority logic region is a high-level integrated unit. A planar arrangement structure in which a plurality of standard cell read conditions are formed, and the metal layer of the third layer on the metal layer 2 of the first layer and the second layer and the fourth metal layer further thereon are shown. / 24 is a plan view, and the wire schematically shows the structure of the high-speed unit and the high-level unit of the semiconductor device which is the embodiment of the present invention. [Main element symbol description] 1 P-type well region 97126596 49 200915488

2 n-type well region 3 element isolation region 11a > and polar region lib source region 12 gate insulating layer 13 gate electrode layer 15 p region 21a > and pole region 21b source region 22 gate insulating layer 23 gate electrode layer 25 n+ Area 31A Interlayer insulating layer 31a Contact hole 31B Interlayer insulating layer 31b Wiring grooves 32a to 32h Wiring layer 32β' 32θ2 Signal line 33 Interlayer insulating layer 33a Via hole (passing groove) 33b Wiring groove 34a to 34d Wiring layer 97126596 50 200915488 40 Fuse 50 Semiconductor device 51 Standard cell region 51a Standard cell 52 I/O cell region A, B, C, Y terminal AR Other than logic BU1, BU2, BU3 Buffer forming region CH Contact hole GE Gate electrode layer GND Potential GNDL , GNDL1 , GNDL2 Lower layer wiring GNDS Reinforced wiring GNDU, GNDU1, GNDU2 Upper layer wiring

HIL high product priority logic region HRL high performance priority logic region IN inverter NA, NA2 NAND gate formation region NIR, NR n+ region NON non-circuit configuration region NT, NT1 to NT3, NT11 to NT21 nMOS transistor PIR, PR PR2 p+ area 97126596 51 200915488 Ρτ Configure the pitch ΡΤ, ΡΤ1 ΡΤ3, ΡΤ11 ΡΤ21 pMOS transistor

Pv Configuration pitch SD source/drain region SL1 to SL4, SLL1 to SLL4 signal line SLU1-SLU4 signal line SOC chip system SUB semiconductor substrate VDD potential VDDL lower layer wiring VDDS reinforcing wiring VDDU upper layer wiring VH1 'VH2 through hole line width

Wla, Wla丨, Wla2, Wlb, W2a, W2ai, W2a2, W2b 97126596 52

Claims (1)

200915488 VII. Patent application scope: L kinds of semiconductor devices have the standard cell of (4); such a semi-conducting financial device, which has: functional components, which are included in the above standard unit; The wire 'electrically connected to the above functional element, and having the lower layer wiring and the lower layer cloth, the wire having a portion extending along the mutually adjacent target unit (the boundary extending over the boundary; the upper layer is in a top view towel, And a semiconductor device having the lower layer wiring disposed on the inner side of the standard unit; wherein the functional element is electrically connected to the lower layer wiring via the upper layer wiring. 2. The semiconductor device according to claim 2, further comprising: an electrical connection a signal line to the functional element; and the signal line is disposed between the above-mentioned Wei element and the above-mentioned layer wiring connection portion and the extension portion of the lower layer wiring in the above-mentioned upper layer wiring. A semiconductor device according to the third aspect of the invention, wherein, in the standard unit in which the functional element is disposed, 4. The semiconductor device according to the first aspect of the invention, wherein the upper layer wiring and the lower layer wiring are connected to the standard unit not including the functional element. 97126596 53 200915488 5 The semiconductor device of claim 4, wherein the semiconductor device is further disposed to be tilted in the standard unit not including the functional element and electrically connected to the lower layer wiring. 6_ a semiconductor device, wherein the upper layer wiring has a portion extending along the boundary of the standard cell and extending over the boundary; and a line width of the extended portion of the upper layer wiring is larger than the above-mentioned G lower layer wiring a line width of an extended portion of the boundary. 7. A semiconductor device 'having a plurality of standard cells arranged; such a semiconductor device having: a function 7L, included in the standard cell; and a first power supply line' Electrically connected to the above functional elements and having underlying wiring and upper wiring; and the lower layer Each of the wire and the upper layer wiring is electrically connected to each other, and G has a portion extending along the boundary between the standard cells adjacent to each other and extending over the boundary; and the upper layer wiring is thicker than the lower layer wiring in a plan view The semiconductor device of claim 7, wherein the lower layer wiring and the upper layer wiring are electrically connected to each of the first via holes; and the first via hole of the first layer is The semiconductor device of the seventh aspect of the present invention, wherein the i-phase 1 power supply line has a reinforcement formed on the upper layer of the upper layer wiring, is provided in the semiconductor device of the above-mentioned upper layer wiring. And the above-mentioned reinforcing wiring is extended in a direction orthogonal to the above-mentioned upper layer wiring. The semiconductor device according to the ninth aspect of the patent application, wherein n is more profitable: formed on the upper layer wiring and the above reinforcing wiring Interlayer insulating layer; and upper, interlayer insulating layer, said upper layer wiring and said reinforcing wiring in a top view The father has a cross-section and having a plurality of the upper layer for terror wiring line and electrically connected to the reinforcing of the second through-hole. The semiconductor device according to claim 7, wherein the plurality of standard units include a first fresh unit and a second standard unit; and the first unit 1 includes: a first power supply line having the lower layer The wiring and the upper layer wiring; and the line L' extend on the same layer as the upper layer wiring, and extend in the direction of the lower layer wiring and the upper red layer wiring in a plan view; the above-mentioned 2 standard unit includes a second power supply line consisting only of a wiring layer extending over the same layer as the lower layer wiring; and a second line extending over the same layer as the upper layer wiring, and in the view of the above-mentioned 97126596 55 200915488 The wiring layers extend in the direction orthogonal to each other. Γ 97126596 56