TWI437665B - Semiconductor device - Google Patents

Description

Semiconductor device

The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a plurality of standard cells arranged in series.

In recent years, in the SOC (System On Chip), the layout of a standard cell library is generally used due to the large-scale circuit. In addition, as the SOC is highly functional and high-performance, the standard cell database is required to be highly integrated and high-speed. On the other hand, as the speed increases, the current consumption increases. Therefore, due to the IR-Drop (current I flows in a certain path, when the path is the resistance value R, a potential difference expressed by I×R is generated at both ends of the path. The deterioration of characteristics caused by power supply noise, etc., becomes a big problem.

In the configuration of the prior art, a standard unit such as a CMOS (Complementary Metal Oxide Semiconductor) inverter is formed as a functional element in a standard cell of a standard cell database. In this configuration, a p-channel MOS transistor (hereinafter referred to as a pMOS transistor) is formed on the surface of the n-type well region, and an n-channel MOS transistor (hereinafter referred to as an nMOS transistor) is formed on the surface of the p-type well region. . A power supply line (VDD wiring, GND wiring) is connected to each of the pMOS transistor and the nMOS transistor. Each of the power supply lines contacts the substrate, and the substrate potential is fixed, and is collectively provided in the functional elements of each standard unit.

Since the current consumption of the standard cell increases as the standard cell database is increased in speed, the current flowing through the power line also increases. In addition, a power line shared by each standard unit flows into a current of a plurality of standard cells. Therefore, since the current value flowing through the power supply line becomes large, it is necessary to consider the influence of the IR-Drop. The IR-Drop of the power line is related to the resistance value of the power line. The smaller the resistance value, the smaller the influence of IR-Drop. Therefore, the countermeasures of the prior art are to make the line width of the power supply line large.

On the other hand, with the high integration of the standard cell database, two CMOS transistors having different dipole nodes are arranged in one standard cell. In this case, the prior art has been carried out by arranging four transistors in a top view and arranging them in a vertical direction to achieve a high integration of standard cells. In such a method, the wiring between the connection transistors and the wiring for connecting the transistor and the power supply line become large, and the wiring arrangement tends to become complicated.

In addition, the prior art configuration has a plurality of standard unit arrangements, for example, disclosed in Japanese Laid-Open Patent Publication No. 2000-223575. This publication discloses that a first layer power supply line (3VDD1, 3VSS1) and a third layer power supply line (3VDD3, 3VSS3) parallel thereto are provided, and a signal line (3S2) is passed through the second layer for use as a third layer power supply. The line reinforces the first layer power line without placing a limit on the configuration of the second layer.

However, in the standard cell structure of the prior art in the above-described manner, in order to realize a high-integration and high-speed standard cell, it is necessary to simultaneously make the power supply line thicker for the high speed, and to have a plurality of structures for high integration. It is difficult to configure the transistor in the longitudinal direction. The reason for this is that since the power supply line is made thick, it is necessary to ensure the connection wiring of the respective p-electrodes of the pMOS transistor and the nMOS transistor which constitute the inverter, and the wiring portion connecting the power supply line to the transistor. difficult.

The present invention has been made in view of the above problems, and an object thereof is to provide a semiconductor device which can be simultaneously speeded up and integrated.

A semiconductor device according to an embodiment of the present invention includes a plurality of standard cells (arranged) in which a functional element and a power supply line are provided. Functional elements are included in the standard unit. The power cord is electrically connected to the functional components and has a lower layer wiring and an upper layer wiring. The lower layer wiring has a portion extending along the standard cell boundary adjacent to each other and extending over the boundary. The upper layer wiring has a portion located inside the standard cell than the lower layer wiring in a plan view. The functional element is electrically connected to the lower layer wiring via the upper layer wiring.

According to the semiconductor device of the embodiment of the present invention, the power supply line is separated into the lower layer wiring and the upper layer wiring, and when compared with the case where the power supply line is a single layer, since the current path can be increased, the speed can be increased. In addition, since the line width of the power supply line does not need to be increased, the current path can be increased, so that high integration can be achieved.

In addition, since the lower layer wiring extends along the boundary of the standard cell, the lower layer wiring can be shared between adjacent standard cells. In this manner, since it is not necessary to form the lower layer wiring individually in each of the adjacent standard cells, it is possible to achieve high integration.

In addition, since the functional element is connected to the lower layer wiring via the upper layer wiring, it is not necessary to extend the layer wiring below the standard cell boundary toward the central portion of the standard cell where the functional element is located. In this manner, since a space is formed in a portion where the lower layer wiring is extended toward the central portion of the standard cell, other wirings and the like can be disposed in the empty space, and high integration can be achieved.

In this way, it is possible to obtain a semiconductor device in which both high speed and high integration are achieved.

The above and other objects, features, aspects and advantages of the present invention will become apparent from

Hereinafter, embodiments of the present invention will be described based on the drawings.

(Embodiment 1)

Referring to FIG. 1, a semiconductor device (eg, a semiconductor wafer) 50 has, on its surface, a standard cell region 51; an I/O (Input/Output) cell region 52 disposed around the standard cell region 51; And pad (not shown), used for input and output with the outside.

The standard cell area 51 has a plurality of standard cells 51a arranged in a matrix (array). When a SOC having a standard cell database is used, a CPU (Central Processing Unit), a RAM (Random Access Memory), and a FIFO (First-In First-) are formed in the standard cell area 51. Out, first in, first out), SCSI (Small Computer System Interface), SOG (Sea Of Gate, standard gate electronic components), etc.

Referring to Fig. 2, the circuit of the functional element formed in the standard cell 51a has a part of a circuit such as a TriState buffer, and has an output section and a driver section. The output section is composed of, for example, a CMOS inverter composed of a pMOS transistor PT1 and an nMOS transistor NT1. The driver portion includes, for example, a CMOS inverter composed of a pMOS transistor PT2 and an nMOS transistor NT2, and a CMOS inverter composed of a pMOS transistor PT3 and an nMOS transistor NT3. The output of the CMOS inverter composed of the pMOS transistor PT2 and the nMOS transistor NT2 is input to the nMOS transistor NT1 of the output section. Further, the output of the CMOS inverter composed of the pMOS transistor PT3 and the nMOS transistor NT3 is input to the pMOS transistor PT1 of the output section.

When the circuit inputs "High" to the two CMOS inverters of the driver section, "High" is output from the CMOS inverter of the output section. Further, when "Low" is input to the two CMOS inverters of the driver section, "Low" is output from the CMOS inverter of the output section. In addition, when "Low" is input to the CMOS inverter composed of the pMOS transistor PT3 and the nMOS transistor NT3, and the "High" is input to the CMOS inverter composed of the pMOS transistor PT2 and the nMOS transistor NT2, The output of the CMOS inverter of the output section becomes a floating state and becomes a so-called "High impedance".

Referring to FIGS. 3 and 4, a p-type well region 1 is formed on the surface of the semiconductor substrate, and an n-type well region 2 is selectively formed on the surface in the p-type well region 1. On the surface in the p-type well region 1, nMOS transistors NT1, NT2, NT3 are formed. On the surface in the n-type well region 2, pMOS transistors PT1, PT2, PT3 are formed.

Further, along the one side of the vertical direction of the standard unit 51a (the Y direction in FIG. 3) (the boundary of the lower side in the Y direction in FIG. 3), the surface in the p-type well region 1 is formed in the lateral direction (Fig. 3 in the X direction) extended p ⁺ region 15. Further, the other side of the boundary between the vertical direction of the standard unit 51a (the Y direction in FIG. 3) (the boundary of the upper side in the Y direction in FIG. 3) is formed in the lateral direction in the surface in the n-type well region 2 (Fig. The n ⁺ region 25 extending in the X direction of 3).

In order to enable a plurality of MOS transistor formation regions, each of the p ⁺ region 15 and the n ⁺ region 25 is electrically isolated from each other, and a component such as STI (Shallow Trench Isolation) is formed on the surface of the semiconductor substrate. Isolation area 3. The STI is composed of a groove provided on the surface of the semiconductor substrate and an insulating filler filled in the groove.

Each of the nMOS transistors NT1, NT2, and NT3 has a drain region 11a and a source region 11b, a gate insulating layer 12, and a gate electrode layer 13. The drain region 11a and the source region 11b are composed of an n-type impurity region, and are formed at a distance from each other on the surface of the p-type well region 1. The gate electrode layer 13 is formed on the region sandwiched by the drain region 11a and the source region 11b via the gate insulating layer 12.

Each of the pMOS transistors PT1, PT2, PT3 has a drain region 21a and a source region 21b, a gate insulating layer 22, and a gate electrode layer 23. The drain region 21a and the source region 21b are composed of p-type impurity regions, and are formed at a distance from each other on the surface of the n-type well region 2. The gate electrode layer 23 is formed on the region sandwiched by the drain region 21a and the source region 21b via the gate insulating layer 22.

The gate electrode layer 13 of the nMOS transistor NT2 and the gate electrode layer 23 of the pMOS transistor PT2 are formed of a common conductive layer and electrically connected to each other. Further, the gate electrode layer 13 of the nMOS transistor NT3 and the gate electrode layer 23 of the pMOS transistor PT3 are formed of a common conductive layer and electrically connected to each other.

The laminated interlayer insulating layers 31A and 31B are formed on the surface of the semiconductor substrate so as to cover the MOS transistors NT1 to NT3 and PT1 to PT3. The interlayer insulating layer 31A is formed, for example, of a TEOS (Tetra-Ethyl-Ortho-Silicate) oxide film, and the interlayer insulating layer 31B is formed of, for example, SiOC, MSQ (Methyl Silses-Quioxane, methyl sesquioxane) or the like. .

The interlayer insulating layer 31B is formed with a wiring trench 31b that reaches the interlayer insulating layer 31A from the upper surface thereof, and a contact hole 31a that reaches the semiconductor substrate from the bottom of the wiring trench 31b is formed in the interlayer insulating layer 31A. Each of the wiring layers 32a to 32h which is made of, for example, a CuAl alloy (Al content is, for example, about 0.1 to 1.0%) is formed in each of the wiring grooves 31b. Further, a plug layer made of, for example, tungsten (W) is embedded in each of the contact holes 31a described above.

Further, a barrier metal layer (not shown) is formed on the side surface and the bottom surface of the contact hole 31a. The barrier metal layer is located between the plug layer and the interlayer insulating layer 31A, and between the plug layer and the semiconductor substrate. The barrier metal layer has a laminated structure of, for example, titanium (Ti) and titanium nitride (TiN).

A barrier metal layer (not shown) is also formed on the side surface and the bottom surface of the wiring trench 31b. The barrier metal layer is located between the wiring layers 32a to 32h and the interlayer insulating layer 31B, between the wiring layers 32a to 32h and the plug layer, and between the wiring layers 32a to 32h and the interlayer insulating layer 31A. The barrier metal layer is composed of, for example, tantalum (Ta).

An etching stopper layer (not shown) made of, for example, SiCN is formed between the interlayer insulating layer 31A and the interlayer insulating layer 31B.

The drain region 11a of the nMOS transistor NT1 and the drain region 21a of the pMOS transistor PT1 are electrically connected to each other by the wiring layer 32e. Further, the drain region 11a of the nMOS transistor NT2 and the drain region 21a of the pMOS transistor PT2 are electrically connected to each other by the wiring layer 32c, and are electrically connected to the gate electrode layer 13 of the nMOS transistor NT1. Further, the drain region 11a of the nMOS transistor NT3 and the drain region 21a of the pMOS transistor PT3 are electrically connected to each other by the wiring layer 32d, and are electrically connected to the gate electrode layer 23 of the pMOS transistor PT1. These wiring layers 32c and 32d correspond to signal lines for transmitting signals from the driver unit to the output section.

Further, the wiring layer 32a extends along one of the vertical direction boundaries of the standard cell 51a (the boundary of the lower side in the Y direction in FIG. 3), and extends in the lateral direction (X direction in FIG. 3) in this boundary. Further, the wiring layer 32b extends along the other side of the vertical direction of the standard cell 51a (the boundary on the upper side in the Y direction in FIG. 3), and extends in the lateral direction (X direction in FIG. 3) in this boundary. The power supply potentials (VDD, GND) can be applied to each of the wiring layers 32a, 32b extending along the standard cell boundary, and correspond to the underlying wiring of the power supply line.

Specifically, a GND potential can be applied to the wiring layer 32a, and a VDD potential can be applied to the wiring layer 32b.

The wiring layer 32a is electrically connected to the p ⁺ region 15 to fix the potential of the p-type well region 1. Further, the wiring layer 32a is branched from a portion extending in a straight line along one of the vertical direction (the Y direction in FIG. 3) (the boundary of the lower side in the Y direction in FIG. 3), and has the nMOS transistors NT2, NT3. Portions extending over the respective source regions 11b are electrically connected to the source regions 11b at the portions.

The wiring layer 32b is electrically connected to the n ⁺ region 25 to fix the potential of the n-type well region 2. Further, the wiring layer 32b is branched from a portion extending in a straight line along the other side of the vertical direction (the Y direction in FIG. 3) (the upper boundary in the Y direction in FIG. 3), and has a source at the pMOS transistor PT2. A portion extending over the region 21b is electrically connected to the source region 21b at the portion.

Further, each of the wiring regions 32g, 32h, and 32f is electrically connected to each of the source region 11b of the nMOS transistor NT1, the source region 21b of the pMOS transistor PT1, and the source region 21b of the pMOS transistor PT3.

Further, the connection between each of the wiring layers 32a to 32h and the impurity region forming the surface of the semiconductor substrate is via a plug layer formed in the contact hole 31a of the interlayer insulating layer 31A.

An interlayer insulating layer 33 made of, for example, SiOC or MSQ is formed on the interlayer insulating layer 31B so as to cover the wiring layers 32a to 32h. A wiring groove 33b is formed on the upper surface of the interlayer insulating layer 33, and a through groove 33a is formed which is formed from the bottom of the wiring groove 33b to the respective wiring layers of the lower layer. Each of the wiring layers 34a to 34d made of, for example, a CuAl alloy (Al content is, for example, about 0.1 to 1.0%) is formed so as to be embedded in the through-grooves 33a and the wiring grooves 33b.

Further, a barrier metal layer (not shown) is formed on the side surface and the bottom surface of the through groove 33a and the wiring groove 33b. The barrier metal layer is located between each of the wiring layers 34a to 34d and the interlayer insulating layer 33, between each of the vias 33a and the interlayer insulating layer 33, and between each of the vias 33a and the wiring layer of the lower layer. The barrier metal layer has a laminated structure of, for example, tantalum (Ta) and tantalum nitride (TaN).

Further, under the interlayer insulating layer 33, an etching stopper layer (not shown) made of, for example, SiCN is formed.

The source region 11b (wiring layer 32g) of the nMOS transistor NT1 and the source region 11b of the nMOS transistor NT3 are electrically connected to each other by the wiring layer 34c, and are electrically connected to the wiring layer 32a to which the GND potential can be applied. Further, the source region 21b (wiring layer 32h) of the pMOS transistor PT1 and the source region 21b (wiring layer 32f) of the pMOS transistor PT3 and the source region 21b of the pMOS transistor PT2 are electrically connected to each other by the wiring layer 34d, and It is electrically connected to the wiring layer 32b to which the VDD potential can be applied.

The wiring layer 34c is disposed on the inner side (center side) of the standard cell 51a as compared with the power line lower layer wiring layer 32a in the plan view shown in FIG. Further, in the plan view shown in FIG. 3, the wiring layer 34d is disposed on the inner side (center side) of the standard unit 51a as compared with the power line lower layer wiring layer 32b.

Further, the wiring layer 34a extends along one of the realms of the vertical direction (Y direction in FIG. 3) of the standard cell 51a (the boundary of the lower side in the Y direction in FIG. 3), and the horizontal direction in the boundary (the X direction in FIG. 3) )extend. Further, the wiring layer 34b extends along the other side of the horizontal direction (the Y direction in FIG. 3) of the standard cell 51a (the boundary of the upper side in the Y direction in FIG. 3), and the horizontal direction in the boundary (the X direction in FIG. 3) )extend. The wiring layer 34a is connected to the wiring layer 32a extending in parallel in the lower layer thereof, and the wiring layer 34b is connected to the wiring layer 32b extending in parallel in the lower layer thereof.

Further, the wiring layer 34a has a line width W2a larger than the line width W1a of the wiring layer 32a extending in parallel with the lower layer. Further, the wiring layer 34b has a line width W2b which is larger than the line width W1b of the wiring layer 32b extending in parallel with the lower layer.

In this manner, all of the wiring layers 34a, 34b, 34c, and 34d in the standard cell 51a are equivalent to the power supply potential of either of VDD and GND, and therefore correspond to the upper layer wiring of the power supply line.

Further, the electrical connection between each of the wiring layers 34a to 34d and each of the wiring layers 32a, 32b, and 32e to 32h is a portion that is buried in the through-groove 33a of each of the wiring layers 34a to 34d.

In the above manner, the source region 11b of the nMOS transistor NT1 is electrically connected to the power line lower layer wiring 32a of the GND potential via the power line upper layer wiring 34c of the GND potential. Further, the source region 21b of each of the pMOS transistors PT1, PT3 is electrically connected to the power line lower layer wiring 32b of the VDD potential via the power line upper layer wiring 34d of the VDD potential.

Further, the signal line 32c is arranged in a plan view shown in Fig. 3, which is located at a connection portion (via hole 33a) of the power line upper layer wiring 34c and the wiring layer 32g, and a straight line extending along the boundary of the standard unit 51a of the lower layer wiring 32a. Between the parts. The signal line 32d is arranged to extend in a line in the top view of FIG. Between the parts.

According to the present embodiment, the power supply line of the GND potential is separated into the lower layer wiring 32a and the upper layer wiring 34a, and the power supply line of the VDD potential is separated into the lower layer wiring 32b and the upper layer wiring 34b. Therefore, compared with the case where the power supply line is a single layer, since the current path is increased, the speed can be increased. In addition, since it is not necessary to increase the line width of the power supply line, the current path can be increased, so that high integration can be achieved.

Further, the upper layer wirings 34a and 34b have line widths W2a and W2b larger than the line widths W1a and W1b of the lower layer wirings 32a and 32b, so that the resistance value of the power source line can be reduced.

Further, the lower layer wirings 32a and 32b have line widths W1a and W1b which are smaller than the line widths W2a and W2b of the upper layer wirings 34a and 34b. Therefore, the space for emptying the wiring portion of the portion can be increased. Therefore, it is easy to arrange other wirings (for example, signal lines 32c, 32d) and the like in the same layer as the lower layer wiring, and it is possible to improve the degree of freedom in the planar arrangement of other wirings.

Further, each of the lower layer wirings 32a, 32b extends along the boundary of the standard cell 51a. Therefore, the lower layer wirings 32a and 32b can be shared between the adjacent standard cells 51a. In this manner, the lower layer wirings 32a and 32b need not be individually formed in each of the adjacent standard cells 51a, so that high integration can be achieved.

Further, each of the upper layer wirings 34a, 34b extends along the boundary of the standard unit 51a. Therefore, similarly to the above, it is not necessary to form the upper layer wirings 34a and 34b individually in each of the adjacent standard cells 51a, so that high integration can be achieved.

Further, the source region 11b of the nMOS transistor NT1 is electrically connected to the power line lower layer wiring 32a of the GND potential via the power line upper layer wiring 34c of the GND potential. Further, the source region 21b of each of the pMOS transistors PT1, PT3 is electrically connected to the power line lower layer wiring 32b of the VDD potential via the power line upper layer wiring 34d of the VDD potential. Therefore, it is not necessary to extend each of the layer wirings 32a and 32b located below the boundary of the standard cell 51a toward the central portion of the standard cell 51a at the position where the transistor is located. In this manner, since an empty space is formed in a portion where the lower layer wirings 32a and 32b are to be extended toward the central portion of the standard cell 51a, other wirings such as the signal lines 32c and 32d can be disposed in the empty space. , and can achieve high integration.

In this manner, as a result of arranging the signal lines 32c, 32d in the empty space, the obtained configuration is that the signal line 32c is located at the connection portion of the upper layer wiring 34c and the wiring layer 32g of the power supply line in the plan view shown in FIG. And between the extended portions of the boundary of the standard unit 51a of the lower layer wiring 32a. Further, the configuration obtained is that the signal line 32d is in the plan view shown in Fig. 3, between the connection portion of the power line upper layer wiring 34d and the wiring layer 32h, and between the extension of the boundary of the standard unit 51a of the lower layer wiring 32b. .

According to the above aspect, it is possible to obtain a semiconductor device which is both high speed and high in integration.

(Embodiment 2)

Referring to Fig. 5 and Fig. 6, in the present embodiment, the configuration is such that a CMOS inverter composed of an nMOS transistor NT1 and a pMOS transistor PT1 is formed in each of a plurality of standard cells 51a.

A p-type well region 1 is formed on the surface of the semiconductor substrate, and an n-type well region 2 is selectively formed on the surface in the p-type well region 1. An nMOS transistor NT1 is formed on the surface in the p-type well region 1. A pMOS transistor PT1 is formed on the surface in the n-type well region 2.

Along the boundary of the vertical direction (Y direction in FIG. 5) of the standard unit 51a (the boundary of the lower side in the Y direction in FIG. 5), the surface in the p-type well region 1 is formed in the lateral direction (FIG. 5). The X direction) extends the p ⁺ region 15. Further, along the other side of the boundary of the standard unit 51a (the Y direction in FIG. 5) (the boundary of the upper side in the Y direction in FIG. 5), the surface in the n-type well region 2 is formed in the lateral direction (FIG. 5). The n ⁺ region 25 extending in the middle X direction.

In order to enable formation regions of a plurality of MOS transistors, each of the p ⁺ region 15 and the n ⁺ region 25 is electrically isolated from each other, and an element isolation region 3 composed of, for example, STI is formed on the surface of the semiconductor substrate. The STI is composed of a groove provided on the surface of the semiconductor substrate and an insulating filler filled in the groove.

The nMOS transistor NT1 has a drain region 11a and a source region 11b, a gate insulating layer 12, and a gate electrode layer 13. The drain region 11a and the source region 11b are composed of an n-type impurity region, and are formed at a distance from each other on the surface of the p-type well region 1. The gate electrode layer 13 is formed on the region sandwiched by the drain region 11a and the source region 11b via the gate insulating layer 12.

The pMOS transistor PT1 has a drain region 21a and a source region 21b, a gate insulating layer 22, and a gate electrode layer 23. The drain region 21a and the source region 21b are composed of p-type impurity regions, and are formed at a distance from each other on the surface of the n-type well region 2. The gate electrode layer 23 is formed on the region sandwiched by the drain region 21a and the source region 21b via the gate insulating layer 22.

The gate electrode layer 13 of the nMOS transistor NT2 and the gate electrode layer 23 of the pMOS transistor PT2 are formed of a common conductive layer and electrically connected to each other.

The laminated interlayer insulating layers 31A and 31B are formed on the surface of the semiconductor substrate so as to cover the respective MOS transistors NT1 and PT1. The interlayer insulating layer 31A is formed, for example, of a TEOS oxide film, and the interlayer insulating layer 31B is formed of, for example, SiOC, MSQ, or the like. The interlayer insulating layer 31B is formed with a wiring trench 31b that reaches the interlayer insulating layer 31A from the upper surface thereof, and a contact hole 31a that reaches the semiconductor substrate from the bottom of the wiring trench 31b is formed in the interlayer insulating layer 31A. Each of the wiring layers 32a, 32b, 32e, 32g, and 32h which is made of, for example, a CuAl alloy (Al content is, for example, about 0.1 to 1.0%) is formed in each of the wiring grooves 31b. Further, a plug layer made of, for example, tungsten (W) is embedded in each of the contact holes 31a described above.

Further, a barrier metal layer (not shown) is formed on the side surface and the bottom surface of the contact hole 31a. The barrier metal layer is located between the plug layer and the interlayer insulating layer 31A, and between the plug layer and the semiconductor substrate. The barrier metal layer has a laminated structure of, for example, titanium (Ti) and titanium nitride (TiN).

A barrier metal layer (not shown) is also formed on the side surface and the bottom surface of the wiring trench 31b. The barrier metal layer is located between each of the wiring layers 32a, 32b, 32e, 32g, and 32h and the interlayer insulating layer 31B, between each of the wiring layers 32a, 32b, 32e, 32g, and 32h and the plug layer, and Each of the wiring layers 32a, 32b, 32e, 32g, and 32h is interposed between the interlayer insulating layer 31A. The barrier metal layer is composed of, for example, tantalum (Ta).

Further, an etching stopper layer (not shown) made of, for example, SiCN is formed between the interlayer insulating layer 31A and the interlayer insulating layer 31B.

The drain region 11a of the nMOS transistor NT1 and the drain region 21a of the pMOS transistor PT1 are electrically connected to each other by the wiring layer 32e. Further, the wiring layer 32a extends along one of the realms of the longitudinal direction of the standard cell 51a (the Y direction in FIG. 5) (the boundary of the lower side in the Y direction in FIG. 5), and the horizontal direction in the boundary (the X direction in FIG. 5) )extend. Further, the wiring layer 32b extends along the other side of the horizontal direction (the Y direction in FIG. 5) of the standard cell 51a (the boundary of the upper side in the Y direction in FIG. 5), and the horizontal direction in the boundary (the X direction in FIG. 5) )extend. The wiring layer 32b is electrically connected to the n ⁺ region 25 of its lower layer, by which the potential of the n-type well region 2 is fixed. Each of the wiring layers 32a, 32b extending along the boundary line of the standard cell 51a can apply a power supply potential of either of VDD and GND, and corresponds to the underlying wiring of the power supply line.

Specifically, a GND potential can be applied to the wiring layer 32a, and a VDD potential can be applied to the wiring layer 32b.

The wiring layer 32a is electrically connected to the p ⁺ region 15 of the lower layer thereof, with which the potential of the p-type well region 1 is fixed. Further, the wiring layer 32a is branched from a portion extending in a straight line along one of the vertical direction (the Y direction in FIG. 5) (the boundary of the lower side in the Y direction in FIG. 5), and has a CMOS inverter not formed. The portion of the functional unit 51a that extends over the functional component.

The wiring layer 32b is electrically connected to the n ⁺ region 25, with which the potential of the n-type well region 2 is fixed. Further, the wiring layer 32b is branched from a portion extending in a straight line along the other side of the vertical direction (the Y direction in FIG. 5) (the upper boundary in the Y direction in FIG. 5), and has a CMOS inverter not formed. The portion of the functional unit 51a that extends over the functional component.

Further, each of the wiring layers 32g and 32h is electrically connected to each of the source region 11b of the nMOS transistor NT1 and the source region 21b of the pMOS transistor PT1.

Further, each of the wiring layers 32a, 32b, 32e, 32g, and 32h and the impurity region formed on the surface of the semiconductor substrate are connected via a plug layer formed in the contact hole 31a of the interlayer insulating layer 31A.

An interlayer insulating layer 33 made of, for example, SiOC or MSQ is formed on the interlayer insulating layer 31B so as to cover the wiring layers 32a, 32b, 32e, 32g, and 32h. A wiring groove 33b is formed on the upper surface of the interlayer insulating layer 33, and a through groove 33a is formed which is formed from the bottom of the wiring groove 33b to the respective wiring layers of the lower layer. Each of the wiring layers 34c and 34d made of, for example, a CuAl alloy (having an Al content of, for example, 0.1 to 1.0%) is formed so as to be embedded in the through grooves 33a and the wiring grooves 33b.

Further, a barrier metal layer (not shown) is formed on the side surface and the bottom surface of the through groove 33a and the wiring groove 33b. The barrier metal layer is located between each of the wiring layers 34c and 34d and the interlayer insulating layer 33, between each of the vias 33a and the interlayer insulating layer 33, and between each of the vias 33a and the wiring layer of the lower layer. The barrier metal layer has a laminated structure of, for example, tantalum (Ta) and tantalum nitride (TaN).

Further, under the interlayer insulating layer 33, an etching stopper layer (not shown) made of, for example, SiCN is formed.

The source regions 11b (wiring layers 32g) of the nMOS transistors NT1 of the respective standard cells 51a are electrically connected to each other by the wiring layer 34c. Further, the wiring layer 34c is electrically connected to the branch portion of the power line lower layer wiring 32a in the standard cell 51a in which the CMOS inverter is not formed.

Further, the source regions 21b (wiring layers 32h) of the pMOS transistors PT1 of the respective standard cells 51a are electrically connected to each other by the wiring layer 34d. Further, the wiring layer 34d is electrically connected to the branch portion of the power line lower layer wiring 32b in the standard cell 51a in which the CMOS inverter is not formed.

The wiring layer 34c is disposed on the inner side (center side) of the standard cell 51a as compared with the power line lower layer wiring layer 32a in the plan view shown in FIG. Further, in the plan view shown in FIG. 5, the wiring layer 34d is disposed on the inner side (center side) of the standard cell 51a as compared with the power line lower layer wiring layer 32b.

Further, the electrical connection between each of the wiring layers 34c and 34d and each of the wiring layers 32a, 32b, 32g, and 32h is a portion that is buried in the through-groove 33a of each of the wiring layers 34c and 34d.

In the above manner, the source region 11b of the nMOS transistor NT1 is electrically connected to the power line lower layer wiring 32a of the GND potential via the power line upper layer wiring 34c of the GND potential. Further, the source region 21b of the pMOS transistor PT1 is electrically connected to the power line lower layer wiring 32b of the VDD potential via the power line upper layer wiring 34d of the VDD potential.

According to the present embodiment, each of the lower layer wirings 32a, 32b extends along the boundary of the standard cell 51a. Therefore, the lower layer wirings 32a and 32b can be shared between the adjacent standard cells 51a. In this manner, since each of the adjacent standard cells 51a does not need to form the lower layer wirings 32a and 32b individually, it is possible to achieve high integration.

Further, each of the upper layer wirings 34a, 34b extends along the boundary of the standard unit 51a. Therefore, in the same manner as described above, since each of the adjacent standard cells 51a does not need to be separately formed with the upper layer wirings 34a and 34b, it is possible to achieve high integration.

Further, the source region 11b of the nMOS transistor NT1 is electrically connected to the power line lower layer wiring 32a of the GND potential via the power line upper layer wiring 34c of the GND potential. Further, the source region 21b of the pMOS transistor PT1 is electrically connected to the power line lower layer wiring 32b of the VDD potential via the power line upper layer wiring 34d of the VDD potential. Therefore, it is not necessary to extend each of the layer wirings 32a and 32b located under the boundary of the standard cell 51a toward the central portion of the standard cell 51a where the respective transistors are located. In this manner, since the empty space is generated in a portion where the lower layer wirings 32a and 32b are to be extended toward the central portion of the standard unit 51a, the signal lines 32c, 32d and the like can be disposed in the empty space. Wiring can achieve high integration.

According to the above aspect, it is possible to obtain a semiconductor device which is both high speed and high in integration.

Further, in the second embodiment, a fuse 40 as shown in Fig. 7 may be disposed in the standard unit 51a in which a functional element (for example, a CMOS inverter) is not formed in Fig. 5 . A column composed of a plurality of standard cells 51a in which such fuses 40 are disposed may be further present in the semiconductor device. The fuse 40 may be disposed, for example, on the path of the branch portion of the power line lower layer wirings 32a, 32b.

The configuration of FIG. 7 is substantially the same as the configuration of FIGS. 5 and 6 described above, and the same reference numerals will be given to the same elements, and the description thereof will not be repeated.

In Fig. 5, the configuration is such that the standard unit 51a in which the functional elements are not formed, the power line upper layer wiring 34c is electrically connected to the lower layer wiring 32a, and the power line upper layer wiring 34d is electrically connected to the lower layer wiring 32b. However, in the second embodiment, as shown in Fig. 8, in the standard unit 51a in which the functional elements are not formed, the power line upper layer wiring 34c is not electrically connected to the lower layer wiring 32a, and the power line upper layer wiring is also provided. The 34d is not electrically connected to the lower layer wiring 32b, and the column composed of the plurality of standard cells 51a is further present in the semiconductor device.

The configuration of FIG. 8 is substantially the same as the configuration of FIGS. 5 and 6 described above, and the same reference numerals are given to the same elements, and the description thereof will not be repeated.

As shown in FIG. 5 of the second embodiment, the standard unit 51a in which the functional element is not formed, the power line upper layer wiring 34c is electrically connected to the lower layer wiring 32a, and the power line upper layer wiring 34d is electrically connected to the lower layer wiring 32b. Become the A form. Further, as shown in FIG. 8, in the standard cell 51a in which the functional element is not formed, the power line upper layer wiring 34c is not electrically connected to the lower layer wiring 32a, and the power line upper layer wiring 34d is not electrically connected to the lower layer wiring 32b. B form.

In the design stage of the semiconductor device, as long as the A form and the B form are alternated, it is possible to design a plurality of standard cells 51a having the A form as a cell array capable of high-speed operation, and can be designed to have a B form. A plurality of standard cells 51a are listed as a cell array capable of low power consumption operation.

In the standard cell 51a array having a plurality of A forms, since the operating current is supplied from the plurality of layers by the power supply line, the operation can be performed at a high speed. Further, in the plurality of standard cells 51a having the B form, the potential relationship is the lower layer wiring 32a < the upper layer wiring 34c < the upper layer wiring 34d < the lower layer wiring 32b. In this manner, a potential voltage different from the substrate potential and the source potential of the nMOS transistor NT1 or the pMOS transistor PT1 is supplied, and the threshold value (Vth) of the transistor is increased by the substrate effect, and the inclusion standard can be used. The waiting current of the circuit of the unit 51a is reduced, so that it can operate with low power consumption.

Since the A and B modes are very similar in size, they can be easily alternated, and the cell columns capable of high-speed operation and the cell columns capable of low power consumption can be easily alternated.

Further, as shown in Fig. 7, the form in which the fuse 40 is placed in the standard unit 51a in which the functional element is not formed is in the C form. By having such a C form, the test step of the product can be alternated between the high-speed operation and the low-power operation described above in accordance with the presence or absence of the fuse. With the miniaturization of semiconductor processing, the problem of variations in characteristics after wafer processing of a product is increased. However, in the test step, by selecting the standard unit 51a by the high-speed operation or the low-power consumption operation, the characteristic variation can be made small. For example, it is conceivable to shift the threshold voltage Vth of the transistor toward a lower direction, so that the operation speed is much larger than the target speed, and the power consumption can be made larger than the target power consumption. In this case, the fuse 40 is cut, and the potential relationship between the plurality of standard cells 51a having the B form is used, and the power consumption can be reduced in the target power consumption by reducing the power consumption generated by the substrate effect. .

(Embodiment 3)

This embodiment is used to realize the circuit structure shown in Fig. 2 via the configuration of the second embodiment.

Referring to Fig. 9 and Fig. 10, in the configuration of the present embodiment, for example, in three standard cells 51a arranged side by side with an inverter, the nMOS transistor NT1 and the pMOS transistor PT1 in the central standard cell 51a correspond to the figure. 2 output segment of the CMOS inverter.

Further, a CMOS inverter composed of the nMOS transistor NT2 and the pMOS transistor PT2 of the standard cell 51a on the right side in the figure of the central standard cell 51a, and the nMOS transistor NT3 and pMOS of the standard cell 51a on the left side in the figure The CMOS inverter formed by the crystal PT3 corresponds to the driver of FIG.

The gate electrode layer 13 of the nMOS transistor NT1 in the central standard cell 51a and the gate electrode layer 23 of the pMOS transistor PT1 are electrically isolated. The wiring layer 32e ₁ of the standard cell 51a on the right side is electrically connected to the gate electrode layer 13 of the central standard cell 51a, and corresponds to the signal line 32c in the first embodiment. The wiring layer 32e _{1 is} electrically connected to the drain region 11a of the nMOS transistor NT2 and the drain region 21a of the pMOS transistor PT2.

Further, the wiring layer 32e ₂ of the standard cell 51a on the left side is electrically connected to the gate electrode layer 23 of the standard cell 51a in the center, corresponding to the signal line 32d in the first embodiment. The wiring layer 32e _{2 is} electrically connected to the drain region 11a of the nMOS transistor NT3 and the drain region 21a of the pMOS transistor PT3.

The power line upper layer wiring 34c has a line width W2a larger than the line width W1a of the layer wiring 32a extending in parallel below the lower layer thereof, and the upper layer wiring 34d has a line larger than the line width W1b of the layer wiring 32b extending in parallel below the lower layer thereof. Wide W2b. In this manner, the upper layer wiring 34c has a portion located inside the standard cell 51a as compared with the lower wiring layer 32a in the plan view shown in FIG. The upper layer wiring 34c is located on the inner side of the lower layer wiring 32a, is planarly repeated in the wiring layer 32g, and is electrically connected to the wiring layer 32g via the via hole 33a.

Further, the power line upper layer wiring 34d has a portion located inside the standard cell 51a as compared with the lower wiring layer 32b in the plan view shown in FIG. The portion of the upper layer wiring 34d located further inside than the lower layer wiring 32b is planarly repeated in the wiring layer 32h, and is electrically connected to the wiring layer 32h via the via hole 33a.

Each of the power line lower layer wirings 32a, 32b linearly extends along the boundary line of the standard unit 51a, and does not have a branch portion extending from the boundary portion toward the inner side of the standard unit 51a.

According to the above, the source region 11b of the nMOS transistor NT1 is electrically connected to the power line lower layer wiring 32a of the GND potential via the power line upper layer wiring 34c of the GND potential. Further, the source region 21b of the pMOS transistor PT1 is electrically connected to the power line lower layer wiring 32b of the VDD potential via the power line upper layer wiring 34d of the VDD potential.

Also the signal layer 32e ₁ shown in the plan view of FIG. 9, the connecting portion is configured to be positioned (through hole 33a) and the upper layer wiring 34c of the wiring layer 32g power supply line between the sum of the lower layer wiring 32a. The signal line 32e ₂ is disposed between the connection portion (via hole 33a) and the lower layer wiring 32b of the power line upper layer wiring 34d and the wiring layer 32h in the plan view shown in FIG.

It is to be noted that the same components as those of the second embodiment shown in FIG. 5 and FIG. 6 are substantially the same as those of the second embodiment, and the same reference numerals will be given to the same elements, and the description thereof will not be repeated.

According to the present embodiment, the power supply line of the GND potential is separated into the lower layer wiring 32a and the upper layer wiring 34c, and the power supply line of the VDD potential is separated into the lower layer wiring 32b and the upper layer wiring 34d. Therefore, compared with the case where the power supply line is a single layer, since the current path is increased, the speed can be increased. In addition, since it is not necessary to increase the line width of the power supply line, the current path can be increased, so that high integration can be achieved.

Further, the upper layer wirings 34c and 34d have line widths W2a and W2b larger than the line widths W1a and W1b of the lower layer wirings 32a and 32b, so that the resistance value of the power source line can be reduced.

Further, the lower layer wirings 32a and 32b have line widths W1a and W1b which are smaller than the line widths W2a and W2b of the upper layer wirings 34c and 34d. Therefore, the space for the wiring arrangement of the portion can be increased. Therefore, it is easy to arrange other wirings (for example, signal lines 32e ₁ and 32e ₂ ) in the same layer as the lower layer wirings 32a and 32b, and it is possible to improve the degree of freedom in the planar arrangement of other wirings.

Further, each of the lower layer wirings 32a, 32b extends along the boundary of the standard cell 51a. Therefore, the lower layer wirings 32a and 32b can be shared between the adjacent standard cells 51a. In this manner, it is not necessary to form the lower layer wirings 32a and 32b individually in the adjacent standard cells 51a, so that high integration can be achieved.

Further, each of the upper layer wirings 34c and 34d extends along the boundary of the standard cell 51a. Therefore, in the same manner as described above, the upper layer wirings 34c and 34d need not be individually formed in the adjacent standard cells 51a, so that high integration can be achieved. .

Further, the source region 11b of each of the nMOS transistors NT1 to NT3 is electrically connected to the power line lower layer wiring 32a of the GND potential via the power line upper layer wiring 34c of the GND potential. Further, each of the source regions 21b of the pMOS transistors PT1 to PT3 is electrically connected to the power line lower layer wiring 32b of the VDD potential via the power line upper layer wiring 34d of the VDD potential. Therefore, it is not necessary to extend each of the layer wirings 32a and 32b located below the boundary of the standard cell 51a toward the central portion of the standard cell 51a where the respective transistors are located. Using this embodiment, since the wiring in the lower layer 32a, 32b of the respective standard cells should be directed to the extending portion 51a of the central portion, an empty space is generated, so the empty space can be configured to a signal line 32e _1, 32e _2, etc. Other wiring can achieve high integration.

In this manner, as a result of arranging the signal lines 32e ₁ , 32e ₂ in the empty space, the obtained configuration is that the signal line 32e _{1 is} in the top view shown in FIG. 9 and is located above the power line upper layer wiring 34c and the wiring layer 32g. The connection portion is between the lower layer wiring 32a. Further, the configuration obtained is that the signal line 32e ₂ is located between the power line upper layer wiring 34d and the wiring layer 32h and the lower layer wiring 32b in the plan view shown in FIG.

According to the above aspect, it is possible to obtain a semiconductor device which is both high speed and high in integration.

Further, in the first to third embodiments described above, an element having a CMOS inverter as a functional element is described. However, the present invention is not limited to this, and may be applied to a CMOS NAND or NOR circuit, or the like. Functional components.

(Embodiment 4)

Referring to Figures 11 and 12, the circuit of this embodiment has two input NAND gates NA1, NA2, buffers BU1, BU2, BU3 and inverter IN.

The 2-input NAND gate NA1 has the connected pMOS transistors PT11, PT12 and nMOS transistors NT11, NT12 shown in FIG. Terminals A are electrically connected to respective gates of the pMOS transistor PT11 and the nMOS transistor NT11, and terminals B are electrically connected to respective gates of the pMOS transistor PT12 and the nMOS transistor NT12.

The buffer BU1 is composed of a CMOS inverter composed of a pMOS transistor PT13 and an nMOS transistor NT13, and a CMOS inverter composed of a pMOS transistor PT14 and an nMOS transistor NT14. The buffer BU1 is constructed to be input with the output of the NAND gate NA1.

The buffer BU2 is composed of a CMOS inverter composed of a pMOS transistor PT15 and an nMOS transistor NT15, and a CMOS inverter composed of a pMOS transistor PT16 and an nMOS transistor NT16. This buffer BU2 is constructed to be input with the output of the buffer BU1.

The buffer BU3 is composed of a CMOS inverter composed of a pMOS transistor PT17 and an nMOS transistor NT17, and a CMOS inverter composed of a pMOS transistor PT18 and an nMOS transistor NT18. A terminal C is electrically connected to each of the gates of the pMOS transistor PT17 and the nMOS transistor NT17.

The 2-input NAND gate NA2 has connected pMOS transistors PT19, PT20 and nMOS transistors NT19, NT20 as shown in FIG. An output of the buffer BU2 is electrically connected to each of the gates of the pMOS transistor PT19 and the nMOS transistor NT19. The outputs of the buffer BU3 are electrically connected to the respective gates of the pMOS transistor PT20 and the nMOS transistor NT20.

The configuration of the inverter IN includes a CMOS inverter composed of a pMOS transistor PT21 and an nMOS transistor NT21. An output of the NAND gate NA2 is electrically connected to each of the gates of the pMOS transistor PT21 and the nMOS transistor NT21. In addition, the output of the inverter IN is electrically connected to the terminal Y.

Next, the planar arrangement of the semiconductor device constituting the circuits shown in Figs. 11 and 12 will be described.

Fig. 13 shows a polysilicon layer formed on a diffusion region and an element isolation region of a semiconductor substrate, and a gate electrode layer or the like formed on a semiconductor substrate. Fig. 14 mainly shows the above polycrystalline germanium layer and the metal layer of the first layer thereon. Further, Fig. 15 shows the metal layer of the first layer described above and the metal layer of the second layer and the metal layer of the third layer thereon.

Referring to Fig. 13, a NAND gate formation region NA1, NA2, a buffer formation region BU1, BU2, BU3, an inverter formation region IN, and a non-circuit region NON are formed on the surface of the semiconductor substrate SUB. . Each of these forming regions is a standard unit.

The buffer formation region BU3, the non-circuit formation region NON, and the inverter formation region IN are arranged in the X direction in the figure in this order. Further, the NAND gate formation region NA1, the buffer formation region BU1, the buffer formation region BU2, and the NAND gate formation region NA2 are arranged in the X direction in the figure in this order.

The above-described pMOS transistors PT11, PT12 and nMOS transistors NT11, NT12 are formed in the NAND gate formation region NA1. The above-described pMOS transistors PT13, PT14 and nMOS transistors NT13, NT14 are formed in the buffer formation region BU1. The above-described pMOS transistors PT15, PT16 and nMOS transistors NT15, NT16 are formed in the buffer formation region BU2. The above-described pMOS transistors PT19, PT20 and nMOS transistors NT19, NT20 are formed in the NAND gate formation region NA2.

The above-described pMOS transistors PT17, PT18 and nMOS transistors NT17, NT18 are formed in the buffer formation region BU3. The above-described pMOS transistor PT21 and nMOS transistor NT21 are formed in the formation region IN of the inverter.

A P is formed on the surface of the semiconductor substrate SUB in such a manner that the boundary between the non-circuit forming region NON and the forming region IN of the inverter in the Y direction on the upper side of the buffer forming region BU3, the non-circuit forming region NON and the inverter forming region IN in the figure. ⁺ Area PR1. Further, in a state along the NAND gate formation region NA1, the buffer formation regions BU1, BU2, and the NAND gate formation region NA2, the lower boundary in the Y direction is extended in the X direction in the drawing, on the semiconductor substrate SUB. The inner surface forms a P ⁺ region PR2.

Further, in the boundary between the buffer formation region BU3, the non-circuit formation region NON, and the formation region IN of the inverter, the lower boundary in the Y direction, that is, along the NAND gate formation region NA1, the buffer formation region BU1. The boundary between the BU2 and the NAND gate forming region NA2 in the upper side in the Y direction forms an n ⁺ region NR. The n ⁺ region NR is also formed on the surface of the semiconductor substrate SUB so as to extend along the boundary in the X direction in the drawing.

Referring to Fig. 14, a metal layer of a patterned first layer is formed on an MOS transistor via an interlayer insulating layer (not shown). The metal layer of the first layer has a power line lower layer wiring GNDL1, GNDL2 of a GND potential, a power line lower layer wiring VDDL of a VDD potential, and other signal lines SL1.

The lower layer wiring GNDL1 extends along the buffer formation region BU3, the non-circuit configuration region NON, and the upper boundary of the formation region IN of the inverter in the Y direction, and extends in the X direction in the drawing. The lower layer wiring GNDL1 is electrically connected to the lower p ⁺ region PR1 via a plurality of contact holes CH.

The lower layer wiring GNDL2 extends along the NAND gate formation region NA1, the buffer formation regions BU1, BU2, and the NAND gate formation region NA2 in the lower side in the Y direction, and extends in the X direction in the drawing. The lower layer wiring GNDL2 is electrically connected to the lower p ⁺ region PR2 via a plurality of contact holes CH.

The underlying wiring VDDL is in the boundary region of the buffer forming region BU3, the non-circuit forming region NON and the forming region IN of the inverter in the Y direction, that is, the boundary region along the NAND gate forming region NA1, the buffer forming region The boundary of the upper side in the Y direction in the map of the formation area NA2 of the BU1, BU2 and the NAND gate extends in the X direction in the drawing. The lower layer wiring VDDL is electrically connected to the n ⁺ region NR of the lower layer via a plurality of contact holes CH.

Referring to Fig. 15, a metal layer of a second layer patterned in a pattern is formed on a metal layer of a first layer via an interlayer insulating layer (not shown). The metal layer of the second layer has a power supply line upper layer wiring GNDU1, GNDU2 of a GND potential, a power supply line upper layer wiring VDDU of VDD potential, and other signal lines SL2.

The upper layer wiring GNDU1 extends along the buffer formation region BU3, the non-circuit configuration region NON, and the upper boundary of the formation region IN of the inverter in the Y direction, and extends in the X direction in the drawing. The upper layer wiring GNDU1 is electrically connected to the lower layer lower layer wiring GNDL1 via a plurality of via holes VH1. Further, the upper layer wiring GNDU1 has a line width W2a _{1 which} is larger than the line width W1a ₁ of the lower layer wiring GNDL1.

The upper layer wiring GNDU2 extends along the NAND gate formation region NA1, the buffer formation regions BU1, BU2, and the NAND gate formation region NA2 in the lower side in the Y direction, and extends in the X direction in the drawing. The upper layer wiring GNDU2 is electrically connected to the lower layer lower layer wiring GNDL2 via a plurality of via holes VH1. Further, the upper layer wiring GNDU2 has a line width W2a _{2 which} is larger than the line width W1a ₂ of the lower layer wiring GNDL2.

The upper layer wiring VDDU is in the buffer forming region BU3, the non-circuit forming region NON and the inverter forming region IN in the lower side of the Y direction, that is, the NAND gate forming region NA1, the buffer forming region. The boundary of the upper side in the Y direction in the map of the formation area NA2 of the BU1, BU2 and the NAND gate extends in the X direction in the drawing. The upper layer wiring VDDU is electrically connected to the lower layer lower layer wiring VDDL via a plurality of via holes VH1. Further, the upper layer wiring VDDU has a line width W2b larger than the line width W1b of the lower layer wiring VDDL.

A metal layer of the patterned third layer is formed on the metal layer of the second layer via an interlayer insulating layer (not shown). The metal layer of the third layer has a reinforcing wiring GNDS for reinforcing the potential of the power supply line of the GND potential, a reinforcing wiring VDDS for reinforcing the potential of the power supply line of the VDD potential, and other signal lines SL3.

Each of the reinforcing wiring GNDS and the reinforcing wiring VDDS extends in the orthogonal direction of the upper layer wirings GNDU1, GNDU2, and VDDU (that is, the Y direction in the drawing) in plan view. In the plan view, the reinforcing wiring GNDS intersects with the upper layer wirings GNDU1 and GNDU2, and is electrically connected to each of the upper layer wirings GNDU1 and GNDU2 via a plurality of (for example, four) via holes VH2 at one intersection. Further, the reinforcing wiring VDDS crosses the upper layer wiring VDDU in a plan view, and is electrically connected to the upper layer wiring VDDU via a plurality of (for example, four) via holes VH2 at one intersection.

Further, the signal lines SL1, SL2, and SL3 of the respective layers are electrically connected to each of the MOS transistors to have the circuit configuration shown in Figs. 11 and 12 . Further, in Fig. 13, a portion indicated by a hatched line is a polysilicon layer formed on a gate electrode layer or the like on a semiconductor substrate, and a portion indicated by a dot pattern is a diffusion region formed on the semiconductor substrate. The polysilicon layers or diffusion regions are electrically connected to each of the MOS transistors to form the circuit configuration shown in FIGS. 11 and 12.

Further, the connector 15 shown in FIG lower layer wiring and upper wiring GNDL1 plurality of through holes VH1 GNDU1 the arrangement pitch P _v, be the same as the arrangement pitch P _T of the transistor 13 as shown in FIG pitch. Further, the lower layer wiring is connected to the upper wiring GNDL2 plurality of through holes VH1 GNDU2 the arrangement pitch P _v, and a plurality of lower-layer wiring arrangement pitch VDDL connected with the upper wiring through hole VH1 VDDU of P _v, shown in Figure 13 has become The arrangement pitch P _T of the transistors is the same distance. In this way, the resistance value of the power supply line can be reduced, and the potentials of the lower layer wiring and the upper layer wiring can be enhanced.

Referring to Fig. 16, a plurality of reinforcing wirings GNDS and VDDS and a plurality of upper layer wirings GNDU and VDDU are arranged in a plan view to form a lattice.

Each of the plurality of reinforcing wirings GNDS is electrically connected to a plurality of upper layer wirings GNDU (including GNDU1, GNDU2) via via holes VH2. Further, each of the plurality of reinforcing wirings VDDS is electrically connected to the plurality of upper layer wirings VDDU via the via holes VH2.

According to the present embodiment, the power supply line of the GND potential is separated into the lower layer wirings GNDL1 and GNDL2 and the upper layer wirings GNDU1 and GNDU2, and the power supply line of the VDD potential is separated into the lower layer wiring VDDL and the upper layer wiring VDDU. Therefore, when compared with the case where the power supply line is a single layer, since the current path is increased, the speed can be increased. In addition, since it is not necessary to increase the line width of the power supply line, the current path can be increased, so that high integration can be achieved.

Further, each of the line widths W2a ₁ , W2a ₂ , and W2b of the upper layer wirings GNDU1, GNDU2, and VDDU is larger than the line widths W1a ₁ , W1a ₂ , and W1b of the lower layer wirings GNDL1, GNDL2, and VDDL, so that the resistance value of the power source line can be reduced. .

In addition, each of the line widths W1a ₁ , W1a ₂ , and W1b of the lower layer wirings GNDL1, GNDL2, and VDDL is smaller than the line widths W2a ₁ , W2a ₂ , and W2b of the upper layer wirings GNDU1, GNDU2, and VDDU, so the arrangement of the portion of the wiring is performed. The space used for it becomes larger. Therefore, it is easy to arrange other wirings and the like in the same layer as the lower layer wirings GNDL1, GNDL2, and VDDL, and it is possible to improve the degree of freedom in the planar arrangement of other wirings.

Further, the lower layer wirings GNDL1, GNDL2, VDDL and the upper layer wirings GNDU1, GNDU2, VDDU extend along the boundary of the standard cell, respectively. Therefore, the power lines can be shared among the adjacent standard cells. In this manner, since it is not necessary to form the power lines individually in each standard cell, high integration can be achieved.

Further, the signal line SL1 of the metal layer of the first layer is used as the standard cell internal wiring. The signal line SL2 of the metal layer of the second layer extends in the X direction in the drawing, and is used as a wiring between the standard cells to be connected by the wiring of the power supply system of the lower layer wirings GNDL1, GNDL2, and VDDL. . Further, the signal line SL3 of the metal layer of the third layer extends in the Y direction in the drawing, and is used as a wiring connecting the standard cells so as to cross the wiring of the power supply system of the lower layer wirings GNDL1, GNDL2, and VDDL. In this way, the wiring design of the P&R (Place and Route) is made easy.

In this way, it is possible to obtain a semiconductor device in which both high speed and high integration are achieved.

(Embodiment 5)

In the present embodiment, a semiconductor device having a high speed cell and a high integrated cell will be described.

Referring to Fig. 17, the SOC wafer SOC has, for example, a high integrated priority logic area HIL, a high performance priority logical area HRL, and an area other than logic AR. The high-level priority logic area HIL is formed by a high-speed unit suitable for high-speed operation. In addition, the high performance priority logic region HRL is formed by a high integrated unit suitable for a high integrated body.

Fig. 18 shows a polysilicon layer formed on a diffusion region and an element isolation region of a semiconductor substrate, and a gate electrode layer or the like formed on the semiconductor substrate. Fig. 19 mainly shows the above polycrystalline germanium layer and the metal layer of the first layer thereon. In addition, FIG. 20 mainly shows the metal layer of the first layer described above and the metal layer of the second layer thereon.

Referring to Fig. 18, both the high speed unit and the high integration unit are formed by a CMOS inverter composed of a pMOS transistor PT and an nMOS transistor NT.

In either of the high speed unit and the high integrated unit, the pMOS transistor PT has a pair of p-type source/drain regions SD, a gate insulating film (not shown), and a gate electrode layer GE. Each of the pair of p-type source/drain regions SD is formed on the surface of the semiconductor substrate SUB. The gate electrode layer GE is formed on the surface of the semiconductor substrate SUB sandwiched by a pair of p-type source/drain regions SD via a gate insulating film.

In either of the high speed unit and the high integration unit, the nMOS transistor NT has a pair of n-type source/drain regions SD, a gate insulating film (not shown), and a gate electrode layer GE. Each of the pair of n-type source/drain regions SD is formed on the surface of the semiconductor substrate SUB. The gate electrode layer GE is formed on the surface of the semiconductor substrate SUB sandwiched by the pair of n-type source/drain regions SD via a gate insulating film.

In either of the high-speed unit and the high-level unit, the gate electrode layer GE of the pMOS transistor PT and the gate electrode layer GE of the nMOS transistor NT are integrally formed and electrically connected to each other.

In either of the high-speed unit and the high-level unit, an n ⁺ region NIR is formed on the surface of the semiconductor substrate SUB along the boundary of the upper side in the Y direction in the figure of the standard cell region so as to extend in the X direction in the drawing. Further, along the boundary of the lower side in the Y direction in the figure of the standard cell region, a p ⁺ region PIR is formed on the surface of the semiconductor substrate SUB so as to extend in the X direction in the drawing.

The planar arrangement of the CMOS inverter of the high speed unit here and the planar arrangement of the CMOS inverter of the high integrated unit are the same. Further, the planar arrangement of each of the n ⁺ region NIR and the p ⁺ region PIR of the high speed unit is the same as the planar arrangement of each of the n ⁺ region NIR and the p ⁺ region PIR of the high integrated unit.

Referring to Fig. 19, a metal layer of a patterned first layer is formed on MOS transistors PT and NT via an interlayer insulating film (not shown). The metal layer of the first layer has a power supply line under the GND potential, a lower layer wiring GND, GNDL, a VDD potential power line lower layer wiring VDD, VDDL, and other signal lines SLL1, SLL2.

The lower layer wiring GNDL extends in the X direction on the lower side of the Y direction in the figure of the high-speed unit along the standard cell area. The lower layer wiring GNDL is electrically connected to the lower p ⁺ region PIR via a plurality of contact holes CH. Further, the lower layer wiring GNDL is electrically connected to one of the source/drain regions SD of the nMOS transistor NT via a plurality of contact holes CH.

The lower layer wiring VDDL extends in the X direction in the figure in the upper direction of the Y direction in the figure of the high-speed unit along the standard cell area. The lower layer wiring VDDL is electrically connected to the lower n ⁺ region NIR via a plurality of contact holes CH. Further, the lower layer wiring VDDL is electrically connected to one of the source/drain regions SD of the pMOS transistor PT via a plurality of contact holes CH.

The signal line SLL1 is electrically connected to the other of the source/drain region SD of the nMOS transistor NT and the other source/drain region SD of the pMOS transistor PT via the contact hole CH. The signal line SLL2 is electrically connected to the gate electrode layer GE via the contact hole CH.

Here, the planar arrangement of each of the lower layer wiring GNDL and the lower layer wiring VDDL of the high speed unit is the same as the plane arrangement of each of the lower integrated layer lower layer wiring GND and the lower layer wiring VDD. Further, the plane of the signal line SLL1 of the high-speed unit and the signal line SLL2 are arranged, and the plane arrangement of the signal line SLL1 and the signal line SLL2 of the high-integral unit is the same.

Referring to Fig. 20, a metal layer of a second layer patterned in a pattern is formed on a metal layer of the first layer via an interlayer insulating layer (not shown). The metal layer of the second layer has a power supply line upper layer wiring GNDU of a GND potential, a power supply line upper layer wiring VDDU of a VDD potential, and other signal lines SLU1 to SLU4.

The upper layer wiring GNDU extends along the boundary of the lower side in the Y direction in the figure of the standard cell area of the high speed cell, and extends in the X direction in the drawing. The upper layer wiring GNDU is electrically connected to the lower layer lower layer wiring GNDL via a plurality of via holes VH1. Further, the upper layer wiring GNDU has a line width W2a larger than the line width W1a of the lower layer wiring GNDL.

The upper layer wiring VDDU extends along the boundary of the upper side in the Y direction in the figure of the standard cell area of the high speed cell, and extends in the X direction in the drawing. The upper layer wiring VDDU is electrically connected to the lower layer lower layer wiring VDDL via a plurality of via holes VH1. Further, the upper layer wiring VDDU has a line width W2b larger than the line width W1b of the lower layer wiring VDDL.

Further, each of the signal lines SLU3 and SLU4 is formed in a standard unit of the high speed unit. Each of the signal lines SLU3 and SLU4 extends in the X direction in the drawing (that is, in the same direction as the direction in which the upper layers GNDU and VDDU extend in the plan view), and traverses the boundary of the standard cell area of the high-speed cell. The signal line SLU3 is electrically connected to the signal line SLL1 via the via hole VH1. In addition, the signal line SLU4 is electrically connected to the signal line SLL2 via the via hole VH1.

Further, in the standard cell of the high-integral cell, each of the signal lines SLU1, SLU2 extends in the Y direction in the drawing (that is, in a plan view, in a direction orthogonal to the extending direction of the lower layer wiring GND, VDD). The signal line SLU1 is electrically connected to the signal line SLL1 via the via hole VH1. In addition, the signal line SLU2 is electrically connected to the signal line SLL2 via the via hole VH1.

Further, each of the signal lines SLU1 and SLU2 also extends in the Y direction in the figure, and traverses the boundary of the standard cell area of the high integrated unit.

Next, a plurality of standard units for each of the high-product priority logical region HIL and the high-performance priority logical region HRL will be described.

Figure 21 shows the metal layer of the first layer. Figure 22 shows the metal layer of the first layer and the metal layer of the second layer thereon. Fig. 23 shows the metal layers of the first layer and the second layer, the metal layer of the third layer thereon, and the fourth metal layer thereon.

Referring to Fig. 21, even in the case of a plurality of standard cells, as in the case of a single standard cell, the planar arrangement of each of the metal layers of the first layer and the layers below it is in the high-speed cell and the high-product The units are all the same.

Referring to Fig. 22 and Fig. 23, even in the case of a plurality of standard cells, as in the case of a single standard cell, the metal layer of the second layer and the layers thereon (for example, the third and fourth metal layers) Each of the planar arrangement structures differs between the high speed unit and the high integrated unit.

In the high-speed cell, the upper layer wirings GNDU and VDDU are composed of the metal layers of the second layer, and are formed to extend along the boundary of the standard cell with a line width smaller than the line width of the lower layer wirings GNDL and VDDL. Further, the signal line SLU composed of the metal layer of the second layer extends in the same direction as the extending direction of the lower layer wirings GNDL and VDDL.

On the other hand, in the high integrated unit, the upper layer wirings GNDU and VDDU are not provided by the metal layer of the second layer. Further, the signal line SLU composed of the metal layer of the second layer extends in a direction orthogonal to the extending direction of the lower layer wirings GNDL and VDDL.

In the high speed unit, as shown in FIG. 22, the upper layer wirings GNDU and VDDU are formed of the metal layers of the second layer. Therefore, the signal line SLU composed of the metal layer of the second layer cannot be extended to the boundary between the standard cell on the upper side in the Y direction and the standard cell on the lower side in the figure. Therefore, in the high-speed unit, as shown in FIG. 23, when the metal layer of the third layer and the metal layer of the fourth layer are not used, the elements in the standard cells adjacent to each other in the Y direction cannot be made to each other, and In the figure, the components in the standard cells adjacent in the X direction are electrically connected to each other.

That is, by arranging the signal line SL3 composed of the metal layer of the third layer so as to cross the boundary between the standard cells above and below the Y direction in the drawing, it is possible to electrically generate the elements in the standard cells adjacent to each other in the Y direction in the drawing. connection. Further, by arranging the signal line SL4 composed of the metal layer of the fourth layer so as to cross the boundary between the standard cells on the left and right in the X direction in the drawing, it is possible to electrically connect the elements in the standard cells adjacent in the X direction in the drawing. .

On the other hand, in the high integrated unit, as shown in Fig. 22, the upper layer wirings GNDU and VDDU are not provided by the metal layer of the second layer. Therefore, the signal line SLU composed of the metal layer of the second layer can be extended to the boundary between the standard cells adjacent to each other in the Y direction in the drawing. Therefore, in the high-mass unit, as shown in FIG. 23, even if the metal layer of the fourth layer is not used, the metal layer of the second layer and the metal layer of the third layer can be adjacent to each other in the Y direction in the drawing. The components in the standard cell are electrically connected to each other and between the components in the standard cell adjacent in the X direction of the drawing.

That is, by arranging the signal line SLU composed of the metal layer of the second layer so as to cross the boundary between the standard cells above and below the Y direction in the figure, it is possible to cause the elements in the standard cells adjacent to each other in the Y direction in the drawing to be generated. Electrical connections. Further, by arranging the signal line SL3 composed of the metal layer of the third layer so as to straddle the boundary between the standard cells on the left and right in the X direction in the drawing, it is possible to generate electrical components between the elements in the standard cells adjacent in the X direction in the drawing. connection.

According to the present embodiment, in the standard cell of the high-speed cell, the power supply line of the GND potential is separated into the lower layer wiring GNDL and the upper layer wiring GNDU, and the power supply line of the VDD potential is separated into the lower layer wiring VDDL and the upper layer wiring VDDU. Therefore, when compared with the case where the power supply line is a single layer, since the current path is increased, the speed can be increased. In addition, since it is not necessary to increase the line width of the power supply line, the current path can be increased, so that high integration can be achieved.

Further, since each of the line widths W2a and W2b of the upper layer wirings GNDU and VDDU is larger than the line widths W1a and W1b of the lower layer wirings GNDL and VDDL, the resistance value of the power supply line can be reduced.

In addition, since each of the line widths W1a and W1b of the lower layer wirings GNDL and VDDL is smaller than the line widths W2a and W2b of the upper layer wirings GNDU and VDDU, the space for arranging the partial wirings becomes large. Therefore, it is easy to arrange other wirings and the like in the same layer as the lower layer wiring, and it is possible to improve the degree of freedom in the planar arrangement of other wirings.

Further, each of the lower layer wirings GNDL, VDDL and the upper layer wirings GNDU, VDDU extends along the boundary of the standard cell. Therefore, the power lines can be shared among the adjacent standard cells. In this manner, since it is not necessary to form the power lines individually in each standard cell, high integration can be achieved.

According to the above method, it is possible to obtain a semiconductor device which is both high speed and high integrated.

Further, according to the present embodiment, the planar arrangement of the metal layer of the first layer and the lower layer thereof is common to the high-speed unit and the high-integral unit. Therefore, the design of the floor plan becomes easy. The P&R (Place and Route) process of this design is as follows.

First, the plane of the metal layer of the first layer and the lower layer thereof are arranged as a common arrangement of the high-speed unit and the high-integral unit, and are registered in the standard unit database. On the other hand, a technical file for accessing a through hole for terminal access of a high speed unit and a through hole for accessing a terminal of a high integrated unit is prepared.

In the P&R process, the registration data of the P&R technical file is added from the common arrangement registered in the standard unit database, thereby designing the high-speed unit and the high-integrated unit.

In this way, since the plane of the metal layer of the first layer and the plane of the lower layer are arranged to be common to the high-speed unit and the high-integral unit, it is not necessary to prepare a plurality of different unit configurations of the high-speed unit and the high-integral unit. The database makes design easy.

Further, by changing the pattern of the metal layer of the second layer and the pattern of the upper layer, a high-speed cell is formed in the high-product-first logic region HIL, and a high-integral cell is formed in the high-performance-priority logic region HRL. In this manner, since the planar pattern of the metal layer of the second layer and the lower layer can be made the same in the high-speed cell and the high-integral cell, the pattern design of the semiconductor device capable of both high speed and high integration can be achieved. It becomes easy.

Further, in the present embodiment, the high-speed unit is formed in the high-product-first logical region HIL, and the high-integral unit is formed in the high-performance-priority logical region HRL. In the high speed unit, the power supply lines (VDD wiring, GND wiring) are allocated to the lower layer wirings GNDL, VDDL, and the upper layer wirings GNDU, VDDU. Therefore, when compared with the case where the power supply line is a single layer, since the current path is increased, the speed can be increased.

Further, in the high-integral unit, since the power supply line (VDD wiring, GND wiring) is a single layer, it is possible to achieve a high integration in the lamination direction. Further, since the power supply line (VDD wiring, GND wiring) is formed of a single layer, the signal line composed of the metal layer of the second layer can be freely arranged than the high-speed unit. For example, as shown in FIG. 20, the signal line formed of the metal layer of the second layer can be made to traverse the boundary of the standard cell extending in the direction orthogonal to the lower layer wiring GND and VDD in the plan view. In this way, the degree of freedom in the planar arrangement of the signal lines composed of the metal layers of the second layer can be made high.

(Embodiment 6)

Referring to Fig. 24, the structure of the present embodiment, when compared with the structure of the fifth embodiment shown in Figs. 21 to 23, is different in that the planar arrangement having the high integrated unit is relatively rotated 90 in the plane arrangement of the high speed unit. °The structure of °.

In this manner, the direction in which the signal line SL3 composed of the metal layer of the third layer extends can be in the same direction in both the high speed unit and the high integrated unit.

It is to be noted that the same components as those of the fifth embodiment shown in FIG. 21 to FIG. 23 are substantially the same as those of the fifth embodiment, and the same reference numerals will be given to the same elements, and the description thereof will not be repeated.

According to the present embodiment, since the direction in which the signal line SL3 composed of the metal layer of the third layer is formed can be in the same direction in the high-speed unit and the high-integral unit, the wiring design becomes easy. In this way, it is possible to achieve an improvement in the degree of integration and a shortening of the convergence time of the automatic wiring.

Further, in the above-described first to sixth embodiments, the planar arrangement of the functional elements and the wirings in the standard cells adjacent to each other in pairs may have a line symmetry structure with respect to the boundary line of the standard cells. In particular, between a plurality of standard cells, the ground wiring and the power wiring disposed at the boundary of the standard cell become a line-symmetric structure at the cell boundary. In this way, the ground wiring and the power wiring can be made common by using the standard cells existing above and below the cell boundary, and the layout reduction or P&R (Place and Route) makes the unit configuration design easy.

Further, in the above-described fourth to sixth embodiments, the functional elements described above are elements having a CMOS inverter, NAND, etc., but the present invention is not limited to this, and can be applied to CMOS NAND or NOR circuits, positive and negative. Device circuit, tri-state buffer circuit, and other functional components.

The invention is particularly advantageous for use in semiconductor devices having a plurality of standard cells arranged in series.

All of the embodiments disclosed herein are for illustrative purposes only and are not to be considered as limiting. The scope of the present invention is defined by the scope of the claims and the scope of the claims.

1. . . P-well area

2. . . N-well area

3. . . Component isolation area

11a. . . Bungee area

11b. . . Source area

12. . . Brake insulation

13. . . Gate electrode layer

15. . . p ⁺ area

21a. . . Bungee area

21b. . . Source area

twenty two. . . Brake insulation

twenty three. . . Gate electrode layer

25. . . n ⁺ area

31A. . . Interlayer insulation

31a. . . Contact hole

31B. . . Interlayer insulation

31b. . . Wiring trench

32a~32h. . . Wiring layer

32e ₁ , 32e ₂ . . . Signal line

33. . . Interlayer insulation

33a. . . Through hole

33b. . . Wiring trench

34a~34d. . . Wiring layer

40. . . Melt line

50. . . Semiconductor device

51. . . Standard cell area

51a. . . Standard unit

52. . . I/O unit area

A, B, C, Y. . . Terminal

AR. . . Area other than logic

BU1, BU2, BU3. . . Buffer forming area

CH. . . Contact hole

GE. . . Gate electrode layer

GND. . . Potential

GNDL, GNDL1, GNDL2. . . Lower wiring

GNDS. . . Reinforced wiring

GNDU, GNDU1, GNDU2. . . Upper wiring

HIL. . . High product priority logic area

HRL. . . High performance priority logic area

IN. . . inverter

NA1, NA2. . . NAND gate forming region

NIR, NR. . . n ⁺ area

NON. . . Non-circuit forming area

NT, NT1~NT3, NT11~NT21. . . nMOS transistor

PIR, PR1, PR2. . . p ⁺ area

P _T . . . Configuration spacing

PT, PT1~PT3, PT11~PT21. . . pMOS transistor

Pv. . . Configuration spacing

SD. . . Source/drain region

SL1~SL4, SLL1~SLL4. . . Signal line

SLU1~SLU4. . . Signal line

SOC. . . Wafer system

SUB. . . Semiconductor substrate

VDD. . . Potential

VDDL. . . Lower wiring

VDDS. . . Reinforced wiring

VDDU. . . Upper wiring

VH1, VH2. . . Through hole

W1a, W1a ₁ , W1a ₂ , W1b, W2a, W2a ₁ , W2a ₂ , W2b. . . Line width

Fig. 1 is a plan view schematically showing the structure of a semiconductor device according to a first embodiment of the present invention.

Fig. 2 is a circuit diagram showing an example of a circuit configuration of functional elements formed in one of the standard cells 51a shown in Fig. 1.

Fig. 3 is a plan view schematically showing the configuration of a standard unit in which one of the circuits shown in Fig. 2 is formed.

Fig. 4 is a schematic cross-sectional view taken along line IV-IV of Fig. 3.

Fig. 5 is a plan view schematically showing a state in which a plurality of standard cells are arranged in a semiconductor device according to a second embodiment of the present invention.

Fig. 6 is a schematic cross-sectional view taken along line VI-VI of Fig. 5;

Fig. 7 is a plan view schematically showing a structure in which a fuse is formed in a standard unit in which a functional element is not formed in the structure of Fig. 5;

Fig. 8 is a plan view schematically showing a configuration in which the upper layer wiring and the lower layer wiring of the power supply line are not connected in the standard unit in which the functional elements are not formed in the configuration of Fig. 5;

FIG. 9 is a plan view schematically showing a state in which a plurality of standard cells are arranged in the semiconductor device according to the third embodiment of the present invention.

Fig. 10 is a schematic cross-sectional view taken along line X-X of Fig. 9.

Figure 11 is a circuit diagram showing the circuit configuration of a semiconductor device according to a fourth embodiment of the present invention.

Figure 12 is a circuit diagram for showing the circuit diagram shown in Figure 11 at the transistor level.

Figure 13 is a schematic plan view showing the planar arrangement of the semiconductor device constituting the circuit shown in Figures 11 and 12, showing the diffusion region and the element isolation region formed on the semiconductor substrate, and the gate formed on the semiconductor substrate. A polycrystalline layer of an electrode layer or the like.

Fig. 14 is a schematic plan view showing a planar arrangement of a semiconductor device constituting the circuit shown in Fig. 11 and Fig. 12, mainly showing a polysilicon layer and a metal layer of the first layer thereon.

Figure 15 is a schematic plan view showing the planar arrangement of the semiconductor device constituting the circuit shown in Figures 11 and 12, showing the metal layer of the first layer and the metal layer and the third layer of the second layer thereon. The metal layer.

Fig. 16 is a schematic plan view showing the arrangement of the reinforcing wiring GNDS and the reinforcing wiring VDDS shown in Fig. 15.

Fig. 17 is a plan view schematically showing the structure of an SOC wafer as a semiconductor device according to a fifth embodiment of the present invention.

Figure 18 is a schematic plan view showing a planar arrangement of a high-speed cell formed in a high-product-first logic region HIL and a high-level integrated cell formed in a high-performance-preferred logic region HRL, which is shown formed on a semiconductor substrate. The diffusion region and the element isolation region, and the polysilicon layer formed on the semiconductor substrate or the gate electrode layer.

Figure 19 is a schematic plan view showing a planar arrangement of a high-speed cell formed in a high-product priority logic region HIL and a high-level integrated cell formed in a high-performance-preferred logic region HRL, which mainly shows a polysilicon layer And the metal layer of the first layer thereon.

Fig. 20 is a schematic plan view showing the planar arrangement of the high-speed unit formed in the high-product-first logical region HIL and the high-integral unit formed in the high-performance-priority logical region HRL, and the first layer is shown. a metal layer and a metal layer of the second layer thereon.

21 is a schematic plan view showing a case where a plurality of standard cells are formed in a high-speed-priority logic region HIL in a high-speed cell, and a plurality of standard cells are formed in a high-performance-priority logic region HRL in a high-integral unit. The planar layout of the time, the metal layer of the first layer is shown in the figure.

FIG. 22 is a schematic plan view showing, in order from the lower layer, a plurality of standard cells formed in a high-speed-priority logic region HIL in a high-speed cell, and a plurality of high-performance-preferred logic regions HRL in a high-integral cell. In the case of a standard cell, the planar arrangement is shown in the figure, which shows the metal layer of the first layer and the metal layer of the second layer thereon.

FIG. 23 is a schematic plan view showing, in order from the lower layer, a plurality of standard cells formed in a high-speed-priority logic region HIL in a high-speed cell, and a plurality of high-performance-preferred logic regions HRL in a high-integral cell. In the case of a standard cell, the planar arrangement structure shows the metal layers of the first and second layers, the metal layer of the third layer thereon, and the fourth metal layer thereon.

Fig. 24 is a plan view schematically showing the structure of a device having both a high-speed unit and a high-level unit of the semiconductor device according to the sixth embodiment of the present invention.

1. . . P-well area

2. . . N-well area

11a. . . Bungee area

11b. . . Source area

13. . . Gate electrode layer

15. . . p ⁺ area

21a. . . Bungee area

21b. . . Source area

twenty three. . . Gate electrode layer

25. . . n ⁺ area

31a. . . Contact hole

32a~32h. . . Wiring layer

33a. . . Through hole

34a~34d. . . Wiring layer

51a. . . Standard unit

NT1, NT2, NT3. . . nMOS transistor

PT1, PT2, PT3. . . pMOS transistor

W1a, W1b, W2a, W2b. . . Line width

Claims (9)

A semiconductor device having a plurality of standard cells arranged; such a semiconductor device comprising: a functional element included in the standard unit; and a power supply line electrically connected to the functional element and having a lower layer a wiring and an upper layer wiring; and the lower layer wiring has a portion extending along the boundary between the standard cells adjacent to each other and extending over the boundary; wherein the upper layer wiring has a lower side wiring than the lower layer wiring on the inner side of the standard unit a portion; the functional element is electrically connected to the lower layer wiring via the upper layer wiring; and further includes a signal line electrically connected to the functional element; and the signal line is disposed in the top view to be located between the functional element and the upper layer wiring The connection portion is between the portion extending over the above-described boundary of the lower layer wiring. The semiconductor device according to claim 1, wherein the upper layer wiring and the lower layer wiring are connected to each other in the standard cell in which the functional element is disposed. The semiconductor device according to claim 1, wherein the upper layer wiring and the lower layer wiring are connected to each other in the standard unit not including the functional element. A semiconductor device as claimed in claim 3, wherein Further, the fuse is provided in the standard unit not including the functional element, and is electrically connected to the lower layer wiring. The semiconductor device according to any one of claims 1 to 3, wherein the upper layer wiring has a portion extending along the boundary of the standard unit and extending over the boundary; and extending over the boundary of the upper layer wiring The line width of the portion is greater than the line width of the extended portion of the above-mentioned lower layer wiring. A semiconductor device having a plurality of standard cells arranged; such a semiconductor device comprising: a functional element included in the standard cell; and a first power supply line electrically connected to the functional component and having a lower layer wiring and The upper layer wiring and the upper layer wiring are electrically connected to each other, and have a portion extending along the boundary of the standard unit adjacent to each other and extending over the boundary; the upper layer wiring has a top view The lower layer wiring is a thick line width; the plurality of standard cells include a first standard unit and a second standard unit; and the first standard unit includes: the first power supply line, the lower layer wiring and the upper layer wiring; a signal line extending over the same layer as the upper layer wiring, and extending in the same direction as the lower layer wiring and the upper layer wiring in a plan view; The second standard unit includes a second power supply line formed of only a wiring layer extending over the same layer as the lower layer wiring, and a second signal line extending over the same layer as the upper layer wiring, and a plan view The middle extends in a direction orthogonal to the wiring layer. The semiconductor device of claim 6, wherein the lower layer wiring and the upper layer wiring are electrically connected by a plurality of first via holes; and the plurality of first via holes and the transistor constituting the functional element The configuration is configured with the same pitch. The semiconductor device according to claim 6 or 7, wherein the first power supply line has a reinforcing wiring formed on an upper layer of the upper wiring; and the reinforcing wiring extends in a direction orthogonal to the upper wiring in a plan view. . The semiconductor device of claim 8, further comprising: an interlayer insulating layer formed between the upper layer wiring and the reinforcing wiring; and the interlayer insulating layer, the upper layer wiring and the reinforcing wiring in a plan view One of the intersecting portions has a plurality of second through holes for electrically connecting the upper layer wiring and the reinforcing wiring.