JP4820542B2 - 半導体集積回路 - Google Patents
半導体集積回路 Download PDFInfo
- Publication number
- JP4820542B2 JP4820542B2 JP2004286576A JP2004286576A JP4820542B2 JP 4820542 B2 JP4820542 B2 JP 4820542B2 JP 2004286576 A JP2004286576 A JP 2004286576A JP 2004286576 A JP2004286576 A JP 2004286576A JP 4820542 B2 JP4820542 B2 JP 4820542B2
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- Japan
- Prior art keywords
- power supply
- supply wiring
- wiring
- cell
- vias
- Prior art date
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- 239000004065 semiconductor Substances 0.000 title claims description 55
- 238000000034 method Methods 0.000 description 13
- 238000013461 design Methods 0.000 description 10
- 230000008569 process Effects 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000007423 decrease Effects 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 230000003014 reinforcing effect Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
- H01L27/11803—Masterslice integrated circuits using field effect technology
- H01L27/11807—CMOS gate arrays
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
図1及び図2は、本発明の第1の実施形態の半導体集積回路の電源配線構造を示す。
図3は、セル電源配線20に接続するビア25の個数が3つの場合の電源配線の断面構造を示す。ビア25の個数が3つであるので、2つの場合に比して、セル電源配線20の各ビア25との接続箇所における単位断面積当りの電流密度を大きく低減できると共に、この電流密度の低減により、セル電源配線20の配線幅を有効に縮小することが可能である。
前記実施形態では、補助電源配線30の上層に垂直方向電源配線40を配置し、更にその上層に水平方向電源配線50を配置した例を示したが、本変形例では、図4に示すように、補助電源配線30の上層に水平方向電源配線40を配置し、更にその上層に垂直方向電源配線50を配置した例を示している。
図6は本発明の第2の実施形態の半導体集積回路の電源配線構造を示す。
図7は本発明の第3の実施形態の半導体集積回路の電源配線構造を示す。
次に、本発明の第4の実施形態を図9に基づいて説明する。
続いて、本発明の第5の実施形態を図10に基づいて説明する。
次に、本発明の第6の実施形態を図11に基づいて説明する。
15 ビア
20 セル電源配線
30 補助電源配線
35、45 ビア
40、50 上層電源配線
60 セル
70 セル内の半導体デバイス
80 セルグランド配線
90 セル内電源配線
Claims (5)
- セルを複数個備えた半導体集積回路であって、
前記各セルに形成されたセル電源配線と、
前記セル電源配線よりも上層に配置された補助電源配線とを備え、
前記セル電源配線と前記補助電源配線とは、2つのビアにより接続されていて、
前記補助電源配線から前記2つのビアを介して前記セル電源配線に電源供給され、
前記補助電源配線の上層には、上層電源配線が配置され、
前記上層電源配線と前記補助電源配線とは、1つ以上のビアにより接続されていて、
前記上層電源配線から前記1つ以上のビアを介して前記補助電源配線に電源供給され、
前記セル電源配線と前記補助電源配線とを接続する2つのビアは、前記補助電源配線と前記上層電源配線とを接続する1つのビアを中心として、相互に反対方向に所定間隔隔てて配置されている
ことを特徴とする半導体集積回路。 - 前記請求項1に記載の半導体集積回路において、
前記補助電源配線は、その配線幅が、前記セル電源配線の配線幅よりも太い
ことを特徴とする半導体集積回路。 - 前記請求項1及び2の何れか1項に記載の半導体集積回路において、
前記上層電源配線は、格子状に配置された格子状電源配線である
ことを特徴とする半導体集積回路。 - 前記請求項1〜3の何れか1項に記載の半導体集積回路において、
前記セル電源配線と前記補助電源配線とを接続する2つのビア間には、複数個のセルが位置している
ことを特徴とする半導体集積回路。 - 前記請求項1〜4の何れか1項に記載の半導体集積回路において、
前記セル電源配線と前記補助電源配線とを接続する2つのビア間には、前記各セルの内部に配置され且つ前記セル電源配線に接続されたセル内電源配線が複数本位置している
ことを特徴とする半導体集積回路。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004286576A JP4820542B2 (ja) | 2004-09-30 | 2004-09-30 | 半導体集積回路 |
US11/229,503 US7514795B2 (en) | 2004-09-30 | 2005-09-20 | Semiconductor integrated circuit having improved power supply wiring |
US12/397,883 US7932610B2 (en) | 2004-09-30 | 2009-03-04 | Semiconductor integrated circuit having improved power supply wiring |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004286576A JP4820542B2 (ja) | 2004-09-30 | 2004-09-30 | 半導体集積回路 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2006100673A JP2006100673A (ja) | 2006-04-13 |
JP4820542B2 true JP4820542B2 (ja) | 2011-11-24 |
Family
ID=36124723
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004286576A Expired - Fee Related JP4820542B2 (ja) | 2004-09-30 | 2004-09-30 | 半導体集積回路 |
Country Status (2)
Country | Link |
---|---|
US (2) | US7514795B2 (ja) |
JP (1) | JP4820542B2 (ja) |
Families Citing this family (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5194461B2 (ja) * | 2007-01-30 | 2013-05-08 | 富士通セミコンダクター株式会社 | 電流密度制限チェック方法及び電流密度制限チェック装置 |
US8063415B2 (en) | 2007-07-25 | 2011-11-22 | Renesas Electronics Corporation | Semiconductor device |
JP5293939B2 (ja) * | 2007-07-25 | 2013-09-18 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
US8438519B2 (en) * | 2008-03-04 | 2013-05-07 | Texas Instruments Incorporated | Via-node-based electromigration rule-check methodology |
JP2010021349A (ja) * | 2008-07-10 | 2010-01-28 | Nec Electronics Corp | 半導体記憶装置 |
US8566776B2 (en) * | 2008-11-13 | 2013-10-22 | Qualcomm Incorporated | Method to automatically add power line in channel between macros |
JP2010283269A (ja) * | 2009-06-08 | 2010-12-16 | Renesas Electronics Corp | 半導体装置 |
US8164190B2 (en) * | 2009-06-25 | 2012-04-24 | International Business Machines Corporation | Structure of power grid for semiconductor devices and method of making the same |
KR101040851B1 (ko) * | 2010-03-23 | 2011-06-14 | 삼성모바일디스플레이주식회사 | 터치 스크린 패널 |
FR2972079B1 (fr) | 2011-02-25 | 2014-01-03 | St Microelectronics Sa | Circuit intégré numérique |
JP5820412B2 (ja) * | 2013-03-08 | 2015-11-24 | 株式会社東芝 | 半導体集積回路 |
US9786663B2 (en) * | 2013-08-23 | 2017-10-10 | Qualcomm Incorporated | Layout construction for addressing electromigration |
US9972624B2 (en) | 2013-08-23 | 2018-05-15 | Qualcomm Incorporated | Layout construction for addressing electromigration |
US9887209B2 (en) | 2014-05-15 | 2018-02-06 | Qualcomm Incorporated | Standard cell architecture with M1 layer unidirectional routing |
US9793211B2 (en) * | 2015-10-20 | 2017-10-17 | Taiwan Semiconductor Manufacturing Co., Ltd. | Dual power structure with connection pins |
JP6966686B2 (ja) | 2016-10-21 | 2021-11-17 | 株式会社ソシオネクスト | 半導体装置 |
US10811357B2 (en) * | 2017-04-11 | 2020-10-20 | Samsung Electronics Co., Ltd. | Standard cell and an integrated circuit including the same |
US10664641B2 (en) * | 2017-11-30 | 2020-05-26 | Taiwan Semiconductor Manufacturing Company Ltd. | Integrated device and method of forming the same |
US11444073B2 (en) | 2020-10-27 | 2022-09-13 | Taiwan Semiconductor Manufacturing Co., Ltd. | Power distribution network |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE3306439C2 (de) * | 1983-02-24 | 1987-01-02 | Phoenix Ag, 2100 Hamburg | Verwendung eines Schmelzklebers zum Verbinden von Artikeln aus EPDM |
JPS6114248A (ja) * | 1984-06-30 | 1986-01-22 | Mitsubishi Petrochem Co Ltd | 熱可塑性樹脂組成物 |
JPH03145743A (ja) * | 1989-10-31 | 1991-06-20 | Hitachi Ltd | 半導体集積回路装置 |
JP3101077B2 (ja) * | 1992-06-11 | 2000-10-23 | 株式会社日立製作所 | 半導体集積回路装置 |
JPH0846049A (ja) | 1994-08-02 | 1996-02-16 | Hitachi Ltd | 集積回路の配線方法及びその製造方法並びにそれを用いた集積回路 |
JPH1056162A (ja) | 1996-05-24 | 1998-02-24 | Toshiba Corp | 半導体集積回路およびその設計方法 |
JPH1145979A (ja) | 1997-05-26 | 1999-02-16 | Toshiba Corp | 半導体集積回路装置及び電源配線の敷設方法 |
JP4228418B2 (ja) * | 1998-07-30 | 2009-02-25 | 沖電気工業株式会社 | 半導体装置 |
US6031293A (en) * | 1999-04-26 | 2000-02-29 | United Microelectronics Corporation | Package-free bonding pad structure |
US6630532B1 (en) * | 1999-09-15 | 2003-10-07 | Kraton Polymer U.S. Llc | Modified styrenic block copolymer compounds having improved elastic performance |
JP4748867B2 (ja) * | 2001-03-05 | 2011-08-17 | パナソニック株式会社 | 集積回路装置 |
JP2004165453A (ja) * | 2002-11-13 | 2004-06-10 | Fujitsu Ltd | 半導体集積回路、電源配線方法、及びコンピュータプログラム |
EP1426411A1 (en) * | 2002-12-06 | 2004-06-09 | KRATON Polymers Research B.V. | Styrenic block copolymer compositions to be used for the manufacture of transparent, gel free films |
-
2004
- 2004-09-30 JP JP2004286576A patent/JP4820542B2/ja not_active Expired - Fee Related
-
2005
- 2005-09-20 US US11/229,503 patent/US7514795B2/en active Active
-
2009
- 2009-03-04 US US12/397,883 patent/US7932610B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US20090166883A1 (en) | 2009-07-02 |
JP2006100673A (ja) | 2006-04-13 |
US7932610B2 (en) | 2011-04-26 |
US20060071319A1 (en) | 2006-04-06 |
US7514795B2 (en) | 2009-04-07 |
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