KR20070032624A - 종래의 종단을 갖는 수퍼 접합 장치를 제조하는 방법 - Google Patents

종래의 종단을 갖는 수퍼 접합 장치를 제조하는 방법 Download PDF

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Publication number
KR20070032624A
KR20070032624A KR1020067014535A KR20067014535A KR20070032624A KR 20070032624 A KR20070032624 A KR 20070032624A KR 1020067014535 A KR1020067014535 A KR 1020067014535A KR 20067014535 A KR20067014535 A KR 20067014535A KR 20070032624 A KR20070032624 A KR 20070032624A
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South Korea
Prior art keywords
trenches
doped region
region
conductivity type
trench
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Ceased
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KR1020067014535A
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English (en)
Korean (ko)
Inventor
푸-아이우안 히시에
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써드 디멘존 세미컨덕터, 인코포레이티드
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Publication of KR20070032624A publication Critical patent/KR20070032624A/ko
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/665—Vertical DMOS [VDMOS] FETs having edge termination structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/01—Manufacture or treatment
    • H10D62/051—Forming charge compensation regions, e.g. superjunctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/109—Reduced surface field [RESURF] PN junction structures
    • H10D62/111—Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/113—Isolations within a component, i.e. internal isolations
    • H10D62/115—Dielectric isolations, e.g. air gaps
    • H10D62/116—Dielectric isolations, e.g. air gaps adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/213—Channel regions of field-effect devices
    • H10D62/221—Channel regions of field-effect devices of FETs
    • H10D62/235—Channel regions of field-effect devices of FETs of IGFETs
    • H10D62/299—Channel regions of field-effect devices of FETs of IGFETs having lateral doping variations
    • H10D62/307—Channel regions of field-effect devices of FETs of IGFETs having lateral doping variations the doping variations being parallel to the channel lengths
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/016—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including vertical IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/22—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping using masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/22—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping using masks
    • H10P30/221—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping using masks characterised by the angle between the ion beam and the mask
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/222—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the angle between the ion beam and the crystal planes or the main crystal surface

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  • Bipolar Transistors (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Light Receiving Elements (AREA)
KR1020067014535A 2003-12-19 2004-12-10 종래의 종단을 갖는 수퍼 접합 장치를 제조하는 방법 Ceased KR20070032624A (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US53150103P 2003-12-19 2003-12-19
US60/531,501 2003-12-19
PCT/US2004/041302 WO2005065140A2 (en) 2003-12-19 2004-12-10 Method of manufacturing a superjunction device with conventional terminations

Related Child Applications (1)

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KR1020087022910A Division KR20080100265A (ko) 2003-12-19 2004-12-10 종래의 종단을 갖는 수퍼 접합 장치를 제조하는 방법

Publications (1)

Publication Number Publication Date
KR20070032624A true KR20070032624A (ko) 2007-03-22

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KR1020067014535A Ceased KR20070032624A (ko) 2003-12-19 2004-12-10 종래의 종단을 갖는 수퍼 접합 장치를 제조하는 방법
KR1020087022910A Withdrawn KR20080100265A (ko) 2003-12-19 2004-12-10 종래의 종단을 갖는 수퍼 접합 장치를 제조하는 방법

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Country Status (6)

Country Link
US (2) US7041560B2 (https=)
EP (1) EP1701686A4 (https=)
JP (2) JP2007515079A (https=)
KR (2) KR20070032624A (https=)
TW (1) TWI368948B (https=)
WO (1) WO2005065140A2 (https=)

Families Citing this family (48)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7638841B2 (en) 2003-05-20 2009-12-29 Fairchild Semiconductor Corporation Power semiconductor devices and methods of manufacture
KR100994719B1 (ko) * 2003-11-28 2010-11-16 페어차일드코리아반도체 주식회사 슈퍼정션 반도체장치
EP1701686A4 (en) * 2003-12-19 2009-07-01 Third Dimension 3D Sc Inc METHOD FOR PRODUCING A SUPER-BONDING DEVICE WITH CONVENTIONAL ENDS
WO2005065144A2 (en) * 2003-12-19 2005-07-21 Third Dimension (3D) Semiconductor, Inc. Planarization method of manufacturing a superjunction device
US6982193B2 (en) * 2004-05-10 2006-01-03 Semiconductor Components Industries, L.L.C. Method of forming a super-junction semiconductor device
TWI401749B (zh) 2004-12-27 2013-07-11 ３Ｄ半導體股份有限公司 用於高電壓超接面終止之方法
US7439583B2 (en) 2004-12-27 2008-10-21 Third Dimension (3D) Semiconductor, Inc. Tungsten plug drain extension
JP2008538659A (ja) * 2005-04-22 2008-10-30 アイスモス テクノロジー コーポレイション 酸化物で内面が覆われた溝を有する超接合素子と酸化物で内面を覆われた溝を有する超接合素子を製造するための方法
US7446018B2 (en) 2005-08-22 2008-11-04 Icemos Technology Corporation Bonded-wafer superjunction semiconductor device
US7429772B2 (en) * 2006-04-27 2008-09-30 Icemos Technology Corporation Technique for stable processing of thin/fragile substrates
US7948033B2 (en) 2007-02-06 2011-05-24 Semiconductor Components Industries, Llc Semiconductor device having trench edge termination structure
US8580651B2 (en) * 2007-04-23 2013-11-12 Icemos Technology Ltd. Methods for manufacturing a trench type semiconductor device having a thermally sensitive refill material
US7723172B2 (en) 2007-04-23 2010-05-25 Icemos Technology Ltd. Methods for manufacturing a trench type semiconductor device having a thermally sensitive refill material
CN103762243B (zh) 2007-09-21 2017-07-28 飞兆半导体公司 功率器件
US20090085148A1 (en) * 2007-09-28 2009-04-02 Icemos Technology Corporation Multi-directional trenching of a plurality of dies in manufacturing superjunction devices
US9484451B2 (en) 2007-10-05 2016-11-01 Vishay-Siliconix MOSFET active area and edge termination area charge balance
ITMI20072341A1 (it) * 2007-12-14 2009-06-15 St Microelectronics Srl Contatti profondi di dispositivi elettronici integrati basati su regioni inpiantate attraverso solchi
CN101510557B (zh) * 2008-01-11 2013-08-14 艾斯莫斯技术有限公司 具有电介质终止的超结半导体器件及制造该器件的方法
US7846821B2 (en) 2008-02-13 2010-12-07 Icemos Technology Ltd. Multi-angle rotation for ion implantation of trenches in superjunction devices
US7795045B2 (en) * 2008-02-13 2010-09-14 Icemos Technology Ltd. Trench depth monitor for semiconductor manufacturing
US8030133B2 (en) * 2008-03-28 2011-10-04 Icemos Technology Ltd. Method of fabricating a bonded wafer substrate for use in MEMS structures
US7807576B2 (en) * 2008-06-20 2010-10-05 Fairchild Semiconductor Corporation Structure and method for forming a thick bottom dielectric (TBD) for trench-gate devices
US20120273916A1 (en) 2011-04-27 2012-11-01 Yedinak Joseph A Superjunction Structures for Power Devices and Methods of Manufacture
US20110198689A1 (en) * 2010-02-17 2011-08-18 Suku Kim Semiconductor devices containing trench mosfets with superjunctions
US8598654B2 (en) 2011-03-16 2013-12-03 Fairchild Semiconductor Corporation MOSFET device with thick trench bottom oxide
US8673700B2 (en) 2011-04-27 2014-03-18 Fairchild Semiconductor Corporation Superjunction structures for power devices and methods of manufacture
US8772868B2 (en) 2011-04-27 2014-07-08 Fairchild Semiconductor Corporation Superjunction structures for power devices and methods of manufacture
US8786010B2 (en) 2011-04-27 2014-07-22 Fairchild Semiconductor Corporation Superjunction structures for power devices and methods of manufacture
US8836028B2 (en) 2011-04-27 2014-09-16 Fairchild Semiconductor Corporation Superjunction structures for power devices and methods of manufacture
CN103094067B (zh) * 2011-10-31 2015-10-14 上海华虹宏力半导体制造有限公司 一种半导体器件的制造方法
US9431249B2 (en) 2011-12-01 2016-08-30 Vishay-Siliconix Edge termination for super junction MOSFET devices
US9614043B2 (en) 2012-02-09 2017-04-04 Vishay-Siliconix MOSFET termination trench
TWI446459B (zh) * 2012-02-14 2014-07-21 茂達電子股份有限公司 具有超級介面之功率電晶體元件之製作方法
US8946814B2 (en) 2012-04-05 2015-02-03 Icemos Technology Ltd. Superjunction devices having narrow surface layout of terminal structures, buried contact regions and trench gates
US9842911B2 (en) 2012-05-30 2017-12-12 Vishay-Siliconix Adaptive charge balanced edge termination
US9576842B2 (en) 2012-12-10 2017-02-21 Icemos Technology, Ltd. Grass removal in patterned cavity etching
US9508596B2 (en) 2014-06-20 2016-11-29 Vishay-Siliconix Processes used in fabricating a metal-insulator-semiconductor field effect transistor
US9887259B2 (en) 2014-06-23 2018-02-06 Vishay-Siliconix Modulated super junction power MOSFET devices
KR102098996B1 (ko) 2014-08-19 2020-04-08 비쉐이-실리코닉스 초접합 금속 산화물 반도체 전계 효과 트랜지스터
CN104465402B (zh) * 2014-12-25 2018-03-06 中航（重庆）微电子有限公司 一种半导体器件制备工艺
CN110993557A (zh) * 2018-10-02 2020-04-10 英飞凌科技奥地利有限公司 用于在半导体主体中形成绝缘层的方法和晶体管器件
DE102018130444B4 (de) 2018-11-30 2025-01-23 Infineon Technologies Austria Ag Verfahren zum Herstellen eines Superjunction-Transistorbauelements
CN111628034B (zh) * 2020-05-28 2023-09-15 湖北京邦科技有限公司 光电探测装置的制造方法
CN112289684B (zh) * 2020-10-28 2023-06-30 上海华虹宏力半导体制造有限公司 功率器件的制作方法及器件
US11769665B2 (en) 2022-01-11 2023-09-26 Applied Materials, Inc. Power device structures and methods of making
JP7728204B6 (ja) 2022-03-04 2025-09-19 株式会社東芝 半導体装置
DE102023209573A1 (de) * 2023-09-29 2025-04-03 Robert Bosch Gesellschaft mit beschränkter Haftung Verfahren zum Herstellen eines Leistungshalbleiterbauelements mit einer Vielzahl von Finnen und daraus hergestelltes Leistungshalbleiterbauelement
CN119584606A (zh) * 2025-02-07 2025-03-07 深圳天狼芯半导体有限公司 超结垂直双扩散金属氧化物半导体器件及其制备方法

Family Cites Families (59)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4158206A (en) 1977-02-07 1979-06-12 Rca Corporation Semiconductor device
JPS5553462A (en) 1978-10-13 1980-04-18 Int Rectifier Corp Mosfet element
US5057444A (en) * 1985-03-05 1991-10-15 Matsushita Electric Industrial Co., Ltd. Method of fabricating semiconductor device
US5019522A (en) 1986-03-21 1991-05-28 Advanced Power Technology, Inc. Method of making topographic pattern delineated power MOSFET with profile tailored recessed source
US4895810A (en) 1986-03-21 1990-01-23 Advanced Power Technology, Inc. Iopographic pattern delineated power mosfet with profile tailored recessed source
US5045903A (en) 1988-05-17 1991-09-03 Advanced Power Technology, Inc. Topographic pattern delineated power MOSFET with profile tailored recessed source
US5472888A (en) 1988-02-25 1995-12-05 International Rectifier Corporation Depletion mode power MOSFET with refractory gate and method of making same
CN1019720B (zh) 1991-03-19 1992-12-30 电子科技大学 半导体功率器件
EP0512607B1 (en) * 1991-05-03 1997-07-16 Koninklijke Philips Electronics N.V. Method of manufacturing a semiconductor device using ion implantation
US5366914A (en) 1992-01-29 1994-11-22 Nec Corporation Vertical power MOSFET structure having reduced cell area
JPH0653315A (ja) * 1992-07-30 1994-02-25 Nec Corp 半導体装置およびその製造方法
US5506421A (en) 1992-11-24 1996-04-09 Cree Research, Inc. Power MOSFET in silicon carbide
CN1035294C (zh) 1993-10-29 1997-06-25 电子科技大学 具有异形掺杂岛的半导体器件耐压层
US5435888A (en) 1993-12-06 1995-07-25 Sgs-Thomson Microelectronics, Inc. Enhanced planarization technique for an integrated circuit
DE4404757C2 (de) * 1994-02-15 1998-08-20 Siemens Ag Verfahren zur Herstellung eines einem Graben benachbarten Diffusionsgebietes in einem Substrat
EP1039548B1 (de) 1996-02-05 2004-03-31 Infineon Technologies AG Durch Feldeffekt steuerbares Halbleiterbauelement
US5744994A (en) 1996-05-15 1998-04-28 Siliconix Incorporated Three-terminal power mosfet switch for use as synchronous rectifier or voltage clamp
KR0183886B1 (ko) 1996-06-17 1999-04-15 김광호 반도체장치의 트렌치 소자분리 방법
JP3327135B2 (ja) 1996-09-09 2002-09-24 日産自動車株式会社 電界効果トランジスタ
JP3607016B2 (ja) 1996-10-02 2005-01-05 株式会社半導体エネルギー研究所 半導体装置およびその作製方法、並びに携帯型の情報処理端末、ヘッドマウントディスプレイ、ナビゲーションシステム、携帯電話、カメラおよびプロジェクター
JP3938964B2 (ja) * 1997-02-10 2007-06-27 三菱電機株式会社 高耐圧半導体装置およびその製造方法
CN1199926A (zh) * 1997-05-21 1998-11-25 日本电气株式会社 一种半导体器件的制造方法
JP3618517B2 (ja) 1997-06-18 2005-02-09 三菱電機株式会社 半導体装置およびその製造方法
US5976947A (en) 1997-08-18 1999-11-02 Micron Technology, Inc. Method for forming dielectric within a recess
US6239463B1 (en) 1997-08-28 2001-05-29 Siliconix Incorporated Low resistance power MOSFET or other device containing silicon-germanium layer
US6081009A (en) * 1997-11-10 2000-06-27 Intersil Corporation High voltage mosfet structure
DE19801095B4 (de) 1998-01-14 2007-12-13 Infineon Technologies Ag Leistungs-MOSFET
EP1026749B1 (en) * 1998-07-23 2003-09-17 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing a semiconductor device and semiconductor device obtainable thereby
US6265282B1 (en) * 1998-08-17 2001-07-24 Micron Technology, Inc. Process for making an isolation structure
US6355580B1 (en) * 1998-09-03 2002-03-12 Micron Technology, Inc. Ion-assisted oxidation methods and the resulting structures
JP3951522B2 (ja) * 1998-11-11 2007-08-01 富士電機デバイステクノロジー株式会社 超接合半導体素子
US6291856B1 (en) 1998-11-12 2001-09-18 Fuji Electric Co., Ltd. Semiconductor device with alternating conductivity type layer and method of manufacturing the same
DE19854915C2 (de) 1998-11-27 2002-09-05 Infineon Technologies Ag MOS-Feldeffekttransistor mit Hilfselektrode
EP1011146B1 (en) 1998-12-09 2006-03-08 STMicroelectronics S.r.l. Method of manufacturing an integrated edge structure for high voltage semiconductor devices
US6452230B1 (en) 1998-12-23 2002-09-17 International Rectifier Corporation High voltage mosgated device with trenches to reduce on-resistance
US6190970B1 (en) 1999-01-04 2001-02-20 Industrial Technology Research Institute Method of making power MOSFET and IGBT with optimized on-resistance and breakdown voltage
US6346442B1 (en) * 1999-02-04 2002-02-12 Tower Semiconductor Ltd. Methods for fabricating a semiconductor chip having CMOS devices and a fieldless array
US6222229B1 (en) 1999-02-18 2001-04-24 Cree, Inc. Self-aligned shield structure for realizing high frequency power MOSFET devices with improved reliability
US6198127B1 (en) 1999-05-19 2001-03-06 Intersil Corporation MOS-gated power device having extended trench and doping zone and process for forming same
EP1058303A1 (en) 1999-05-31 2000-12-06 STMicroelectronics S.r.l. Fabrication of VDMOS structure with reduced parasitic effects
DE19964214C2 (de) 1999-09-07 2002-01-17 Infineon Technologies Ag Verfahren zur Herstellung einer Driftzone eines Kompensationsbauelements
GB9929613D0 (en) 1999-12-15 2000-02-09 Koninkl Philips Electronics Nv Manufacture of semiconductor material and devices using that material
US6214698B1 (en) 2000-01-11 2001-04-10 Taiwan Semiconductor Manufacturing Company Shallow trench isolation methods employing gap filling doped silicon oxide dielectric layer
JP4483001B2 (ja) * 2000-02-17 2010-06-16 富士電機システムズ株式会社 半導体素子
JP4560181B2 (ja) * 2000-06-30 2010-10-13 アイシン高丘株式会社 燃料電池セパレータの製造方法および製造装置
JP2002170955A (ja) * 2000-09-25 2002-06-14 Toshiba Corp 半導体装置およびその製造方法
JP4088031B2 (ja) * 2000-10-16 2008-05-21 株式会社東芝 半導体装置およびその製造方法
JP4088033B2 (ja) * 2000-11-27 2008-05-21 株式会社東芝 半導体装置
US6509220B2 (en) 2000-11-27 2003-01-21 Power Integrations, Inc. Method of fabricating a high-voltage transistor
US6608350B2 (en) 2000-12-07 2003-08-19 International Rectifier Corporation High voltage vertical conduction superjunction semiconductor device
US6424007B1 (en) 2001-01-24 2002-07-23 Power Integrations, Inc. High-voltage transistor with buried conduction layer
JP2002230413A (ja) * 2001-02-06 2002-08-16 Makoto Yamada 広告配信システム及びその方法
US6465325B2 (en) 2001-02-27 2002-10-15 Fairchild Semiconductor Corporation Process for depositing and planarizing BPSG for dense trench MOSFET application
EP1267415A3 (en) * 2001-06-11 2009-04-15 Kabushiki Kaisha Toshiba Power semiconductor device having resurf layer
US6949798B2 (en) * 2002-01-28 2005-09-27 Mitsubishi Denki Kabushiki Kaisha Semiconductor device
KR20070029655A (ko) * 2003-12-19 2007-03-14 써드 디멘존 세미컨덕터, 인코포레이티드 넓은 메사를 갖는 수퍼 접합 장치의 제조 방법
EP1701686A4 (en) * 2003-12-19 2009-07-01 Third Dimension 3D Sc Inc METHOD FOR PRODUCING A SUPER-BONDING DEVICE WITH CONVENTIONAL ENDS
WO2005065144A2 (en) * 2003-12-19 2005-07-21 Third Dimension (3D) Semiconductor, Inc. Planarization method of manufacturing a superjunction device
US7023069B2 (en) * 2003-12-19 2006-04-04 Third Dimension (3D) Semiconductor, Inc. Method for forming thick dielectric regions using etched trenches

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TW200531280A (en) 2005-09-16
JP2007515079A (ja) 2007-06-07
US20050181558A1 (en) 2005-08-18
JP5154347B2 (ja) 2013-02-27
TWI368948B (en) 2012-07-21
EP1701686A4 (en) 2009-07-01
US7041560B2 (en) 2006-05-09
WO2005065140A3 (en) 2006-10-12
KR20080100265A (ko) 2008-11-14
EP1701686A2 (en) 2006-09-20
JP2009004805A (ja) 2009-01-08
US7704864B2 (en) 2010-04-27
WO2005065140A2 (en) 2005-07-21
US20060160309A1 (en) 2006-07-20

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