KR20050118676A - 반도체 장치와 그 제조방법 - Google Patents

반도체 장치와 그 제조방법 Download PDF

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Publication number
KR20050118676A
KR20050118676A KR1020057017078A KR20057017078A KR20050118676A KR 20050118676 A KR20050118676 A KR 20050118676A KR 1020057017078 A KR1020057017078 A KR 1020057017078A KR 20057017078 A KR20057017078 A KR 20057017078A KR 20050118676 A KR20050118676 A KR 20050118676A
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South Korea
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layer
film
semiconductor device
insulating film
substrate
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KR1020057017078A
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English (en)
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KR100722623B1 (ko
Inventor
고지 도미나가
구니히코 이와모토
데츠지 야스다
도시히데 나바타메
Original Assignee
가부시키가이샤 호리바 세이사꾸쇼
도꾸리쯔교세이호진 상교기쥬쯔 소고겡뀨죠
로무 가부시키가이샤
가부시끼가이샤 르네사스 테크놀로지
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Publication of KR20050118676A publication Critical patent/KR20050118676A/ko
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Publication of KR100722623B1 publication Critical patent/KR100722623B1/ko

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    • H—ELECTRICITY
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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Abstract

본 발명은 게이트 절연막에 기인하는 트랜지스터 특성의 열화나 계면층의 증가를 억제한 고품위의 반도체 장치와 그 제조방법을 제공한다. 본 발명에서는, 실리콘 기판의 하나의 면에 계면층과 확산 억제층과 고유전율 절연막이 이 순서로 형성되어 있다.

Description

반도체 장치와 그 제조방법{SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME}
본 발명은 반도체 장치와 그 제조방법에 관한 것으로, 특히, 실리콘 기판에 금속 산화막 등을 게이트 절연막으로서 형성한 MIS(Metal Insulator Semiconductor)형 트랜지스터로서의 반도체 장치와 그 제조방법에 관한 것이다.
최근, 반도체의 고집적화에 따라, MIS형 트랜지스터의 게이트 절연막으로는, 종래의 실리콘 기판(Si 기판)을 산화시킨 SiO2로부터, 보다 유전체가 큰 재료(High-k)가 이용되어 오고 있다. 그러나, High-k 재료는 Si 기판과 상호 확산하여 유전율이 작아지고, 게다가 트랜지스터 작성 프로세스 시의 열처리에 의해서 그 확산층이 보다 증가한다는 과제가 있었다.
상술한 바와 같은 과제를 해결하기 위해서, 예를 들면, 일본 특허 공개 제2002-43565호 공보에 기재된 기술이 제안되고 있다. 즉, 이 기술은 Si 기판과 High-k 재료의 상호 확산을 막기 위해 Si를 질화시킨 Si3N4막을 Si 기판에 일단 형성한 후, High-k막을 형성하는 것이다.
그러나, 상기 공보에 기재된 기술에서는, 질소가 Si 계면 근처에 존재함으로써 트랜지스터 특성이 열화된다는 문제가 발생하고 있어, 고품위의 MIS형 트랜지스터를 반드시 확실하게 얻을 수 없었다.
본 발명은 상술한 사정에 유의하여 이루어진 것으로, 그 목적은 게이트 절연막에 기인하는 트랜지스터 특성의 열화나 계면층의 증가를 억제한 고품위의 반도체 장치와 그 제조방법을 제공하는 것이다.
도 1은 본 발명의 반도체 장치로서의 MIS형 트랜지스터의 구조를 개략적으로 도시하는 종단면도이다.
도 2는 상기 반도체 장치의 게이트 절연막의 형성 방법의 일례를 도시하는 도면이다.
도 3은 상기 반도체 장치의 게이트 절연막의 형성 방법의 다른 예를 도시하는 도면이다.
상기 목적을 달성하기 위해서, 본 발명의 반도체 장치는 실리콘 기판의 하나의 면에 계면층과 확산 억제층과 고유전율 절연막이 이 순서로 형성되어 있는 것을 특징으로 하고 있다(청구항 제 1항).
상기 반도체 장치에 있어서는, 예를 들면 Si 단결정으로 이루어지는 Si 기판과, 이 Si 기판의 하나의 면측에 형성되는 고유전율 절연막(High-k 절연막) 사이에 Si 기판과 상호 확산되도록 하여 형성된 Si와 High-k 구성 금속 원소로 구성되는 산화물이 계면층으로서 형성되며, 또한 이 계면층의 상면에 해당 계면층의 상기 High-k절연막으로의 확산을 억제하는 확산 억제층이 형성되어 있기 때문에, 계면층에는 High-k 구성 금속 원소, 산소 원소 및 Si만 존재하게 되어 트랜지스터 특성이 열화되는 일이 없다. 또한, 상기 반도체 장치에 있어서는, 트랜지스터 제작의 프로세스 중의 열처리에 의해서도, 상기 확산 억제층의 존재에 의해 계면층의 두께가 증대하는 일이 없이 고품위로 된다.
상기 반도체 장치에 있어서, 계면층의 두께가 SiO2 등가 환산 막두께로 1.0㎚ 이하인 것이 바람직하고(청구항 제2항), 또, 고유전율 절연막에서의 구성 원소가 계면층에서의 구성 원소의 일부와 동일하도록 하고 있어도 된다(청구항 제3항).
그리고, 상기 목적을 달성하기 위해, 본 발명의 반도체 장치의 제조방법은 실리콘 기판의 하나의 면에 초기층을 형성하고, 이 초기층의 표면에 확산 억제층을 형성한 후, 열처리를 실시하여 상기 초기층을 실리콘 기판과 상호 확산시킨 계면층으로 하며, 그 후, 상기 확산 억제층의 표면에 고유전율 절연막을 형성하는 것을 특징으로 하고 있다(청구항 제4항).
상기 반도체 장치의 제조방법에 의하면, 고품위의 반도체 장치를 확실히 얻을 수 있다.
또한, 상기 목적을 달성하기 위해서, 본 발명의 반도체 장치의 제조방법은 실리콘 기판의 하나의 면에 초기층을 형성하고, 이 초기층의 표면에 확산 억제층을 형성하며, 이 확산 억제층의 표면에 고유전율 절연막을 형성한 후, 열처리를 실시하여 상기 초기층을 실리콘 기판과 상호 확산시킨 계면층으로 하는 것을 특징으로 하고 있다(청구항 제5항).
상기 반도체 장치의 제조방법에 의하면, 청구항 제4항에 기재된 반도체 장치의 제조방법의 효과에 더하여 다음과 같은 효과가 있다. 즉, 성막의 방법으로서 ALD(Atomic Layer Deposition; 원자층 성막)법을 채용함으로써, 동일한 챔버 내에서 중단되는 일없이 프로세스 처리를 행할 수 있어 복수의 챔버를 준비할 필요가 없다.
발명의 실시형태를 도면을 참조하면서 설명한다. 우선, 도 1은 본 발명의 반도체 장치로서의 MIS형 트랜지스터(1)의 구성을 개략적으로 도시하는 것으로, 이 도면에 있어서 2는 Si 단결정 기판(이하, 간단히 Si 기판이라고 함)으로, 그 저항율은 예를 들면 0.01∼15Ω·㎝이다. 3은 소자간을 분리시키기 위한 소자 분리 산화막으로, Si 기판(1)을 열산화시켜 형성된다. 4는 게이트 절연막으로, 계면층(5), 확산 억제층(6) 및 High-k막(7)으로 이루어진다. 이 게이트 절연막(4)의 형성 방법에 대해서는, 이후에 상세하게 설명한다.
8은 게이트 절연막(4)의 상면에 형성되는 게이트 전극으로, 예를 들면 다결정 Si막이나 다결정 SiGe막, 또는, 게이트 절연막(4)과 반응하지 않는 Pt(백금) 등의 귀금속이나 TiN, TaN 등의 고융점 금속으로 이루어진다. 9는 채널 영역으로, n채널에는 P(인) 등을, p채널에는 B(붕소) 등을 각각 주입하고, 800∼1000℃의 온도에서 10∼30분간 열처리를 행하여 활성화시킨다. 10은 층간 절연막으로, 예를 들면 SiO2이고, CVD(Chemical Vapor Deposition)법 등으로 형성된다. 11은 인출 전극으로, 예를 들면 Al로 이루어지고 소스·드레인 전극이 된다. 한편, 패터닝은 예를 들면 포토리소그래피 기술에 의해서 행해진다.
다음에, 상기 게이트 절연막(4)을 형성하는 제1 방법에 대해서, 도 2를 참조하면서 설명한다.
(11) 우선, 도 2(A)에 도시하는 바와 같이, 적당한 두께(예를 들면, 500㎛ 정도)의 Si 단결정판으로 이루어지는 Si 기판(2)의 하나의 면(2a)에 Si와 상호 확산시키기 위한 초기층(제1층이라고도 함: 5')으로서 HfO2(산화 하프니아)로 이루어지는 박막을 약 0.5㎚의 두께로 형성한다. 상기 초기층(5')의 성막의 수단으로서는, CVD(Chemical Vapor Deposition)법, ALD법, 스퍼터법 등 각종 공지의 방법이 있다.
(12) 다음에, 도 2(B)에 도시하는 바와 같이, 초기층(5')의 상면에 확산 억제막(6)으로서, 금속 질화막으로서의 AlN막을 0.5∼5㎚의 두께로, 또는, 금속산 질화막으로서의 AlOxNy막(y>0)을 0.5∼5㎚의 두께로 형성한다. 이 경우, AlN막은 TMA (트리메틸알루미늄: Al(CH3)3)와 암모니아 가스(NH3)의 교대 원료 공급에 의한 ALD법에 따르는 성막이어도, 질소 함유 가스 분위기 중 스퍼터법이어도 된다. 또한, AlOxNy막은 TMA와 수증기 가스(H2O)의 교대 원료 공급에 의한 ALD법에 의해 성막한 Al2O3막을 NH3 가스 분위기 중의 열처리에 의해서 작성한 AlOxNy이어도, 상기 방법으로 성막한 Al2O3막을 플라즈마 질소 가스 분위기 중에서 처리한 AlOxNy이어도 된다.
(13) 다음에, 열처리(약 800℃)에 의해서, Si 기판(2) 중의 Si와 초기층(5')으로서 HfO2를 상호 확산시키고, 도 2(C)에 도시하는 바와 같이 계면층으로서의 HfSiO4(하프니아실리케이트: 5)를 형성한다.
(14) 그 후, 확산 억제막(6)의 상면에 High-k막(7)으로서 HfO2막을 약 5㎚의 두께로 성막함으로써, 도 2(D)에 도시하는 바와 같이, Si 기판(2)의 한 쪽의 면(2a) 상에 계면층(5), 확산 억제막(6) 및 High-k막(7)의 3층 구조를 가지는 게이트 절연막(4)을 형성할 수 있다. 상기 High-k막으로서의 HfO2막(7)의 성막은 CVD법, ALD법 또는 스퍼터법 중 어느 하나로 행해도 된다.
상술한 바와 같이 하여 형성된 반도체 장치(1)의 게이트 절연막(4)은, 트랜지스터 제작의 프로세스 중의 열처리에 의해서도, 전기 절연성이 뛰어난 확산 억제막(6)이 계면층(5)과 High-k막(7)의 사이에 형성되어 있기 때문에, 계면층(5)이 그 두께를 증대시키는 일은 없다. 또한, 상기 확산 억제막(6)이 존재함으로써 High-k막(7) 중의 산소가 계면층(5)측으로 확산되는 것이 억제되고, 그 결과, High-k성이 손상된다는 것이 효과적으로 방지된다. 따라서, 상기 반도체 장치(1)의 게이트 절연막(4)은 고품위인 것과 동시에, 그 제조방법은 고품위의 반도체 장치(1)의 게이트 절연막(4)을 확실히 제조할 수 있다.
한편, 상술한 실시형태에 있어서는, High-k막(7)을 HfO2막으로 형성하고 있었지만, 이 HfO2막 대신에 ZrO2나 TiO2로 하고, 계면층(5)을 ZrSiO4, TiSiO4로 각각 형성하고 있어도 좋고, 또한, HfO2와 Al2O3 등 High-k막 복합물(이 경우, HfAlOx)로 형성하고, 초기층(5')을 HfO2로 하며, 계면층(5)을 HfSiO4로 하고, 고유전율 절연막인 High-k막(7)에서의 구성 원소가 계면층(5)에서의 구성 원소의 일부와 동일하도록 구성해도 된다.
도 3은 게이트 절연막(4)이 형성하는 제2 방법을 개략적으로 도시하는 것이다.
(21) 우선, 도 3(A)에 도시하는 바와 같이, 적당한 두께(비유, 500㎛ 정도)의 Si 단결정판으로 이루어지는 Si 기판(2)의 하나의 면(2a)에 Si와 교대로 확산시키기 위한 초기층(5')으로서 HfO2로 이루어지는 박막을 약 0.5㎚의 두께로 형성한다. 상기 초기층(5')의 성막의 수단으로서는, Hf〔N(CH3)2〕4와 수증기 가스의 교대 원료 공급에 의한 ALD법으로 행한다. 이 때의 기판 온도는 250∼350℃, 성막 사이클수는 4회이다.
(22) 다음에, 공급 가스를 바꾸어, TMA와 암모니아 가스의 교대 원료 공급에 의한 ALD법에 의해서, 도 3(B)에 도시하는 바와 같이, 초기층(5')의 상면에 확산 억제막(6)으로서 AlN막을 0.5㎚의 두께로 형성한다. 이 때의 기판 온도는 250∼350℃, 성막 사이클수는 5회이다.
(23) 다음에, 도 3(C)에 도시하는 바와 같이, 확산 억제막(6)의 표면에 High-k막(7)으로서 HfO2막을 약 5㎚의 두께로 성막한다. 상기 High-k막(7)의 성막의 수단으로서는, Hf〔N(CH3)2〕4와 수증기 가스의 상호 원료 공급에 의한 ALD법으로 행한다. 즉, 상기 (21)과 동일하다. 이 때의 기판 온도는 250∼350℃, 성막 사이클수는 40회이다.
(24) 마지막으로, 열처리(약 800℃, 60초간)에 의해서, Si 기판(2) 중의 Si와 초기층(5')으로서의 HfO2를 상호 확산시키고, 도 3(D)에 도시하는 바와 같이, 계면층으로서의 HfSiO4(5)를 형성함으로써 Si 기판(2)의 한 쪽의 면(2a) 상에 계면층(5), 확산 억제막(6) 및 High-k막(7)의 3층 구조를 갖는 게이트 절연막(4)을 형성할 수 있다.
상술한 바와 같이 하여 제작된 반도체 장치(1)의 게이트 절연막(4)에 있어서도, 트랜지스터 제작의 프로세스 중의 열처리에 의해서도 전기 절연성이 뛰어난 확산 억제막(6)이 계면층(5)과 High-k막(7)의 사이에 형성되어 있기 때문에, 계면층(5)이 그 두께를 증대시키는 일은 없다. 또한, 상기 확산 억제막(6)이 존재함으로써, High-k막(7) 중의 산소가 계면층(5)측에 확산되는 것이 억제되고, 그 결과, High-k성이 손상된다는 것이 효과적으로 방지된다. 따라서, 상기 반도체 장치(1)의 게이트 절연막(4)은 고품위이다.
그리고, 이 도 3의 게이트 절연막(4)의 형성 방법에 의하면, 각 막(5' 6, 7)의 성막을 ALD법에 의해 행함으로써, 동일 챔버 내에서 중단되는 일없이 성막을 행할 수 있고, 복수의 장치나 챔버를 준비할 필요가 없어 제조 설비가 적어도 됨과 동시에, 고품위의 게이트 절연막(4)을 효율적으로 형성할 수 있다.
이상 설명한 바와 같이, 본 발명에 의하면 게이트 절연막에 기인하는 트랜지스터 특성의 열화나 계면층의 증가를 억제할 수 있고, 따라서, 고품위의 MIS형 트랜지스터를 얻을 수 있다.

Claims (5)

  1. 실리콘 기판의 하나의 면에 계면층과 확산 억제층과 고유전율 절연막이 이 순서로 형성되어 있는 것을 특징으로 하는 반도체 장치.
  2. 제1항에 있어서, 계면층의 두께가 SiO2 등가 환산 막두께로 1.0㎚ 이하인, 반도체 장치.
  3. 제1항 또는 제2항에 있어서, 고유전율 절연막에서의 구성 원소가 계면층에서의 구성 원소의 일부와 동일한, 반도체 장치.
  4. 실리콘 기판의 하나의 면에 초기층을 형성하고, 이 초기층의 표면에 확산 억제층을 형성한 후, 열처리를 실시하여 상기 초기층을 실리콘 기판과 상호 확산시킨 계면층으로 하며, 그 후, 상기 확산 억제층의 표면에 고유전율 절연막을 형성하는 것을 특징으로 하는 반도체 장치의 제조방법.
  5. 실리콘 기판의 하나의 면에 초기층을 형성하고, 이 초기층의 표면에 확산 억제층을 형성하며, 이 확산 억제층의 표면에 고유전율 절연막을 형성한 후, 열처리를 실시하여 상기 초기층을 실리콘 기판과 상호 확산시킨 계면층으로 하는 것을 특징으로 하는 반도체 장치의 제조방법.
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