KR20020062197A - 반도체직접회로장치 및 그 제조방법 - Google Patents

반도체직접회로장치 및 그 제조방법 Download PDF

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Publication number
KR20020062197A
KR20020062197A KR1020020002722A KR20020002722A KR20020062197A KR 20020062197 A KR20020062197 A KR 20020062197A KR 1020020002722 A KR1020020002722 A KR 1020020002722A KR 20020002722 A KR20020002722 A KR 20020002722A KR 20020062197 A KR20020062197 A KR 20020062197A
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KR
South Korea
Prior art keywords
wiring
connection terminal
semiconductor
external connection
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
KR1020020002722A
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English (en)
Korean (ko)
Inventor
미야모토토시오
안조이치로
니시무라아사오
카타기리미츠아키
시라이유지
야마구치요시히데
Original Assignee
가부시키가이샤 히타치세이사쿠쇼
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Application filed by 가부시키가이샤 히타치세이사쿠쇼 filed Critical 가부시키가이샤 히타치세이사쿠쇼
Publication of KR20020062197A publication Critical patent/KR20020062197A/ko
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H10P74/23—Testing or measuring during manufacture or treatment of wafers, substrates or devices characterised by multiple measurements, corrections, marking or sorting processes
    • H10P74/232—Testing or measuring during manufacture or treatment of wafers, substrates or devices characterised by multiple measurements, corrections, marking or sorting processes comprising connection or disconnection of parts of a device in response to a measurement
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/641—Adaptable interconnections, e.g. fuses or antifuses
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/129—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed forming a chip-scale package [CSP]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H10W46/101—Marks applied to devices, e.g. for alignment or identification characterised by the type of information, e.g. logos or symbols
    • H10W46/103—Marks applied to devices, e.g. for alignment or identification characterised by the type of information, e.g. logos or symbols alphanumeric information, e.g. words, letters or serial numbers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H10W70/654—Top-view layouts
    • H10W70/655—Fan-out layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/019—Manufacture or treatment of bond pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/922—Bond pads being integral with underlying chip-level interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/922—Bond pads being integral with underlying chip-level interconnections
    • H10W72/9223—Bond pads being integral with underlying chip-level interconnections with redistribution layers [RDL]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/923—Bond pads having multiple stacked layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/9415—Dispositions of bond pads relative to the surface, e.g. recessed, protruding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/942—Dispositions of bond pads relative to underlying supporting features, e.g. bond pads, RDLs or vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/944—Dispositions of multiple bond pads
    • H10W72/9445—Top-view layouts, e.g. mirror arrays

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
  • Formation Of Insulating Films (AREA)
KR1020020002722A 2001-01-18 2002-01-17 반도체직접회로장치 및 그 제조방법 Ceased KR20020062197A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2001010821A JP2002217377A (ja) 2001-01-18 2001-01-18 半導体集積回路装置およびその製造方法
JPJP-P-2001-00010821 2001-01-18

Publications (1)

Publication Number Publication Date
KR20020062197A true KR20020062197A (ko) 2002-07-25

Family

ID=18878068

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020020002722A Ceased KR20020062197A (ko) 2001-01-18 2002-01-17 반도체직접회로장치 및 그 제조방법

Country Status (3)

Country Link
US (2) US6861742B2 (https=)
JP (1) JP2002217377A (https=)
KR (1) KR20020062197A (https=)

Cited By (1)

* Cited by examiner, † Cited by third party
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KR20170044665A (ko) * 2014-08-26 2017-04-25 데카 테크놀로지 잉크 고유 식별자를 포함하는 패키지에 대한 프론트사이드 패키지 레벨 직렬화

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US8021976B2 (en) * 2002-10-15 2011-09-20 Megica Corporation Method of wire bonding over active area of a semiconductor circuit
US6815324B2 (en) * 2001-02-15 2004-11-09 Megic Corporation Reliable metal bumps on top of I/O pads after removal of test probe marks
TWI313507B (en) * 2002-10-25 2009-08-11 Megica Corporatio Method for assembling chips
US6818545B2 (en) * 2001-03-05 2004-11-16 Megic Corporation Low fabrication cost, fine pitch and high reliability solder bump
US8158508B2 (en) * 2001-03-05 2012-04-17 Megica Corporation Structure and manufacturing method of a chip scale package
US7099293B2 (en) * 2002-05-01 2006-08-29 Stmicroelectronics, Inc. Buffer-less de-skewing for symbol combination in a CDMA demodulator
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JP3871609B2 (ja) * 2002-05-27 2007-01-24 松下電器産業株式会社 半導体装置及びその製造方法
DE10258094B4 (de) * 2002-12-11 2009-06-18 Qimonda Ag Verfahren zur Ausbildung von 3-D Strukturen auf Wafern
US7470997B2 (en) * 2003-07-23 2008-12-30 Megica Corporation Wirebond pad for semiconductor chip or wafer
US7394161B2 (en) * 2003-12-08 2008-07-01 Megica Corporation Chip structure with pads having bumps or wirebonded wires formed thereover or used to be tested thereto
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US7422930B2 (en) * 2004-03-02 2008-09-09 Infineon Technologies Ag Integrated circuit with re-route layer and stacked die assembly
US8067837B2 (en) * 2004-09-20 2011-11-29 Megica Corporation Metallization structure over passivation layer for IC chip
USD522470S1 (en) * 2004-09-09 2006-06-06 Kabushiki Kaisha Toshiba Portion of a semiconductor device
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JP4289335B2 (ja) * 2005-08-10 2009-07-01 セイコーエプソン株式会社 電子部品、回路基板及び電子機器
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JP5078725B2 (ja) * 2008-04-22 2012-11-21 ラピスセミコンダクタ株式会社 半導体装置
US11131431B2 (en) 2014-09-28 2021-09-28 Jiaxing Super Lighting Electric Appliance Co., Ltd LED tube lamp
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JP5671890B2 (ja) * 2010-08-31 2015-02-18 株式会社ニコン 撮像装置
TWI464857B (zh) * 2011-05-20 2014-12-11 精材科技股份有限公司 晶片封裝體、其形成方法、及封裝晶圓
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US11028973B2 (en) 2015-03-10 2021-06-08 Jiaxing Super Lighting Electric Appliance Co., Ltd. Led tube lamp
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KR20170044665A (ko) * 2014-08-26 2017-04-25 데카 테크놀로지 잉크 고유 식별자를 포함하는 패키지에 대한 프론트사이드 패키지 레벨 직렬화

Also Published As

Publication number Publication date
US20020093082A1 (en) 2002-07-18
JP2002217377A (ja) 2002-08-02
US20040155351A1 (en) 2004-08-12
US6946327B2 (en) 2005-09-20
US6861742B2 (en) 2005-03-01

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