KR20020035870A - 인듐 열결합을 갖는 전자 조립체 및 그 구성방법 - Google Patents

인듐 열결합을 갖는 전자 조립체 및 그 구성방법 Download PDF

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Publication number
KR20020035870A
KR20020035870A KR1020027003268A KR20027003268A KR20020035870A KR 20020035870 A KR20020035870 A KR 20020035870A KR 1020027003268 A KR1020027003268 A KR 1020027003268A KR 20027003268 A KR20027003268 A KR 20027003268A KR 20020035870 A KR20020035870 A KR 20020035870A
Authority
KR
South Korea
Prior art keywords
alloy
semiconductor chip
thin plate
melting point
thermally conductive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
KR1020027003268A
Other languages
English (en)
Korean (ko)
Inventor
디송테렌스제이.
처릴라폴더블유.
폴렌데이비드에이치.
Original Assignee
피터 엔. 데트킨
인텔 코오퍼레이션
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 피터 엔. 데트킨, 인텔 코오퍼레이션 filed Critical 피터 엔. 데트킨
Publication of KR20020035870A publication Critical patent/KR20020035870A/ko
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3736—Metallic materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
KR1020027003268A 1999-09-13 2000-08-29 인듐 열결합을 갖는 전자 조립체 및 그 구성방법 Ceased KR20020035870A (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/394,860 US6461891B1 (en) 1999-09-13 1999-09-13 Method of constructing an electronic assembly having an indium thermal couple and an electronic assembly having an indium thermal couple
US09/394,860 1999-09-13
PCT/US2000/023778 WO2001020673A1 (en) 1999-09-13 2000-08-29 A method of constructing an electronic assembly having an indium thermal couple and an electronic assembly having an indium thermal couple

Publications (1)

Publication Number Publication Date
KR20020035870A true KR20020035870A (ko) 2002-05-15

Family

ID=23560692

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020027003268A Ceased KR20020035870A (ko) 1999-09-13 2000-08-29 인듐 열결합을 갖는 전자 조립체 및 그 구성방법

Country Status (8)

Country Link
US (2) US6461891B1 (enExample)
JP (1) JP5030352B2 (enExample)
KR (1) KR20020035870A (enExample)
CN (1) CN1319158C (enExample)
AU (1) AU7088900A (enExample)
MX (1) MXPA02002649A (enExample)
MY (1) MY122678A (enExample)
WO (1) WO2001020673A1 (enExample)

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KR100820665B1 (ko) * 2006-09-19 2008-04-11 후지쯔 가부시끼가이샤 반도체 장치 및 그 제조 방법

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US6461891B1 (en) 1999-09-13 2002-10-08 Intel Corporation Method of constructing an electronic assembly having an indium thermal couple and an electronic assembly having an indium thermal couple
US6709898B1 (en) * 2000-10-04 2004-03-23 Intel Corporation Die-in-heat spreader microelectronic package
CN100362655C (zh) * 2002-01-30 2008-01-16 霍尼韦尔国际公司 热界面材料以及包括铟和锌的组合物
US6882041B1 (en) * 2002-02-05 2005-04-19 Altera Corporation Thermally enhanced metal capped BGA package
US7436058B2 (en) * 2002-05-09 2008-10-14 Intel Corporation Reactive solder material
US20070164424A1 (en) * 2003-04-02 2007-07-19 Nancy Dean Thermal interconnect and interface systems, methods of production and uses thereof
DE10335111B4 (de) * 2003-07-31 2006-12-28 Infineon Technologies Ag Montageverfahren für ein Halbleiterbauteil
US7132746B2 (en) * 2003-08-18 2006-11-07 Delphi Technologies, Inc. Electronic assembly with solder-bonded heat sink
JP4411123B2 (ja) * 2004-03-31 2010-02-10 新光電気工業株式会社 放熱板の製造方法
JP2007266150A (ja) * 2006-03-28 2007-10-11 Fujitsu Ltd 熱伝導性接合材、半導体パッケージ、ヒートスプレッダ、半導体チップ、及び半導体チップとヒートスプレッダとを接合する接合方法
US7633151B2 (en) * 2007-03-16 2009-12-15 Advanced Micro Devices, Inc. Integrated circuit package lid with a wetting film
US7834442B2 (en) * 2007-12-12 2010-11-16 International Business Machines Corporation Electronic package method and structure with cure-melt hierarchy
JP5153316B2 (ja) * 2007-12-21 2013-02-27 新光電気工業株式会社 半導体パッケージ用放熱板およびそのめっき方法
US8378480B2 (en) * 2010-03-04 2013-02-19 Taiwan Semiconductor Manufacturing Company, Ltd. Dummy wafers in 3DIC package assemblies

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100820665B1 (ko) * 2006-09-19 2008-04-11 후지쯔 가부시끼가이샤 반도체 장치 및 그 제조 방법
US8513800B2 (en) 2006-09-19 2013-08-20 Fujitsu Semiconductor Limited Semiconductor device and method for manufacturing the same

Also Published As

Publication number Publication date
US20020151110A1 (en) 2002-10-17
AU7088900A (en) 2001-04-17
US20020020912A1 (en) 2002-02-21
JP2003509865A (ja) 2003-03-11
MY122678A (en) 2006-04-29
US6461891B1 (en) 2002-10-08
CN1319158C (zh) 2007-05-30
CN1373903A (zh) 2002-10-09
MXPA02002649A (es) 2003-01-28
JP5030352B2 (ja) 2012-09-19
US6882043B2 (en) 2005-04-19
WO2001020673A1 (en) 2001-03-22

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