KR20020027588A - 에칭 방법 및 플라즈마 처리 방법 - Google Patents
에칭 방법 및 플라즈마 처리 방법 Download PDFInfo
- Publication number
- KR20020027588A KR20020027588A KR1020027002517A KR20027002517A KR20020027588A KR 20020027588 A KR20020027588 A KR 20020027588A KR 1020027002517 A KR1020027002517 A KR 1020027002517A KR 20027002517 A KR20027002517 A KR 20027002517A KR 20020027588 A KR20020027588 A KR 20020027588A
- Authority
- KR
- South Korea
- Prior art keywords
- layer
- gas
- etching
- processing
- treatment
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims description 64
- 238000005530 etching Methods 0.000 title claims description 56
- 238000009832 plasma treatment Methods 0.000 title claims description 8
- 238000012545 processing Methods 0.000 claims abstract description 60
- 229910052799 carbon Inorganic materials 0.000 claims abstract description 24
- 229910052731 fluorine Inorganic materials 0.000 claims abstract description 23
- 239000007789 gas Substances 0.000 claims description 67
- 238000004380 ashing Methods 0.000 claims description 19
- 229910052739 hydrogen Inorganic materials 0.000 claims description 13
- 229920002120 photoresistant polymer Polymers 0.000 claims description 9
- 239000011261 inert gas Substances 0.000 claims description 6
- 229910052760 oxygen Inorganic materials 0.000 claims description 5
- 238000003672 processing method Methods 0.000 claims description 4
- 229910004205 SiNX Inorganic materials 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 94
- 230000008569 process Effects 0.000 description 30
- 235000012431 wafers Nutrition 0.000 description 16
- 239000004065 semiconductor Substances 0.000 description 9
- 238000004381 surface treatment Methods 0.000 description 8
- 229910004298 SiO 2 Inorganic materials 0.000 description 6
- 230000003647 oxidation Effects 0.000 description 5
- 238000007254 oxidation reaction Methods 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 2
- 238000010348 incorporation Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- 229910000967 As alloy Inorganic materials 0.000 description 1
- -1 He may be used Substances 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 125000004432 carbon atom Chemical group C* 0.000 description 1
- 239000007795 chemical reaction product Substances 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 125000001153 fluoro group Chemical group F* 0.000 description 1
- NBVXSUQYWXRMNV-UHFFFAOYSA-N fluoromethane Chemical compound FC NBVXSUQYWXRMNV-UHFFFAOYSA-N 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000010849 ion bombardment Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000000691 measurement method Methods 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 125000004430 oxygen atom Chemical group O* 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31127—Etching organic layers
- H01L21/31133—Etching organic layers by chemical means
- H01L21/31138—Etching organic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- General Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Inorganic Chemistry (AREA)
- Plasma & Fusion (AREA)
- Drying Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Plasma Technology (AREA)
Abstract
Description
Claims (11)
- 처리실 내에 도입된 처리 기체를 플라즈마화하고, 상기 처리실 내에 배치된 피처리체에 형성된 Cu층상의 SiNx층을 에칭하여 Cu층을 노출시키는 에칭 방법에 있어서,상기 처리 기체가 C, H 및 F로 구성된 기체 및 O2를 포함하는 것을 특징으로 하는 에칭 방법.
- 제 1 항에 있어서,상기 C, H 및 F로 구성된 기체가 CH2F2인 에칭 방법.
- 제 1 항에 있어서,상기 C, H 및 F로 구성된 기체가 CH3F인 에칭 방법.
- 제 1 항에 있어서,상기 C, H 및 F로 구성된 기체가 CHF3인 에칭 방법.
- 제 1 항에 있어서,상기 처리 기체에 불활성 기체가 첨가되는 에칭 방법.
- C, H 및 F로 구성된 기체 및 O2를 포함하는 처리 기체를 플라즈마화하고, 소정의 패턴이 형성된 포토레지스트층을 사용하여 Cu층상의 SiNx층을 에칭하여 Cu층을 노출시키는 단계;상기 에칭 단계 후 포토레지스트층을 애싱하는 단계; 및상기 애싱 단계 후 처리실 내에 H2를 도입하고, H2를 플라즈마화하하여 노출된 Cu층에 H2플라즈마 처리를 실시하는 단계를 포함하는 것을 특징으로 하는 플라즈마 처리 방법.
- 제 6 항에 있어서,상기 C, H 및 F로 구성된 기체가 CH2F2인 에칭 방법.
- 제 6 항에 있어서,상기 C, H 및 F로 구성된 기체가 CH3F인 에칭 방법.
- 제 6 항에 있어서,상기 C, H 및 F로 구성된 기체가 CHF3인 에칭 방법.
- 제 6 항에 있어서,상기 처리 기체에 불활성 기체가 첨가되는 에칭 방법.
- 제 6 항에 있어서,상기 에칭 단계, 애싱 단계 및 H2에칭 단계가 동일한 처리실 내에서 실시되는 에칭 방법.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JPJP-P-1999-00241427 | 1999-08-27 | ||
JP24142799A JP4471243B2 (ja) | 1999-08-27 | 1999-08-27 | エッチング方法およびプラズマ処理方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR20020027588A true KR20020027588A (ko) | 2002-04-13 |
KR100739909B1 KR100739909B1 (ko) | 2007-07-16 |
Family
ID=17074148
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1020027002517A KR100739909B1 (ko) | 1999-08-27 | 2000-08-23 | 에칭 방법 및 플라즈마 처리 방법 |
Country Status (7)
Country | Link |
---|---|
US (2) | US6780342B1 (ko) |
EP (1) | EP1207550B1 (ko) |
JP (1) | JP4471243B2 (ko) |
KR (1) | KR100739909B1 (ko) |
DE (1) | DE60016423T2 (ko) |
TW (1) | TW457582B (ko) |
WO (1) | WO2001017007A1 (ko) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003017469A (ja) * | 2001-06-29 | 2003-01-17 | Tokyo Electron Ltd | エッチング兼アッシング装置、アッシング装置、アッシング方法及び処理方法 |
US7235884B1 (en) * | 2003-04-01 | 2007-06-26 | Altera Corporation | Local control of electrical and mechanical properties of copper interconnects to achieve stable and reliable via |
US7101487B2 (en) * | 2003-05-02 | 2006-09-05 | Ossur Engineering, Inc. | Magnetorheological fluid compositions and prosthetic knees utilizing same |
WO2005076336A1 (ja) * | 2004-02-09 | 2005-08-18 | Tadahiro Ohmi | 半導体装置の製造方法および絶縁膜のエッチング方法 |
US20050227382A1 (en) * | 2004-04-02 | 2005-10-13 | Hui Angela T | In-situ surface treatment for memory cell formation |
JP2008235918A (ja) * | 2008-04-16 | 2008-10-02 | Tokyo Electron Ltd | プラズマ基板処理装置 |
CN103839604A (zh) * | 2014-02-26 | 2014-06-04 | 京东方科技集团股份有限公司 | 导电膜及其制备方法、阵列基板 |
JP6385198B2 (ja) * | 2014-08-21 | 2018-09-05 | 日東電工株式会社 | 回路付サスペンション基板の製造方法 |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2758754B2 (ja) * | 1991-12-05 | 1998-05-28 | シャープ株式会社 | プラズマエッチング方法 |
JPH06204191A (ja) | 1992-11-10 | 1994-07-22 | Sony Corp | 金属プラグ形成後の表面処理方法 |
JP3390329B2 (ja) | 1997-06-27 | 2003-03-24 | 日本電気株式会社 | 半導体装置およびその製造方法 |
JPH11214355A (ja) * | 1998-01-20 | 1999-08-06 | Nec Corp | 異方性ドライエッチング方法 |
US6162583A (en) * | 1998-03-20 | 2000-12-19 | Industrial Technology Research Institute | Method for making intermetal dielectrics (IMD) on semiconductor integrated circuits using low dielectric constant spin-on polymers |
US6107208A (en) | 1998-06-04 | 2000-08-22 | Advanced Micro Devices, Inc. | Nitride etch using N2 /Ar/CHF3 chemistry |
US6380096B2 (en) * | 1998-07-09 | 2002-04-30 | Applied Materials, Inc. | In-situ integrated oxide etch process particularly useful for copper dual damascene |
JP3180779B2 (ja) | 1998-10-05 | 2001-06-25 | 日本電気株式会社 | 半導体装置の製造方法 |
US6093632A (en) * | 1998-12-07 | 2000-07-25 | Industrial Technology Research Institute | Modified dual damascene process |
US6204192B1 (en) * | 1999-03-29 | 2001-03-20 | Lsi Logic Corporation | Plasma cleaning process for openings formed in at least one low dielectric constant insulation layer over copper metallization in integrated circuit structures |
-
1999
- 1999-08-27 JP JP24142799A patent/JP4471243B2/ja not_active Expired - Lifetime
-
2000
- 2000-08-23 DE DE60016423T patent/DE60016423T2/de not_active Expired - Lifetime
- 2000-08-23 WO PCT/JP2000/005624 patent/WO2001017007A1/ja active IP Right Grant
- 2000-08-23 EP EP00954911A patent/EP1207550B1/en not_active Expired - Lifetime
- 2000-08-23 US US10/030,656 patent/US6780342B1/en not_active Expired - Lifetime
- 2000-08-23 KR KR1020027002517A patent/KR100739909B1/ko active IP Right Grant
- 2000-08-25 TW TW089117250A patent/TW457582B/zh not_active IP Right Cessation
-
2004
- 2004-08-02 US US10/902,893 patent/US7211197B2/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
US20050000939A1 (en) | 2005-01-06 |
EP1207550A1 (en) | 2002-05-22 |
EP1207550B1 (en) | 2004-12-01 |
TW457582B (en) | 2001-10-01 |
DE60016423D1 (de) | 2005-01-05 |
US7211197B2 (en) | 2007-05-01 |
DE60016423T2 (de) | 2005-11-24 |
EP1207550A4 (en) | 2002-11-06 |
US6780342B1 (en) | 2004-08-24 |
JP4471243B2 (ja) | 2010-06-02 |
WO2001017007A1 (fr) | 2001-03-08 |
KR100739909B1 (ko) | 2007-07-16 |
JP2001068454A (ja) | 2001-03-16 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US5302240A (en) | Method of manufacturing semiconductor device | |
KR960000375B1 (ko) | 반도체장치의 제조방법 | |
KR101032831B1 (ko) | 챔버 탈불화 및 웨이퍼 탈불화 단계들을 방해하는 플라즈마에칭 및 포토레지스트 스트립 프로세스 | |
JPH06252107A (ja) | ドライエッチング方法 | |
JPH09148314A (ja) | ケイ化チタンのエッチングプロセス | |
JPH07153746A (ja) | ドライエッチング室のクリーニング方法 | |
KR20020027588A (ko) | 에칭 방법 및 플라즈마 처리 방법 | |
KR100407998B1 (ko) | 금속 배선의 콘택 영역 세정 방법 | |
KR950005351B1 (ko) | 알루미늄 합금의 부식 방지 방법 | |
JP2002134611A (ja) | 半導体装置の製造方法 | |
US5827436A (en) | Method for etching aluminum metal films | |
US6492272B1 (en) | Carrier gas modification for use in plasma ashing of photoresist | |
JP3258240B2 (ja) | エッチング方法 | |
US6391786B1 (en) | Etching process for organic anti-reflective coating | |
KR101179111B1 (ko) | 에칭 방법 및 기억 매체 | |
WO1999062111A1 (fr) | Procede de gravure | |
JPH08306668A (ja) | アッシング方法 | |
JPH0697127A (ja) | 配線形成方法 | |
KR20000071322A (ko) | 반도체 장치 제조 방법 | |
US20070037381A1 (en) | Method for fabricating Al metal line | |
JP3440599B2 (ja) | ビアホール形成方法 | |
JP3164789B2 (ja) | 高融点金属膜のドライエッチング方法 | |
JPH05217965A (ja) | 半導体装置の製造方法 | |
KR20000073004A (ko) | 금속층 식각에 사용된 포토레지스트 마스크 제거 방법 | |
JP3337652B2 (ja) | 金属膜のエッチング方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
E902 | Notification of reason for refusal | ||
E701 | Decision to grant or registration of patent right | ||
GRNT | Written decision to grant | ||
FPAY | Annual fee payment |
Payment date: 20130621 Year of fee payment: 7 |
|
FPAY | Annual fee payment |
Payment date: 20140626 Year of fee payment: 8 |
|
FPAY | Annual fee payment |
Payment date: 20150618 Year of fee payment: 9 |
|
FPAY | Annual fee payment |
Payment date: 20160617 Year of fee payment: 10 |
|
FPAY | Annual fee payment |
Payment date: 20170616 Year of fee payment: 11 |
|
FPAY | Annual fee payment |
Payment date: 20180618 Year of fee payment: 12 |
|
FPAY | Annual fee payment |
Payment date: 20190618 Year of fee payment: 13 |