DE60016423D1 - Ätzmethode und plasmabehandlungsmethode - Google Patents

Ätzmethode und plasmabehandlungsmethode

Info

Publication number
DE60016423D1
DE60016423D1 DE60016423T DE60016423T DE60016423D1 DE 60016423 D1 DE60016423 D1 DE 60016423D1 DE 60016423 T DE60016423 T DE 60016423T DE 60016423 T DE60016423 T DE 60016423T DE 60016423 D1 DE60016423 D1 DE 60016423D1
Authority
DE
Germany
Prior art keywords
plasma treatment
treatment method
plasma
treatment
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60016423T
Other languages
English (en)
Other versions
DE60016423T2 (de
Inventor
Masaaki Hagihara
Koichiro Inazawa
Wakako Naito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tokyo Electron Ltd
Original Assignee
Tokyo Electron Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Electron Ltd filed Critical Tokyo Electron Ltd
Publication of DE60016423D1 publication Critical patent/DE60016423D1/de
Application granted granted Critical
Publication of DE60016423T2 publication Critical patent/DE60016423T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31127—Etching organic layers
    • H01L21/31133—Etching organic layers by chemical means
    • H01L21/31138—Etching organic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Plasma & Fusion (AREA)
  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Plasma Technology (AREA)
DE60016423T 1999-08-27 2000-08-23 Ätzmethode und plasmabehandlungsmethode Expired - Lifetime DE60016423T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP24142799A JP4471243B2 (ja) 1999-08-27 1999-08-27 エッチング方法およびプラズマ処理方法
JP24142799 1999-08-27
PCT/JP2000/005624 WO2001017007A1 (fr) 1999-08-27 2000-08-23 Techniques d'attaque et de traitement au plasma

Publications (2)

Publication Number Publication Date
DE60016423D1 true DE60016423D1 (de) 2005-01-05
DE60016423T2 DE60016423T2 (de) 2005-11-24

Family

ID=17074148

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60016423T Expired - Lifetime DE60016423T2 (de) 1999-08-27 2000-08-23 Ätzmethode und plasmabehandlungsmethode

Country Status (7)

Country Link
US (2) US6780342B1 (de)
EP (1) EP1207550B1 (de)
JP (1) JP4471243B2 (de)
KR (1) KR100739909B1 (de)
DE (1) DE60016423T2 (de)
TW (1) TW457582B (de)
WO (1) WO2001017007A1 (de)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003017469A (ja) * 2001-06-29 2003-01-17 Tokyo Electron Ltd エッチング兼アッシング装置、アッシング装置、アッシング方法及び処理方法
US7235884B1 (en) * 2003-04-01 2007-06-26 Altera Corporation Local control of electrical and mechanical properties of copper interconnects to achieve stable and reliable via
US7101487B2 (en) * 2003-05-02 2006-09-05 Ossur Engineering, Inc. Magnetorheological fluid compositions and prosthetic knees utilizing same
WO2005076336A1 (ja) * 2004-02-09 2005-08-18 Tadahiro Ohmi 半導体装置の製造方法および絶縁膜のエッチング方法
US20050227382A1 (en) * 2004-04-02 2005-10-13 Hui Angela T In-situ surface treatment for memory cell formation
JP2008235918A (ja) * 2008-04-16 2008-10-02 Tokyo Electron Ltd プラズマ基板処理装置
CN103839604A (zh) * 2014-02-26 2014-06-04 京东方科技集团股份有限公司 导电膜及其制备方法、阵列基板
JP6385198B2 (ja) * 2014-08-21 2018-09-05 日東電工株式会社 回路付サスペンション基板の製造方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2758754B2 (ja) * 1991-12-05 1998-05-28 シャープ株式会社 プラズマエッチング方法
JPH06204191A (ja) 1992-11-10 1994-07-22 Sony Corp 金属プラグ形成後の表面処理方法
JP3390329B2 (ja) 1997-06-27 2003-03-24 日本電気株式会社 半導体装置およびその製造方法
JPH11214355A (ja) * 1998-01-20 1999-08-06 Nec Corp 異方性ドライエッチング方法
US6162583A (en) * 1998-03-20 2000-12-19 Industrial Technology Research Institute Method for making intermetal dielectrics (IMD) on semiconductor integrated circuits using low dielectric constant spin-on polymers
US6107208A (en) 1998-06-04 2000-08-22 Advanced Micro Devices, Inc. Nitride etch using N2 /Ar/CHF3 chemistry
US6380096B2 (en) * 1998-07-09 2002-04-30 Applied Materials, Inc. In-situ integrated oxide etch process particularly useful for copper dual damascene
JP3180779B2 (ja) 1998-10-05 2001-06-25 日本電気株式会社 半導体装置の製造方法
US6093632A (en) * 1998-12-07 2000-07-25 Industrial Technology Research Institute Modified dual damascene process
US6204192B1 (en) * 1999-03-29 2001-03-20 Lsi Logic Corporation Plasma cleaning process for openings formed in at least one low dielectric constant insulation layer over copper metallization in integrated circuit structures

Also Published As

Publication number Publication date
JP4471243B2 (ja) 2010-06-02
TW457582B (en) 2001-10-01
US20050000939A1 (en) 2005-01-06
KR20020027588A (ko) 2002-04-13
EP1207550B1 (de) 2004-12-01
KR100739909B1 (ko) 2007-07-16
DE60016423T2 (de) 2005-11-24
WO2001017007A1 (fr) 2001-03-08
US6780342B1 (en) 2004-08-24
EP1207550A4 (de) 2002-11-06
US7211197B2 (en) 2007-05-01
JP2001068454A (ja) 2001-03-16
EP1207550A1 (de) 2002-05-22

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