KR20010041108A - 구동 ic칩 및 프린트 헤드 - Google Patents
구동 ic칩 및 프린트 헤드 Download PDFInfo
- Publication number
- KR20010041108A KR20010041108A KR1020007009149A KR20007009149A KR20010041108A KR 20010041108 A KR20010041108 A KR 20010041108A KR 1020007009149 A KR1020007009149 A KR 1020007009149A KR 20007009149 A KR20007009149 A KR 20007009149A KR 20010041108 A KR20010041108 A KR 20010041108A
- Authority
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- South Korea
- Prior art keywords
- pads
- chip
- side edge
- pad
- integrated circuit
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Classifications
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
- B41J—TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
- B41J2/00—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed
- B41J2/315—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by selective application of heat to a heat sensitive printing or impression-transfer material
- B41J2/32—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by selective application of heat to a heat sensitive printing or impression-transfer material using thermal heads
- B41J2/345—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by selective application of heat to a heat sensitive printing or impression-transfer material using thermal heads characterised by the arrangement of resistors or conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05553—Shape in top view being rectangular
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0612—Layout
- H01L2224/06179—Corner adaptations, i.e. disposition of the bonding areas at the corners of the semiconductor or solid-state body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electronic Switches (AREA)
Abstract
Description
Claims (10)
- 내부에 조립되어 있으며, 또한 프린트 헤드의 복수의 인자용 소자를 선택적으로 구동시키기 위한 집적회로와,제 1의 방향으로 뻗는 적어도 하나의 제 1의 측면 가장자리부 및 그와 교차하는 제 2의 방향으로 뻗는 적어도 하나의 제 2의 측면 가장자리부를 갖고 있는 주면과,상기 주면에 설치되며, 또한 상기 집적회로에 도통하고 있는 제 1 및 제 2의 패드를 갖고 있는 구동 IC칩으로서,상기 제 1 및 제 2의 패드는, 상기 제 1 및 제 2의 측면 가장자리부가 교차하고 있는 공통의 모서리부에 설치되어 있으며, 또한,상기 제 1 및 제 2의 패드의 각각의 중심끼리는, 상기 제 1 및 제 2의 방향으로 위치 어긋나 있는 것을 특징으로 하는 구동 IC칩.
- 제 1항에 있어서,상기 제 1 및 제 2의 패드는, 상기 집적회로를 구동시키기 위한 전력공급, 상기 집적회로의 그라운드접속, 상기 집적회로로의 신호의 입력 및 출력의 어느 것인가를 행하게 하기 위한 패드인 것을 특징으로 하는 구동 IC칩.
- 제 1항에 있어서,상기 제 1 및 제 2의 패드는, 상기 제 1 및 제 2의 어느 방향에 있어서도 그들의 전체 및 일부가 상호 중첩되지 않도록 설치되어 있는 것을 특징으로 하는 구동 IC칩.
- 제 1항에 있어서,상기 제 1의 패드는 상기 제 2의 방향의 길이 보다도 상기 제 1 방향의 길이 쪽이 긴 직사각 형상이며, 또한 상기 제 2의 패드는 상기 제 1방향의 길이 보다도 상기 제 2 방향의 길이 쪽이 긴 직사각 형상인 것을 특징으로 하는 구동 IC칩.
- 제 4항에 있어서,상기 제 1의 패드는 상기 제 1의 측면 가장자리부에 설치되어 있음과 동시에, 상기 제 2의 패드는 상기 제 2의 측면 가장자리부에 설치되어 있는 것을 특징으로 하는 구동 IC칩.
- 제 1항에 있어서,상기 주면은, 상기 제 1 및 제 2의 측면 가장자리부를 한 쌍씩 가짐과 동시에, 4개소의 모서리부를 갖는 직사각 형상인 것을 특징으로 하는 구동 IC칩.
- 제 6항에 있어서,상기 집적회로를 상기 복수의 인자용 소자에 전기적으로 접속하기 위한 복수의 제 3의 패드를 또한 구비하고 있으며, 또한 이들 복수의 제 3의 패드는, 상기 한 쌍의 제 2의 측면 가장자리부의 한쪽에 나란히 설치되어 있는 것을 특징으로 하는 구동 IC칩.
- 제 7항에 있어서,상기 제 1 및 제 2의 패드는, 상기 4개소의 모서리부 중, 상기 한 쌍의 제 2의 측면 가장자리부의 다른 쪽 가까이에 위치하는 모서리부에 설치되어 있는 것을 특징으로 하는 구동 IC칩.
- 어레이상으로 나란하게 복수의 인자용 소자를 탑재한 기판과, 복수의 구동 IC칩을 갖고 있으며, 또한,상기 각 구동IC칩은,내부에 조립되어 있고, 또한, 상기 복수의 인자용 소자를 선택적으로 구동하기 위한 집적회로와,제 1의 방향으로 뻗는 적어도 1개의 제 1의 측면 가장자리부 및 이와 교차하는 제 2의 방향으로 뻗는 적어도 1개의 제 2의 측면 가장자리부를 갖고 있는 주면과,이 주면에 설치되며, 또한, 상기 집적회로에 도통하고 있는 제 1 및 제 2의 패드를 갖고 있는 프린트 헤드로서,상기 제 1 및 제 2의 패드는, 상기 제 1 및 제 2의 측면 가장자리부가 교차하고 있는 공통의 모서리부에 설치되어 있으며, 또한,상기 제 1 및 제 2의 패드의 각각의 중심끼리는, 상기 제 1 및 제 2의 방향으로 위치 어긋나 있는 것을 특징으로 하는 프린트 헤드.
- 제 9항에 있어서,상기 각 인자용 소자는, 발열소자인 것을 특징으로 하는 프린트 헤드.
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP36439698A JP3908401B2 (ja) | 1998-12-22 | 1998-12-22 | プリントヘッド用の駆動icチップおよびこれを備えたプリントヘッド |
JP10-364396 | 1998-12-22 | ||
PCT/JP1999/007167 WO2000037255A1 (fr) | 1998-12-22 | 1999-12-21 | Puce a circuit integre de commande et tete d'impression |
Publications (2)
Publication Number | Publication Date |
---|---|
KR20010041108A true KR20010041108A (ko) | 2001-05-15 |
KR100346744B1 KR100346744B1 (ko) | 2002-08-03 |
Family
ID=18481708
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1020007009149A KR100346744B1 (ko) | 1998-12-22 | 1999-12-21 | 구동 ic칩 및 프린트 헤드 |
Country Status (8)
Country | Link |
---|---|
US (1) | US6392685B1 (ko) |
EP (1) | EP1057650A4 (ko) |
JP (1) | JP3908401B2 (ko) |
KR (1) | KR100346744B1 (ko) |
CN (1) | CN1105649C (ko) |
CA (1) | CA2320452C (ko) |
TW (1) | TW437020B (ko) |
WO (1) | WO2000037255A1 (ko) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002170844A (ja) | 2000-12-04 | 2002-06-14 | Oki Electric Ind Co Ltd | 半導体装置 |
JP5375198B2 (ja) * | 2008-03-07 | 2013-12-25 | セイコーエプソン株式会社 | ヘッド基板およびサーマルヘッド基板 |
JP6790419B2 (ja) * | 2016-03-31 | 2020-11-25 | ブラザー工業株式会社 | ヘッドユニット、及び、液体吐出装置 |
EP4131245A4 (en) * | 2020-03-27 | 2023-05-24 | BOE Technology Group Co., Ltd. | DISPLAY PANEL AND DISPLAY DEVICE |
WO2023210426A1 (ja) * | 2022-04-28 | 2023-11-02 | ローム株式会社 | サーマルプリントヘッドおよびサーマルプリンタ |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6052365A (ja) | 1983-08-31 | 1985-03-25 | Konishiroku Photo Ind Co Ltd | 感熱記録ヘッド |
KR920702779A (ko) * | 1990-04-24 | 1992-10-06 | 아이지와 스스무 | 회로 셀·어레이를 갖춘 반도체 장치 및 데이타 입출력 장치 |
JPH0787199B2 (ja) | 1991-03-29 | 1995-09-20 | ローム株式会社 | ヘッド駆動用ic及びヘッド基板 |
US5335002A (en) | 1991-09-30 | 1994-08-02 | Rohm Co., Ltd. | Printing head and printer incorporating the same |
JP2814175B2 (ja) | 1992-02-14 | 1998-10-22 | ローム株式会社 | プリントヘッドおよびこれに搭載する駆動用ic |
WO1996011109A1 (fr) * | 1994-10-06 | 1996-04-18 | Rohm Co., Ltd. | Circuit integre servant a commander une imprimante et une tete d'impression |
US5917220A (en) * | 1996-12-31 | 1999-06-29 | Stmicroelectronics, Inc. | Integrated circuit with improved overvoltage protection |
-
1998
- 1998-12-22 JP JP36439698A patent/JP3908401B2/ja not_active Expired - Lifetime
-
1999
- 1999-12-21 CA CA002320452A patent/CA2320452C/en not_active Expired - Fee Related
- 1999-12-21 EP EP99959934A patent/EP1057650A4/en not_active Withdrawn
- 1999-12-21 KR KR1020007009149A patent/KR100346744B1/ko active IP Right Grant
- 1999-12-21 US US09/622,649 patent/US6392685B1/en not_active Expired - Lifetime
- 1999-12-21 WO PCT/JP1999/007167 patent/WO2000037255A1/ja active IP Right Grant
- 1999-12-21 CN CN99803042A patent/CN1105649C/zh not_active Expired - Fee Related
- 1999-12-22 TW TW088122602A patent/TW437020B/zh not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
WO2000037255A1 (fr) | 2000-06-29 |
US6392685B1 (en) | 2002-05-21 |
JP2000185420A (ja) | 2000-07-04 |
JP3908401B2 (ja) | 2007-04-25 |
CN1105649C (zh) | 2003-04-16 |
TW437020B (en) | 2001-05-28 |
CA2320452A1 (en) | 2000-06-29 |
CN1291138A (zh) | 2001-04-11 |
EP1057650A4 (en) | 2001-11-14 |
KR100346744B1 (ko) | 2002-08-03 |
CA2320452C (en) | 2004-11-02 |
EP1057650A1 (en) | 2000-12-06 |
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