KR102397140B1 - 임의의 관통 비아가 없는 인터포저를 포함하는 반도체 구조의 제조 방법 - Google Patents

임의의 관통 비아가 없는 인터포저를 포함하는 반도체 구조의 제조 방법 Download PDF

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KR102397140B1
KR102397140B1 KR1020187034604A KR20187034604A KR102397140B1 KR 102397140 B1 KR102397140 B1 KR 102397140B1 KR 1020187034604 A KR1020187034604 A KR 1020187034604A KR 20187034604 A KR20187034604 A KR 20187034604A KR 102397140 B1 KR102397140 B1 KR 102397140B1
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contact pads
way
temporary support
interconnection layer
layer
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KR20190015707A (ko
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빗-옌 응우옌
루도빅 에카르노
모하메드 나디아 벤
크리스토프 말빌
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소이텍
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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Wire Bonding (AREA)
KR1020187034604A 2016-05-30 2017-05-24 임의의 관통 비아가 없는 인터포저를 포함하는 반도체 구조의 제조 방법 Active KR102397140B1 (ko)

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Application Number Priority Date Filing Date Title
FR1654831 2016-05-30
FR1654831A FR3051971B1 (fr) 2016-05-30 2016-05-30 Procede de fabrication d'une structure semi-conductrice comprenant un interposeur
PCT/EP2017/062556 WO2017207390A1 (en) 2016-05-30 2017-05-24 Method for fabrication of a semiconductor structure including an interposer free from any through via

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Publication Number Publication Date
KR20190015707A KR20190015707A (ko) 2019-02-14
KR102397140B1 true KR102397140B1 (ko) 2022-05-16

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US (1) US11114314B2 (https=)
KR (1) KR102397140B1 (https=)
CN (1) CN109196627B (https=)
DE (1) DE112017002718T5 (https=)
FR (1) FR3051971B1 (https=)
SG (2) SG11201810104VA (https=)
TW (1) TWI712106B (https=)
WO (1) WO2017207390A1 (https=)

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