TWI752968B - 被配置為於超過１ＧＨｚ操作的３Ｄ電子模組的集體製造的方法 - Google Patents

被配置為於超過１ＧＨｚ操作的３Ｄ電子模組的集體製造的方法 Download PDF

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TWI752968B
TWI752968B TW106120053A TW106120053A TWI752968B TW I752968 B TWI752968 B TW I752968B TW 106120053 A TW106120053 A TW 106120053A TW 106120053 A TW106120053 A TW 106120053A TW I752968 B TWI752968 B TW I752968B
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wafer
electronic
reconstituted
packages
ball
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TW106120053A
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TW201804578A (zh
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克里斯汀 佛
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３Ｄ波拉斯公司
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Abstract

本發明之標的為一種3D電子模組的集體製造之方法，每一個3D電子模組包含至少兩個表面可轉移並在其操作溫度及頻率被測試的球柵電子封裝的堆疊。該方法包含：-製造重構晶圓的步驟，以下列順序根據下列子步驟製造每一個重構晶圓：○A1)將該些電子封裝以球側置於第一黏性表層上，○B1)將該些電子封裝模封在樹脂中並聚合化樹脂以獲得中級晶圓，○C1)在該中級晶圓相對於該些球之的面上薄化該中級晶圓，○D1)移除該第一黏性表層並將該中級晶圓以相對於該些球的側置於第二黏性表層上，○E1)在該球側面上薄化該中級晶圓， ○F1)形成球側重佈層，○G1)移除該第二黏性表層獲得比該些電子封裝的原始厚度更小的厚度之重構晶圓，-在完成該些前述步驟後獲得數個重構晶圓，堆疊該些重構晶圓，-切割堆疊的重構晶圓以獲得3D模組。

Description

被配置為於超過1GHz操作的3D電子模組的集體製造的方法
本發明之領域在於包含至少兩個電子晶片的堆疊之具有減少的厚度之3D電子模組的集體製造。
於高頻率操作的組件(記憶體、處理器等等)出現在市面上意味著使用未封裝的晶片(裸晶)產生新的效率問題。使用探針尖端來測試超過約1GHz的頻率的裸晶變得非常棘手。主要的結果為在這些組件堆疊於三維(3D)電子模組中的情況中，某些晶片將能夠在最大頻率操作，其他則不能；因此包含複數晶片的模組將無法在最大頻率操作。
迴避此困難的一種方式為使用封裝晶片，亦即被置於封裝中的那些，其本身可被完整測試。確實，封裝包含焊球形式的輸出，其間距比晶片的襯墊大許多： 晶片襯墊的間距：50至100μm，封裝晶片的球柵封裝之間距：從400至800μm。
因此可使用測試插座並可在可能大於1GHz的頻率及介於-55℃及+125℃之間的操作溫度測試封裝。
但是封裝的堆疊比晶片的堆疊更厚，以致於產生同樣較厚的3D模組，然而希望獲得具有減少厚度的3D模組。
基於此觀察，因此必須找到適合能夠在高頻率操作之這些封裝的堆疊技術，使得獲得具有減少厚度的3D模組變得可行。
因此，至今仍需要一種3D電子模組的集體製造方法，其同時滿足所有上述需求，亦即在特別是大於1GHz的操作頻率之電子晶片的可靠性；在介於-55℃及+125℃之間的操作溫度；以及所得之3D模組之減少的厚度。
更精確來說，本發明之標的為一種3D電子模組的集體製造之方法，每一個3D電子模組包含至少兩個表面可轉移並在其操作溫度及頻率被測試的球柵電子封裝的堆疊，該方法包含：-製造重構晶圓的步驟，以下列順序根據下列子步驟製造每一個重構晶圓； ○A1)將該些電子封裝以球側置於第一黏性表層上，○B1)將該些電子封裝模封在樹脂中並聚合化樹脂以獲得中級晶圓，○C1)在相對於該些球之該中級晶圓的面上薄化該中級晶圓，○D1)移除該第一黏性表層並將該中級晶圓以相對於該些球的側置於第二黏性表層上，○E1)在該球側面上薄化該中級晶圓，○F1)形成球側重佈層，○G1)移除該第二黏性表層以獲得比該些電子封裝的原始厚度更小的厚度之重構晶圓，-在完成該些前述步驟後獲得數個重構晶圓，堆疊該些重構晶圓，-切割堆疊的重構晶圓以獲得3D模組。
本發明的標的亦為一種3D電子模組的集體製造之方法，每一個3D電子模組包含至少兩個表面可轉移並在其操作溫度及頻率被測試的球柵電子封裝的堆疊，該方法包含：-製造重構晶圓的步驟，以下列順序根據下列子步驟製造每一個重構晶圓；○A2)將該些電子封裝以相對於球的側置於第一黏性表層上，○B2)將該些電子封裝模封在樹脂中並聚合化樹 脂以獲得中級晶圓，○C2)在該中級晶圓之球側的面上薄化該中級晶圓，○D2)形成球側重佈層，○E2)移除該第一黏性表層並將該經薄化的中級晶圓以該RDL側置於第二黏性表層上，○F2)在該中級晶圓之相對於該些球的面上薄化該中級晶圓，○G2)移除該第二黏性表層以獲得比該些電子封裝的原始厚度更小的厚度之重構晶圓，-在完成該些前述步驟後獲得數個重構晶圓，堆疊該些重構晶圓，-切割堆疊的重構晶圓以獲得3D模組。
因此有兩種薄化步驟。
電子封裝為BGA封裝或覆晶封裝；BGA電子封裝可包含中央突起。
操作頻率尤其大於1GHz，及/或操作溫度介於例如-55℃及125℃之間。
在將電子封裝置於第一黏性表層上的步驟之前，以移除電子封裝的球之步驟取代在中級晶圓之球側的面上薄化中級晶圓之步驟。
1‧‧‧黏性表層
2‧‧‧裸晶
3‧‧‧中央突起
4‧‧‧連結球
4’‧‧‧經薄化的球
5‧‧‧樹脂
6‧‧‧中級晶圓
8‧‧‧黏性表層
10‧‧‧電子封裝
11‧‧‧樹脂
21‧‧‧連結電線
22‧‧‧互連電路
41‧‧‧襯墊
60‧‧‧重構晶圓
61‧‧‧重佈層
70‧‧‧切割路徑
610‧‧‧接點
615‧‧‧樹脂
611‧‧‧導電體
在閱讀過以非限制性範例和參考附圖的方式 提出之詳細說明後，本發明之其他特徵及優點將變得更為明顯，圖中：第1圖以剖面圖示意性表示具有隆起(第1a圖)和無隆起(第1b圖)之BGA型及覆晶型的電子封裝，第2圖繪示根據本發明的一示範方法之各種步驟，第3圖繪示根據本發明的另一種示範方法之各種步驟，第4圖以剖面圖示意性表示藉由根據本發明之方法所得之示範重構晶圓，第5圖以剖面圖示意性表示藉由根據本發明之方法所得之4個重構晶圓的示範堆疊。
在所有圖中，以相同參考符號標示相同元件。
在前面的說明中，參考圖的方位使用「上」、「下」、「前」、「後」、「側」的措詞。只要可根據其他方位定位裝置，方向性術語僅為例式性而非限制性。
裸晶的電氣測試無法保證在高於1GHz的頻率之可靠操作。另一方面，電子封裝的測試，亦即具有連接球的電子組件，其為可表面轉移且包括晶片，可應用於超過1GHz的這些頻率並亦保證介於-55℃及+125℃之間的操作溫度。
本發明基於晶圓的製造，其並非由裸晶而是由電子封裝重構而成。一旦晶圓已經由N個「良好的」 BGA封裝重構而成，(N可多達數百)，將例如已在法國專利FR 03 07977及FR 06 07442進行它們的堆疊、切割等等。
電子封裝10，在第1圖中顯示其之一些範例，是指：
-具有連結球4(或焊球)之(BGA或球柵陣列)球柵封裝10，亦即封裝在樹脂11中的裸晶2，此裸晶2具有連接至設有該些球4之互連電路22(一般具有多層)的連結電線21。嵌入樹脂中的這些電線連接至電路的上表面(第1b圖)，或這些電線連接至電路下方的面且亦受到樹脂保護，藉此在封裝下方形成突出中央隆起3(或中央突起)(第1a圖)。
這些封裝的連結球4具有通常介於200μm及400μm之間的厚度eb；在封裝中央的隆起3(記憶體封裝中必定會有)，通常約150μm；封裝本體的厚度ec(亦即無連結球的封裝)通常介於0.8mm及0.9mm之間；封裝的總厚度E(E=eb+ec)因此介於0.82mm及1.3mm之間。
-覆晶組件10，亦即連接至稱為重佈層之設有連結球4之互連層22的未封裝晶片2(第1c圖)。根據本發明這種覆晶組件視為封裝10，因為其：○可轉移到像是球柵封裝(BGA)的基板上，○可在出廠給客戶前加以測試，因為球的間距(從100至500μm)比晶片的襯墊間距(從40至 100μm)大上許多，故可使用測試插座並因此在可能高於1GHz的頻率測試組件。
此外，與裸晶相比，較容易有這種覆晶封裝，且它們比BGA封裝更輕巧。這些覆晶封裝不會有某些BGA封裝所示的任何隆起。這些覆晶封裝的連結球4具有通常介於50μm至150μm的厚度；覆晶封裝本體的厚度ec(亦即無連結球的封裝)通常介於100μm及400μm之間；封裝的總厚度E(E=eb+ec)因此介於150μm及550μm之間。
為了簡明在後圖中並未顯示襯墊41及電路或互連層22。
由例如Xilinx、Micron、Samsung等等的各種製造商販賣這種經測試封裝10。
根據本發明，包含在操作溫度及頻率測試之至少兩個可表面轉移球柵電子封裝10的堆疊之3D電子模組可以下列方式集體製造：-製造數個重構晶圓，每一個重構晶圓60僅包含N個「良好的」封裝，亦即僅包含經測試的封裝，-堆疊重構晶圓，-切割堆疊的重構晶圓以獲得3D模組。
製造重構晶圓的步驟進展取決於電子封裝是否以連結球側或相對側置於第一黏性表層上。採用相同步驟，但以不同順序進行。
連同第2圖說明當封裝10以連結球的側放置時 的步驟進展。
-步驟A1：N個封裝10以連結球4的側藉由取放(Pick and Place)設備置於第一黏性表層1上，英文亦稱為「膠帶(tape)」。但無焊接連結球的步驟；球4僅臨時固定至此黏膠1。這些N個封裝皆相同。
-步驟B1：例如藉由壓縮或藉由鑄造將封裝10模封於樹脂5中。接下來，聚合化樹脂。於是獲得中級晶圓6。
-步驟C1：薄化此中級晶圓之後面的側(亦即相對於球)。封裝10之後面的薄化使得到達位在封裝10內的晶片2之後面變得可能：薄化可限制於晶片2之後面的出現即止或可甚至薄化晶片2本身。封裝10之本體的厚度ec可減少約30%至35%。
-步驟D1：移除第一黏性表層1並將經過薄化的中級晶圓以相對於封裝焊球4的側置於第二黏性表層8上(在步驟C1中薄化的側被黏在黏性表層8上)。
-步驟E1：執行第二薄化以減少焊球4的厚度eb。這些球例如由錫/銀/銅(Sn/Ag/Cu，亦簡稱為SAC)構成。獲得經薄化的球4’。
-步驟F1：在經薄化的球4’側上形成重佈層61(亦稱為RDL層，縮寫代表ReDistribution Layer)。此RDL層形成自可光蝕刻樹脂615，包含與球4’連接的電性接點610以及包含將接點610連接至封裝周圍(亦即至切割路徑70)的導電體611之一或更多子層。確 實，當執行晶圓60的堆疊時，會在3D模組的垂直面上產生連接至存在於周圍上的導電體611區域之垂直(沿著堆疊的方向)導電體。以傳統沉積製造此RDL層61：使用鈦/鎢然後銅類型的擴散阻障來沉積可光蝕刻的介電質及金屬。
-步驟G1：移除第二黏性表層8以獲得重構晶圓60。
連同第3圖說明當封裝10以相對於連結球4的側放置時的步驟進展。
-步驟A2：將封裝10以未承載球4的側黏在第一黏性表層1上。使用之取放設備的頭必須適合抓取沒有如前面情況中連續平坦表面的封裝。此設備的吸頭為中空以避免封裝10之球4及可能的中央隆起3。
-步驟B2：例如藉由壓縮或藉由鑄造將封裝模封於樹脂5中，程度到達球4的平面或稍微高於球的平面。封裝10以相對於球的側轉移到第一黏性表層上，不會有可能出現在第2圖的步驟B1中當填充樹脂在球的表面與第一黏性表層之間的空間時的問題。接下來，聚合化樹脂。於是獲得中級晶圓6。
-步驟C2：施加薄化至中級晶圓6之包含球4的面以減少球的體積，及最重要地，球的厚度。獲得經薄化的球4’。
-步驟D2：如步驟F1中般藉由重佈層61(RDL)執行經薄化的球4’與未來垂直導電體的互連，其包含與球4’連接的電性接點610及一或兩個重佈子層。
-步驟E2：從第一黏性表層1脫除附加有RDL層的經薄化中級晶圓6，並將其翻過來以RDL層的側黏於第二黏性表層8上。
-步驟F2：接著在相對於RDL層的面上執行薄化，如步驟C1所述般。
-步驟G2：移除第二黏性表層8以獲得重構晶圓60。
當完成這些步驟時，獲得小厚度的重構晶圓，僅包含「良好的」封裝(N個封裝)，亦即，僅經過測試的封裝，且意欲將其堆疊在以相同方式重構的其他晶圓上。
可將如前述般進行製造重構晶圓60之步驟的兩種方式用於有或無中央隆起3的BGA封裝10或覆晶型封裝10。在無隆起3的BGA封裝或覆晶型封裝的情況中，薄化球側上的面之步驟不限於中央突起(步驟E1或C2)並且薄化可趨近封裝本體的表面約50μm。在無隆起的BGA封裝或覆晶型封裝的情況中，這讓最終封裝的總厚度稍微減少約100μm。
在將封裝10轉移到步驟A1或A2的黏性表層1之前，可將無中央突起3之經測試封裝10去球(亦即移除球4)。在獲得經測試封裝後集體執行此去球；可例如機械性或藉由電漿氣相化學侵蝕執行。在這些情況下，曾經承載球的封裝表面僅包含襯墊41(第1圖中可見)並且有或無球4的殘留。薄化的步驟E1或C2變得多餘。如同已在步驟F1或D2中說明般，產生RDL 61以連接並非球4’而是直接連 接襯墊41。此方法的好處尤其在於封裝之稍小的厚度(本體+球)。
下表總結在BGA或覆晶封裝10的這些步驟程序中獲得的厚度。
Figure 106120053-A0202-12-0011-2
球4或4’所示的厚度包括襯墊41的厚度。
重構晶圓60的厚度(亦即封裝及RDL的厚度)因此為：-針對BGA封裝10的晶圓60介於700μm及860μm之間，-針對覆晶封裝10的晶圓60介於95μm及360μm之 間。
第4圖顯示藉由一或其他方法獲得的重構晶圓60，其上標有切割路徑70。接著將這些重構晶圓60互相堆疊同時對準切割路徑70，並藉由膠水15黏在一起，可從第5圖中見到。接下來，沿著切割路徑切割堆疊以獲得N個3D電子模組，其尤其將輔以形成在3D模組的垂直面上之垂直匯流排。

Claims (7)

  1. 一種三維(3D)電子模組的集體製造之方法，每一個3D電子模組包含至少兩個表面可轉移並在其操作溫度及頻率被測試的球柵電子封裝(10)的堆疊，該方法包含：- 製造重構晶圓的步驟，以下列順序根據下列子步驟製造每一個重構晶圓(60)，○A1)將該些電子封裝(10)以球(4)側置於第一黏性表層(1)上，○B1)將該些電子封裝(10)模封在樹脂(5)中並聚合化樹脂以獲得中級晶圓(6)，○C1)在相對於該些球之該中級晶圓的面上薄化該中級晶圓(6)，○D1)移除該第一黏性表層(1)並將該中級晶圓以相對於該些球(4)的側置於第二黏性表層(8)上，○E1)在該球側面上薄化該中級晶圓，○F1)形成球側重佈層(61)，○G1)移除該第二黏性表層(8)以獲得比該些電子封裝的原始厚度更小的厚度之重構晶圓(60)，- 在完成該些前述子步驟後獲得數個重構晶圓，堆疊該些重構晶圓，- 切割堆疊的重構晶圓以獲得3D模組。
  2. 一種三維(3D)電子模組的集體製造之方法，每一個3D 電子模組包含至少兩個表面可轉移並在其操作溫度及頻率被測試的球柵電子封裝(10)的堆疊，該方法包含：- 製造重構晶圓的步驟，以下列順序根據下列子步驟製造每一個重構晶圓(60)，○A2)將該些電子封裝(10)以相對於球的側置於第一黏性表層(1)上，○B2)將該些電子封裝(10)模封在樹脂(5)中並聚合化樹脂以獲得中級晶圓(6)，○C2)在該中級晶圓之球側的面上薄化該中級晶圓(6)，○D2)形成球側重佈層(61)，○E2)移除該第一黏性表層(1)並將該經薄化的中級晶圓以該RDL側置於第二黏性表層(8)上，○F2)在該中級晶圓之相對於該些球的面上薄化該中級晶圓，○G2)移除該第二黏性表層(8)以獲得比該些電子封裝的原始厚度更小的厚度之重構晶圓(60)，- 在完成該些前述子步驟後獲得數個重構晶圓，堆疊該些重構晶圓，- 切割堆疊的重構晶圓以獲得3D模組。
  3. 如申請專利範圍第1或2項的3D電子模組的集體製造之方法，其中該些電子封裝(10)為BGA封裝或覆晶封裝。
  4. 如前述申請專利範圍第1或2項的3D電子模組的集體製造之方法，其中該操作頻率大於1GHz。
  5. 如前述申請專利範圍第1或2項的3D電子模組的集體製造之方法，其中該操作溫度介於-55℃及125℃之間。
  6. 如前述申請專利範圍第1或2項的3D電子模組的集體製造之方法，其中該些電子封裝(10)包含中央突起(3)。
  7. 如申請專利範圍第1或2項的3D電子模組的集體製造之方法，其中在將該些電子封裝置於該第一黏性表層上的步驟之前，以移除該些電子封裝的該些球(4)之步驟取代在該中級晶圓之球側的面上薄化該中級晶圓(6)之該步驟。
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