JP6963424B2 - 1GHzを超えて動作するように構成された3次元電子モジュールの一括製造方法 - Google Patents
1GHzを超えて動作するように構成された3次元電子モジュールの一括製造方法 Download PDFInfo
- Publication number
- JP6963424B2 JP6963424B2 JP2017118360A JP2017118360A JP6963424B2 JP 6963424 B2 JP6963424 B2 JP 6963424B2 JP 2017118360 A JP2017118360 A JP 2017118360A JP 2017118360 A JP2017118360 A JP 2017118360A JP 6963424 B2 JP6963424 B2 JP 6963424B2
- Authority
- JP
- Japan
- Prior art keywords
- ball
- sub
- wafer
- package
- electronic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 28
- 235000012431 wafers Nutrition 0.000 claims description 79
- 239000002313 adhesive film Substances 0.000 claims description 31
- 238000000034 method Methods 0.000 claims description 18
- 239000011347 resin Substances 0.000 claims description 18
- 229920005989 resin Polymers 0.000 claims description 18
- 238000000465 moulding Methods 0.000 claims description 6
- 238000010030 laminating Methods 0.000 claims description 4
- 230000000379 polymerizing effect Effects 0.000 claims description 4
- 239000004820 Pressure-sensitive adhesive Substances 0.000 claims description 2
- 239000004020 conductor Substances 0.000 description 4
- 238000007689 inspection Methods 0.000 description 4
- 229910000679 solder Inorganic materials 0.000 description 4
- 239000010949 copper Substances 0.000 description 3
- 238000003475 lamination Methods 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 238000005266 casting Methods 0.000 description 2
- 230000006835 compression Effects 0.000 description 2
- 238000007906 compression Methods 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 230000014509 gene expression Effects 0.000 description 2
- 238000006116 polymerization reaction Methods 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 239000000523 sample Substances 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000008719 thickening Effects 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3135—Double encapsulation or coating and encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
- H01L24/92—Specific sequence of method steps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/321—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68359—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68368—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0612—Layout
- H01L2224/0613—Square or rectangular array
- H01L2224/06134—Square or rectangular array covering only portions of the surface to be connected
- H01L2224/06135—Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0612—Layout
- H01L2224/0613—Square or rectangular array
- H01L2224/06134—Square or rectangular array covering only portions of the surface to be connected
- H01L2224/06136—Covering only the central area of the surface to be connected, i.e. central arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
- H01L2225/1035—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
- H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
- H01L2924/141—Analog devices
- H01L2924/142—HF devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
- H01L2924/143—Digital devices
- H01L2924/1434—Memory
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18165—Exposing the passive side of the semiconductor or solid-state body of a wire bonded chip
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Wire Bonding (AREA)
- Dicing (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Finish Polishing, Edge Sharpening, And Grinding By Specific Grinding Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Description
チップのパッドの間隔は、50から100μm、
チップを封入するボール・グリッド・パッケージの間隔は、400から800μmである。
− 再構成ウェーハを製造するステップであって、各再構成ウェーハは、次の順序で次のサブステップ、
・A1)ボール側で、第1の粘着膜上に電子パッケージを配置するサブステップと、
・B1)樹脂で電子パッケージを成形し樹脂を重合して、中間ウェーハを取得するサブステップと、
・C1)ボールと反対の中間ウェーハの面上で中間ウェーハを薄化するサブステップと、
・D1)第1の粘着膜を除去し、ボールと反対側で、第2の粘着膜上に中間ウェーハを配置するサブステップと、
・E1)ボール側の面上で中間ウェーハを薄化するサブステップと、
・F1)ボール側再配線層を形成するサブステップと、
・G1)電子パッケージの元の厚さより小さい厚さの再構成ウェーハを取得するために第2の粘着膜を除去するサブステップと
に従う第1の実施形態に従って製造される、再構成ウェーハを製造するステップと、
− 前のサブステップの完了で取得されたいくつかの再構成ウェーハを積層するステップと、
− 3次元モジュールを取得するために積層された再構成ウェーハをダイシングするステップと
を含む、3次元電子モジュールの一括製造方法である。
− 再構成ウェーハを製造するステップであって、各再構成ウェーハは、次の順序で次のサブステップ、
・A2)ボールと反対側で第1の粘着膜上に電子パッケージを配置するサブステップと、
・B2)樹脂で電子パッケージを成形し樹脂を重合して、中間ウェーハを取得するサブステップと、
・C2)ボール側の、中間ウェーハの面上で中間ウェーハを薄化するサブステップと、
・D2)ボール側再配線層を形成するサブステップと、
・E2)第1の粘着膜を除去し、RDL側で、第2の粘着膜上に薄化された中間ウェーハを配置するサブステップと、
・F2)ボールと反対の中間ウェーハの面上で中間ウェーハを薄化するサブステップと、
・G2)電子パッケージの元の厚さより小さい厚さの再構成ウェーハを取得するために第2の粘着膜を除去するサブステップと
に従う第2の実施形態に従って製造される、再構成ウェーハを製造するステップと、
− 前のサブステップの完了で取得されたいくつかの再構成ウェーハを積層するステップと、
− 3次元モジュールを取得するために積層された再構成ウェーハをダイシングするステップと
を含む、3次元電子モジュールの一括製造方法である。
いくつかの実施例が図1に示される、電子パッケージ10は、以下を指す。
− 接続ボール4(またははんだボール)を有する(BGAまたはボール・グリッド・アレイ)ボール・グリッド・パッケージ10、すなわち樹脂11に封入されたベアチップ2であって、このベアチップ2は、前記ボール4を備えた(一般に数個の層を有する)相互接続回路22に結合された接続ワイヤ21を出している。樹脂に埋め込まれたこれらのワイヤは、回路の上面に結合され(図1b)、またはこれらのワイヤは回路の下の面に結合されて同様に樹脂によって保護され、それによりパッケージの下に突出する中央の厚くなった部分3(または中央突起部)を形成する(図1a)。
・ボール・グリッド・パッケージ(BGA)のように基板上に移動することができ、
・ボールの間隔(100から500μm)は、チップのパッドの間隔(40から100μm)よりはるかに大きく、検査ソケットを使用して、したがって場合によっては1GHzを上まわる周波数で部品を検査することを可能にするので、顧客への納入前に検査することができる
ことから、本発明によれば、パッケージ10であると考えられる。
− 各再構成ウェーハ60がN個の「良品」パッケージ、すなわち検査済みパッケージだけを含む、いくつかの再構成ウェーハの製造と、
− 再構成ウェーハの積層と、
− 3次元モジュールを取得するための積層された再構成ウェーハのダイシングと
で一括して製造される。
− ステップA1:N個のパッケージ10は、ピックアンドプレイス機構を用いて接続ボール4の側で、英語で「テープ(tape)」とも呼ばれる第1の粘着膜1上に配置される。しかし、接続ボールをはんだ付けするステップはなく、ボール4はただ、この粘着剤1に仮に固定される。これらのN個のパッケージはすべて同じである。
− ステップA2:パッケージ10は、ボール4を支持していない側で第1の粘着膜1にはり付けられる。使用されるピックアンドプレイス機構のヘッドは、前の事例のように連続的な平板表面を有さないパッケージをつかむのに適していなければならない。この機構の吸引ヘッドは、パッケージ10のボール4および場合によってはあり得る中央の厚くなった部分3を避けるようにくり抜かれている。
− BGAパッケージ10を持つウェーハ60の場合700μmから860μmの間、
− フリップチップパッケージ10を持つウェーハ60の場合95μmから360μmの間
である。
3 中央突起部
4 ボール
5 樹脂
6 中間ウェーハ
8 第2の粘着膜
10 ボールグリッド電子パッケージ
60 再構成ウェーハ
61 ボール側再配線層
Claims (7)
- 各3次元電子モジュールが、ボールグリッド電子パッケージ(10)の動作温度および周波数で検査された、少なくとも2つの、表面移動可能な、前記ボールグリッド電子パッケージ(10)の積層を含む、3次元電子モジュールの一括製造方法であって、
− 再構成ウェーハを製造するステップであって、各再構成ウェーハ(60)は、次の順序で次のサブステップ、
・A1)ボール(4)側で、第1の粘着膜(1)上に前記電子パッケージ(10)を配置するサブステップと、
・B1)樹脂(5)で前記電子パッケージ(10)を成形し前記樹脂を重合して、中間ウェーハ(6)を取得するサブステップと、
・C1)前記ボールと反対の前記中間ウェーハの面上で前記中間ウェーハ(6)を薄化するサブステップと、
・D1)前記第1の粘着膜(1)を除去し、前記ボール(4)と反対側で、第2の粘着膜(8)上に前記中間ウェーハを配置するサブステップと、
・E1)前記ボール側の面上で前記中間ウェーハを薄化するサブステップと、
・F1)ボール側再配線層(61)を形成するサブステップと、
・G1)前記電子パッケージの元の厚さより小さい厚さの再構成ウェーハ(60)を取得するために前記第2の粘着膜(8)を除去するサブステップと、
に従って製造される、再構成ウェーハを製造するステップと、
− 前記サブステップの完了で取得されたいくつかの再構成ウェーハを積層するステップと、
− 3次元モジュールを取得するために前記積層された再構成ウェーハをダイシングするステップと、
を含む、3次元電子モジュールの一括製造方法。 - 各3次元電子モジュールが、ボールグリッド電子パッケージ(10)の動作温度および周波数で検査された、少なくとも2つの、表面移動可能な、前記ボールグリッド電子パッケージ(10)の積層を含む、3次元電子モジュールの一括製造方法であって、
− 再構成ウェーハを製造するステップであって、各再構成ウェーハ(60)は、次の順序で次のサブステップ、
・A2)前記ボールと反対側で、第1の粘着膜(1)上に前記電子パッケージ(10)を配置するサブステップと、
・B2)樹脂(5)で前記電子パッケージ(10)を成形し前記樹脂を重合して、中間ウェーハ(6)を取得するサブステップと、
・C2)ボール側の、前記中間ウェーハの面上で前記中間ウェーハ(6)を薄化するサブステップと、
・D2)ボール側再配線層(61)を形成するサブステップと、
・E2)前記第1の粘着膜(1)を除去し、RDL側で、第2の粘着膜(8)上に前記薄化された中間ウェーハを配置するサブステップと、
・F2)前記ボールと反対の前記中間ウェーハの前記面上で前記中間ウェーハを薄化するサブステップと、
・G2)前記電子パッケージの元の厚さより小さい厚さの再構成ウェーハ(60)を取得するために前記第2の粘着膜(8)を除去するサブステップと、
に従って製造される、再構成ウェーハを製造するステップと、
− 前記サブステップの完了で取得されたいくつかの再構成ウェーハを積層するステップと、
− 3次元モジュールを取得するために前記積層された再構成ウェーハをダイシングするステップと、
を含む、3次元電子モジュールの一括製造方法。 - 前記電子パッケージ(10)はBGAパッケージまたはフリップチップパッケージであることを特徴とする、請求項1または2に記載の3次元電子モジュールの一括製造方法。
- 前記動作周波数は1GHzより大きいことを特徴とする、請求項1〜3のいずれか一項に記載の3次元電子モジュールの一括製造方法。
- 前記動作温度は−55℃から125℃の間にあることを特徴とする、請求項1〜4のいずれか一項に記載の3次元電子モジュールの一括製造方法。
- 前記電子パッケージ(10)は中央突起部(3)を含むことを特徴とする、請求項1〜5のいずれか一項に記載の3次元電子モジュールの一括製造方法。
- ボール側の、前記中間ウェーハの前記面上で前記中間ウェーハ(6)を薄化する前記ステップは、前記第1の粘着膜上に前記電子パッケージを配置する前記ステップの前に前記電子パッケージの前記ボール(4)を除去するステップで置き換えられることを特徴とする、請求項1〜5のいずれか一項に記載の3次元電子モジュールの一括製造方法。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR1655798A FR3053158B1 (fr) | 2016-06-22 | 2016-06-22 | Procede de fabrication collective de modules electroniques 3d configures pour fonctionner a plus d'1 ghz |
FR1655798 | 2016-06-22 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2017228778A JP2017228778A (ja) | 2017-12-28 |
JP6963424B2 true JP6963424B2 (ja) | 2021-11-10 |
Family
ID=56611472
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2017118360A Active JP6963424B2 (ja) | 2016-06-22 | 2017-06-16 | 1GHzを超えて動作するように構成された3次元電子モジュールの一括製造方法 |
Country Status (6)
Country | Link |
---|---|
US (1) | US9899250B2 (ja) |
EP (1) | EP3261116B1 (ja) |
JP (1) | JP6963424B2 (ja) |
CN (1) | CN107527895B (ja) |
FR (1) | FR3053158B1 (ja) |
TW (1) | TWI752968B (ja) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11127604B2 (en) * | 2018-01-05 | 2021-09-21 | Innolux Corporation | Manufacturing method of semiconductor device |
US10825696B2 (en) | 2018-07-02 | 2020-11-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Cross-wafer RDLs in constructed wafers |
KR102609475B1 (ko) * | 2018-10-23 | 2023-12-06 | 주식회사 다이셀 | 반도체 장치 제조 방법 |
JP7224138B2 (ja) | 2018-10-23 | 2023-02-17 | 株式会社ダイセル | 半導体装置製造方法 |
JP7201386B2 (ja) | 2018-10-23 | 2023-01-10 | 株式会社ダイセル | 半導体装置製造方法 |
US11004758B2 (en) | 2019-06-17 | 2021-05-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuit package and method |
Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH08115989A (ja) * | 1994-08-24 | 1996-05-07 | Fujitsu Ltd | 半導体装置及びその製造方法 |
JP2001313350A (ja) * | 2000-04-28 | 2001-11-09 | Sony Corp | チップ状電子部品及びその製造方法、並びにその製造に用いる疑似ウエーハ及びその製造方法 |
JP4571320B2 (ja) * | 2001-02-02 | 2010-10-27 | Okiセミコンダクタ株式会社 | 半導体チップパッケージ |
JP2003273317A (ja) * | 2002-03-19 | 2003-09-26 | Nec Electronics Corp | 半導体装置及びその製造方法 |
FR2857157B1 (fr) | 2003-07-01 | 2005-09-23 | 3D Plus Sa | Procede d'interconnexion de composants actif et passif et composant heterogene a faible epaisseur en resultant |
JP2006332141A (ja) * | 2005-05-24 | 2006-12-07 | Matsushita Electric Ind Co Ltd | 半導体装置の製造方法 |
FR2905198B1 (fr) | 2006-08-22 | 2008-10-17 | 3D Plus Sa Sa | Procede de fabrication collective de modules electroniques 3d |
JP2011014844A (ja) * | 2009-07-06 | 2011-01-20 | Casio Computer Co Ltd | 半導体装置の製造方法 |
EP2330618A1 (en) * | 2009-12-04 | 2011-06-08 | STMicroelectronics (Grenoble 2) SAS | Rebuilt wafer assembly |
JP5803276B2 (ja) * | 2011-05-26 | 2015-11-04 | 富士通株式会社 | 半導体装置の製造方法 |
JP2013093568A (ja) * | 2011-10-06 | 2013-05-16 | Nagase & Co Ltd | 電気部品の積層構造体の製造方法、電気部品の平面配置集合体及び電気部品の平面配置集合体の積層結合方法 |
JP2014056924A (ja) * | 2012-09-12 | 2014-03-27 | Hitachi Chemical Co Ltd | 半導体装置の製造方法及びそれに用いる熱硬化性樹脂組成物並びにそれらにより得られる半導体装置 |
US9508674B2 (en) * | 2012-11-14 | 2016-11-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Warpage control of semiconductor die package |
US9368438B2 (en) * | 2012-12-28 | 2016-06-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package on package (PoP) bonding structures |
TWI518852B (zh) * | 2013-10-02 | 2016-01-21 | 矽品精密工業股份有限公司 | 半導體封裝件及其製法 |
CN105575821A (zh) * | 2015-12-22 | 2016-05-11 | 华进半导体封装先导技术研发中心有限公司 | 多层堆叠扇出型封装及其制备方法 |
-
2016
- 2016-06-22 FR FR1655798A patent/FR3053158B1/fr not_active Expired - Fee Related
-
2017
- 2017-06-13 US US15/621,908 patent/US9899250B2/en active Active
- 2017-06-14 EP EP17175943.4A patent/EP3261116B1/fr active Active
- 2017-06-15 TW TW106120053A patent/TWI752968B/zh active
- 2017-06-16 JP JP2017118360A patent/JP6963424B2/ja active Active
- 2017-06-22 CN CN201710479941.1A patent/CN107527895B/zh active Active
Also Published As
Publication number | Publication date |
---|---|
US9899250B2 (en) | 2018-02-20 |
TW201804578A (zh) | 2018-02-01 |
EP3261116A1 (fr) | 2017-12-27 |
FR3053158B1 (fr) | 2018-11-16 |
FR3053158A1 (fr) | 2017-12-29 |
TWI752968B (zh) | 2022-01-21 |
JP2017228778A (ja) | 2017-12-28 |
EP3261116B1 (fr) | 2019-10-02 |
CN107527895B (zh) | 2023-05-12 |
US20170372935A1 (en) | 2017-12-28 |
CN107527895A (zh) | 2017-12-29 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP6963424B2 (ja) | 1GHzを超えて動作するように構成された3次元電子モジュールの一括製造方法 | |
US20200350293A1 (en) | Semiconductor device having laterally offset stacked semiconductor dies | |
US9570429B2 (en) | Methods of fabrication and testing of three-dimensional stacked integrated circuit system-in-package | |
US7999377B2 (en) | Method and structure for optimizing yield of 3-D chip manufacture | |
US20200203331A1 (en) | Semiconductor device using emc wafer support system and fabricating method thereof | |
CN107452725B (zh) | 制造半导体封装的方法 | |
US7683459B2 (en) | Bonding method for through-silicon-via based 3D wafer stacking | |
KR101818507B1 (ko) | 반도체 패키지 | |
JP2021520071A (ja) | 多層3d集積化のダイスタック | |
US7960210B2 (en) | Ultra-thin chip packaging | |
JP4237207B2 (ja) | 半導体装置の製造方法 | |
US20090261476A1 (en) | Semiconductor device and manufacturing method thereof | |
CN108206169B (zh) | 包含在裸芯边缘处的裸芯接合垫的半导体装置 | |
WO2009146587A1 (en) | Bongding method for through-silicon-via based 3d wafer stacking | |
TWI662677B (zh) | 堆疊式封裝結構及其製造方法 | |
US10529693B2 (en) | 3D stacked dies with disparate interconnect footprints | |
TWI544555B (zh) | 半導體封裝結構及其製造方法 | |
CN115394768A (zh) | 一种多层高带宽存储器及其制造方法 | |
CN109950223B (zh) | 包含双垫引线键合体互连的半导体装置 | |
CN220914204U (zh) | 半导体裸片封装及半导体装置封装 | |
CN114695323A (zh) | 半导体装置封装 | |
CN114823585A (zh) | 一种晶圆级多芯片堆叠封装结构及工艺 | |
KR20110038561A (ko) | 멀티칩 모듈들을 위한 개선된 전기적 연결들 | |
KR20110030088A (ko) | 반도체 패키지 및 그 제조방법 | |
JP2005123567A (ja) | 半導体装置およびその製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20200417 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20210212 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20210323 |
|
A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20210617 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20210916 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20211005 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20211015 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 6963424 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |