KR102094563B1 - 와이어 상호접속 구조를 형성하는 방법 - Google Patents

와이어 상호접속 구조를 형성하는 방법 Download PDF

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KR102094563B1
KR102094563B1 KR1020157000968A KR20157000968A KR102094563B1 KR 102094563 B1 KR102094563 B1 KR 102094563B1 KR 1020157000968 A KR1020157000968 A KR 1020157000968A KR 20157000968 A KR20157000968 A KR 20157000968A KR 102094563 B1 KR102094563 B1 KR 102094563B1
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wire
interconnect structure
forming
length
bond
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KR20150036074A (ko
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토마스 제이. 주니어 콜로시모
존 더블유. 브루너
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쿨리케 앤드 소파 인더스트리즈, 인코포레이티드
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    • H—ELECTRICITY
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    • H01L24/42—Wire connectors; Manufacturing methods related thereto
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    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
KR1020157000968A 2012-07-17 2013-07-01 와이어 상호접속 구조를 형성하는 방법 Active KR102094563B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US201261672449P 2012-07-17 2012-07-17
US61/672,449 2012-07-17
PCT/US2013/048860 WO2014014643A1 (en) 2012-07-17 2013-07-01 Methods of forming wire interconnect structures

Publications (2)

Publication Number Publication Date
KR20150036074A KR20150036074A (ko) 2015-04-07
KR102094563B1 true KR102094563B1 (ko) 2020-03-27

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US (3) US9502371B2 (enExample)
JP (1) JP6297553B2 (enExample)
KR (1) KR102094563B1 (enExample)
CN (1) CN104471693B (enExample)
TW (1) TWI531015B (enExample)
WO (1) WO2014014643A1 (enExample)

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WO2014014643A1 (en) * 2012-07-17 2014-01-23 Kulicke And Soffa Industries, Inc. Methods of forming wire interconnect structures
US9870946B2 (en) 2013-12-31 2018-01-16 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer level package structure and method of forming same
JP5686912B1 (ja) * 2014-02-20 2015-03-18 株式会社新川 バンプ形成方法、バンプ形成装置及び半導体装置の製造方法
US10256208B2 (en) 2014-10-03 2019-04-09 Intel Corporation Overlapping stacked die package with vertical columns
US11145620B2 (en) * 2019-03-05 2021-10-12 Asm Technology Singapore Pte Ltd Formation of bonding wire vertical interconnects
US11543362B2 (en) * 2019-05-02 2023-01-03 Asmpt Singapore Pte. Ltd. Method for measuring the heights of wire interconnections
JP2022033633A (ja) 2020-08-17 2022-03-02 キオクシア株式会社 半導体装置
KR20220045684A (ko) 2020-10-06 2022-04-13 에스케이하이닉스 주식회사 지그재그 모양의 와이어를 포함하는 반도체 패키지
JP7471692B2 (ja) * 2020-11-25 2024-04-22 株式会社新川 ワイヤ形成方法及び半導体装置の製造方法
US12057431B2 (en) * 2020-12-18 2024-08-06 Kulicke And Soffa Industries, Inc. Methods of forming wire interconnect structures and related wire bonding tools
JP7441558B2 (ja) 2021-09-16 2024-03-01 株式会社新川 ピンワイヤ形成方法、及びワイヤボンディング装置
JP7741745B2 (ja) 2022-02-15 2025-09-18 キオクシア株式会社 半導体装置およびその製造方法
TW202347637A (zh) 2022-02-15 2023-12-01 美商庫利克和索夫工業公司 確定用於產生與工件相關的複數個導線迴路的順序的方法

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US20170345787A1 (en) 2017-11-30
US10153247B2 (en) 2018-12-11
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US20170040280A1 (en) 2017-02-09
US20150132888A1 (en) 2015-05-14
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CN104471693A (zh) 2015-03-25
TW201405683A (zh) 2014-02-01
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US9502371B2 (en) 2016-11-22
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