KR101710862B1 - 인쇄된 전자장치를 위한 인쇄-적합 디자인 및 레이아웃 - Google Patents
인쇄된 전자장치를 위한 인쇄-적합 디자인 및 레이아웃 Download PDFInfo
- Publication number
- KR101710862B1 KR101710862B1 KR1020127002943A KR20127002943A KR101710862B1 KR 101710862 B1 KR101710862 B1 KR 101710862B1 KR 1020127002943 A KR1020127002943 A KR 1020127002943A KR 20127002943 A KR20127002943 A KR 20127002943A KR 101710862 B1 KR101710862 B1 KR 101710862B1
- Authority
- KR
- South Korea
- Prior art keywords
- structures
- width
- minimum
- length
- features
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0085—Apparatus for treatments of printed circuits with liquids not provided for in groups H05K3/02 - H05K3/46; conveyors and holding means therefor
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C14/00—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
- G11C14/0054—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down in which the volatile element is a SRAM cell
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
- G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistors, capacitors or inductors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
- H10K71/60—Forming conductive regions or layers, e.g. electrodes
- H10K71/611—Forming conductive regions or layers, e.g. electrodes using printing deposition, e.g. ink jet printing
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
- H10W20/44—Conductive materials thereof
- H10W20/4473—Conductive organic materials, e.g. conductive adhesives or conductive inks
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
- G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
- G11C17/18—Auxiliary circuits, e.g. for writing into memory
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09218—Conductive traces
- H05K2201/09245—Crossing layout
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/12—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using thick film techniques, e.g. printing techniques to apply the conductive material or similar techniques for applying conductive paste or ink patterns
- H05K3/1241—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using thick film techniques, e.g. printing techniques to apply the conductive material or similar techniques for applying conductive paste or ink patterns by ink-jet printing or drawing by dispensing
- H05K3/125—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using thick film techniques, e.g. printing techniques to apply the conductive material or similar techniques for applying conductive paste or ink patterns by ink-jet printing or drawing by dispensing by ink-jet printing
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Structure Of Printed Boards (AREA)
Applications Claiming Priority (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US23164309P | 2009-08-05 | 2009-08-05 | |
| US61/231,643 | 2009-08-05 | ||
| US25580409P | 2009-10-28 | 2009-10-28 | |
| US61/255,804 | 2009-10-28 | ||
| PCT/US2010/044598 WO2011017552A1 (en) | 2009-08-05 | 2010-08-05 | Print compatible designs and layout schemes for printed electronics |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20120052273A KR20120052273A (ko) | 2012-05-23 |
| KR101710862B1 true KR101710862B1 (ko) | 2017-02-28 |
Family
ID=43544671
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020127002943A Active KR101710862B1 (ko) | 2009-08-05 | 2010-08-05 | 인쇄된 전자장치를 위한 인쇄-적합 디자인 및 레이아웃 |
Country Status (6)
| Country | Link |
|---|---|
| US (2) | US8383952B2 (https=) |
| JP (1) | JP2013501383A (https=) |
| KR (1) | KR101710862B1 (https=) |
| CN (1) | CN102474254A (https=) |
| TW (1) | TWI573496B (https=) |
| WO (1) | WO2011017552A1 (https=) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| AT12741U1 (de) * | 2011-03-10 | 2012-10-15 | Forster Verkehrs Und Werbetechnik Gmbh | Anordnung mit elektrischen/elektronischen bauteilen |
| WO2015075310A1 (en) * | 2013-11-19 | 2015-05-28 | Teknologian Tutkimuskeskus Vtt Oy | A method for the fabrication and use of electronic circuits and an electronics circuit structure |
| GB2543528B (en) | 2015-10-20 | 2020-01-15 | Advanced Risc Mach Ltd | Memory circuit |
| WO2019036304A1 (en) * | 2017-08-18 | 2019-02-21 | Thin Film Electronics Asa | SPRAY-COATED DETECTION LINES, SAFETY AND / OR IDENTIFICATION LABELS AND DEVICES COMPRISING THE SAME, AND METHODS OF MAKING |
| US20210189165A1 (en) * | 2017-10-19 | 2021-06-24 | Hewlett-Packard Development Company, L.P. | Printable ammonium-based chalcogenometalate fluids |
| US10306749B1 (en) * | 2018-02-19 | 2019-05-28 | Dell Products L.P. | System and method of utilizing serpentine regions |
| CN113486621B (zh) * | 2021-06-28 | 2024-03-01 | 深圳市华星光电半导体显示技术有限公司 | 像素电路的设计方法、装置、控制器及存储介质 |
Family Cites Families (46)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5811750B2 (ja) * | 1979-06-04 | 1983-03-04 | 株式会社日立製作所 | 高耐圧抵抗素子 |
| JPS607147A (ja) * | 1983-06-24 | 1985-01-14 | Mitsubishi Electric Corp | 半導体装置 |
| US4685203A (en) * | 1983-09-13 | 1987-08-11 | Mitsubishi Denki Kabushiki Kaisha | Hybrid integrated circuit substrate and method of manufacturing the same |
| JPH02163960A (ja) * | 1988-12-16 | 1990-06-25 | Toshiba Corp | 半導体装置 |
| JPH0750710B2 (ja) * | 1990-06-06 | 1995-05-31 | 富士ゼロックス株式会社 | 多層配線構造 |
| US5723908A (en) * | 1993-03-11 | 1998-03-03 | Kabushiki Kaisha Toshiba | Multilayer wiring structure |
| US5764488A (en) * | 1996-06-11 | 1998-06-09 | Ast Research, Inc. | Printed circuit board having a dual pattern footprint for receiving one of two component packages |
| US5805428A (en) * | 1996-12-20 | 1998-09-08 | Compaq Computer Corporation | Transistor/resistor printed circuit board layout |
| EP0909117B1 (en) * | 1997-10-08 | 2006-01-04 | Delphi Technologies, Inc. | Method of making thick film circuits |
| JP3070678B2 (ja) * | 1998-03-24 | 2000-07-31 | 日本電気株式会社 | 図形レイアウト変更システム及び図形レイアウト変更方法 |
| JP4228418B2 (ja) * | 1998-07-30 | 2009-02-25 | 沖電気工業株式会社 | 半導体装置 |
| US6691297B1 (en) * | 1999-03-04 | 2004-02-10 | Matsushita Electric Industrial Co., Ltd. | Method for planning layout for LSI pattern, method for forming LSI pattern and method for generating mask data for LSI |
| US6238824B1 (en) * | 1999-08-31 | 2001-05-29 | Micron Technology, Inc. | Method for designing and making photolithographic reticle, reticle, and photolithographic process |
| TW438198U (en) * | 1999-10-14 | 2001-05-28 | Via Tech Inc | Wiring structure of a printed circuit board |
| EP1113368A3 (en) * | 1999-12-27 | 2001-09-26 | Matsushita Electric Industrial Co., Ltd. | Semiconductor integrated circuit with cache |
| US6792590B1 (en) * | 2000-09-29 | 2004-09-14 | Numerical Technologies, Inc. | Dissection of edges with projection points in a fabrication layout for correcting proximity effects |
| DE10059498A1 (de) * | 2000-11-30 | 2002-06-13 | Infineon Technologies Ag | Substrat mit einer halbleitenden Schicht, elektronisches Bauelement mit diesem Substrat, elektronische Schaltung mit mindestens einem solchen elektronischen Bauelement, druckbare Zusammensetzung sowie Verfahren zur Herstellung eines Substrats |
| US6858928B1 (en) * | 2000-12-07 | 2005-02-22 | Cadence Design Systems, Inc. | Multi-directional wiring on a single metal layer |
| US6664639B2 (en) * | 2000-12-22 | 2003-12-16 | Matrix Semiconductor, Inc. | Contact and via structure and method of fabrication |
| US6492736B1 (en) * | 2001-03-14 | 2002-12-10 | Lsi Logic Corporation | Power mesh bridge |
| JP2002312414A (ja) * | 2001-04-13 | 2002-10-25 | Toshiba Corp | 半導体集積回路装置のレイアウト設計システム、配線設計方法、配線設計プログラム及び半導体集積回路装置の製造方法 |
| TW522764B (en) * | 2001-08-28 | 2003-03-01 | Via Tech Inc | Power layout structure on host bridge chip substrate and motherboard |
| US6825509B1 (en) * | 2001-11-26 | 2004-11-30 | Corrent Corporation | Power distribution system, method, and layout for an electronic device |
| US7739624B2 (en) * | 2002-07-29 | 2010-06-15 | Synopsys, Inc. | Methods and apparatuses to generate a shielding mesh for integrated circuit devices |
| GB0225202D0 (en) * | 2002-10-30 | 2002-12-11 | Hewlett Packard Co | Electronic components |
| US6874133B2 (en) * | 2002-12-04 | 2005-03-29 | Cadence Design Systems, Inc. | Integrated circuit design layout compaction method |
| JP2004335887A (ja) * | 2003-05-09 | 2004-11-25 | Canon Inc | プリント配線基板及び該基板を用いた装置 |
| US7124390B2 (en) * | 2003-07-25 | 2006-10-17 | Mentor Graphics Corporation | Generating a split power plane of a multi-layer printed circuit board |
| TW591985B (en) * | 2003-10-15 | 2004-06-11 | Benq Corp | PCB having a circuit layout for preventing the PCB from bending when heated |
| WO2005111874A2 (en) * | 2004-05-07 | 2005-11-24 | Mentor Graphics Corporation | Integrated circuit layout design methodology with process variation bands |
| US7161823B2 (en) * | 2004-06-03 | 2007-01-09 | Samsung Electronics Co., Ltd. | Semiconductor memory device and method of arranging signal and power lines thereof |
| TWI259043B (en) * | 2004-11-19 | 2006-07-21 | Realtek Semiconductor Corp | Structure of circuit layout and method thereof |
| WO2006076606A2 (en) * | 2005-01-14 | 2006-07-20 | Cabot Corporation | Optimized multi-layer printing of electronics and displays |
| JP2006253498A (ja) * | 2005-03-11 | 2006-09-21 | Matsushita Electric Ind Co Ltd | 半導体集積回路装置 |
| US7446352B2 (en) * | 2006-03-09 | 2008-11-04 | Tela Innovations, Inc. | Dynamic array architecture |
| JP5050413B2 (ja) * | 2006-06-09 | 2012-10-17 | 富士通株式会社 | 設計支援プログラム、該プログラムを記録した記録媒体、設計支援方法、および設計支援装置 |
| US7624500B2 (en) * | 2006-08-16 | 2009-12-01 | Lexmark International, Inc. | Printing of multi-layer circuits |
| US7615706B2 (en) * | 2006-08-21 | 2009-11-10 | Tpo Displays Corp. | Layout of a printed circuit board |
| US20080072204A1 (en) * | 2006-09-19 | 2008-03-20 | Inventec Corporation | Layout design of multilayer printed circuit board |
| US7493436B2 (en) * | 2006-10-26 | 2009-02-17 | International Business Machines Corporation | Interrupt handling using simultaneous multi-threading |
| WO2008085806A1 (en) * | 2007-01-03 | 2008-07-17 | Nanogram Corporation | Nanoparticle inks based on silicon/germanium, doped particles, printing and processes for semiconductor applications |
| JP5521270B2 (ja) * | 2007-02-21 | 2014-06-11 | 凸版印刷株式会社 | 薄膜トランジスタアレイ、薄膜トランジスタアレイの製造方法、および薄膜トランジスタアレイを用いたアクティブマトリクス型ディスプレイ |
| TWI363210B (en) * | 2007-04-04 | 2012-05-01 | Au Optronics Corp | Layout structure for chip coupling |
| US7979983B2 (en) * | 2007-04-04 | 2011-07-19 | Cisco Technology, Inc. | Connection an integrated circuit on a surface layer of a printed circuit board |
| TWI370464B (en) * | 2007-04-19 | 2012-08-11 | Ind Tech Res Inst | Resistance layout structure and manufacture method thereof |
| US8453094B2 (en) * | 2008-01-31 | 2013-05-28 | Tela Innovations, Inc. | Enforcement of semiconductor structure regularity for localized transistors and interconnect |
-
2010
- 2010-08-05 KR KR1020127002943A patent/KR101710862B1/ko active Active
- 2010-08-05 WO PCT/US2010/044598 patent/WO2011017552A1/en not_active Ceased
- 2010-08-05 JP JP2012523958A patent/JP2013501383A/ja active Pending
- 2010-08-05 TW TW099126062A patent/TWI573496B/zh not_active IP Right Cessation
- 2010-08-05 US US12/851,014 patent/US8383952B2/en active Active
- 2010-08-05 CN CN2010800345952A patent/CN102474254A/zh active Pending
-
2013
- 2013-02-01 US US13/757,649 patent/US9155202B2/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| TWI573496B (zh) | 2017-03-01 |
| US9155202B2 (en) | 2015-10-06 |
| WO2011017552A1 (en) | 2011-02-10 |
| CN102474254A (zh) | 2012-05-23 |
| JP2013501383A (ja) | 2013-01-10 |
| US20110186333A1 (en) | 2011-08-04 |
| US20130146334A1 (en) | 2013-06-13 |
| US8383952B2 (en) | 2013-02-26 |
| KR20120052273A (ko) | 2012-05-23 |
| TW201125445A (en) | 2011-07-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR101710862B1 (ko) | 인쇄된 전자장치를 위한 인쇄-적합 디자인 및 레이아웃 | |
| KR101526021B1 (ko) | 패턴화된 도체, 반도체 및 유전 물질을 위한 인쇄 공정 | |
| JP5692924B2 (ja) | プリント不揮発性メモリ | |
| US20140299883A1 (en) | Printed, self-aligned, top gate thin film transistor | |
| US8748242B2 (en) | Electronic circuit structure and method for forming same | |
| JP2010541255A (ja) | 輪郭設計された薄膜デバイス及び構造体 | |
| JP2011511441A (ja) | シリコン薄膜トランジスタ、並びにその製造システム及び方法 | |
| CN102770948A (zh) | 制造包括凹型的晶体管的方法 | |
| TW200845398A (en) | Semiconductor device and manufacture method thereof | |
| TW201921498A (zh) | 選擇性氧化鋁蝕刻的使用 | |
| JP2017139276A (ja) | 半導体装置 | |
| KR20140082681A (ko) | 반도체 디바이스 제조를 위한 프로세스 | |
| WO2009075739A2 (en) | Forming thin film transistors using ablative films | |
| US20090278134A1 (en) | Semiconductor device and method of manufacturing the semiconductor device | |
| US9123815B1 (en) | VTFTs including offset electrodes | |
| TW201320346A (zh) | 具有減小寄生電容之垂直電晶體 | |
| CN1951162B (zh) | 元件配置基板及其制备方法 | |
| US7537883B2 (en) | Method of manufacturing nano size-gap electrode device | |
| JP2005038895A (ja) | トランジスタの製造方法、電気光学装置、電子機器 | |
| JP2005209696A (ja) | 半導体装置の製造方法 | |
| CN108321122B (zh) | Cmos薄膜晶体管及其制备方法和显示装置 | |
| US9142647B1 (en) | VTFT formation using selective area deposition | |
| CN113078166B (zh) | 半导体装置 | |
| CN100562978C (zh) | 印刷式自对准上闸极薄膜晶体管 | |
| JP4617642B2 (ja) | 配線基板の製造方法、及び電気光学装置の製造方法 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PA0105 | International application |
St.27 status event code: A-0-1-A10-A15-nap-PA0105 |
|
| PG1501 | Laying open of application |
St.27 status event code: A-1-1-Q10-Q12-nap-PG1501 |
|
| A201 | Request for examination | ||
| E13-X000 | Pre-grant limitation requested |
St.27 status event code: A-2-3-E10-E13-lim-X000 |
|
| P11-X000 | Amendment of application requested |
St.27 status event code: A-2-2-P10-P11-nap-X000 |
|
| P13-X000 | Application amended |
St.27 status event code: A-2-2-P10-P13-nap-X000 |
|
| PA0201 | Request for examination |
St.27 status event code: A-1-2-D10-D11-exm-PA0201 |
|
| N231 | Notification of change of applicant | ||
| PN2301 | Change of applicant |
St.27 status event code: A-3-3-R10-R13-asn-PN2301 St.27 status event code: A-3-3-R10-R11-asn-PN2301 |
|
| P22-X000 | Classification modified |
St.27 status event code: A-2-2-P10-P22-nap-X000 |
|
| E902 | Notification of reason for refusal | ||
| PE0902 | Notice of grounds for rejection |
St.27 status event code: A-1-2-D10-D21-exm-PE0902 |
|
| P11-X000 | Amendment of application requested |
St.27 status event code: A-2-2-P10-P11-nap-X000 |
|
| P13-X000 | Application amended |
St.27 status event code: A-2-2-P10-P13-nap-X000 |
|
| P11-X000 | Amendment of application requested |
St.27 status event code: A-2-2-P10-P11-nap-X000 |
|
| P13-X000 | Application amended |
St.27 status event code: A-2-2-P10-P13-nap-X000 |
|
| E701 | Decision to grant or registration of patent right | ||
| PE0701 | Decision of registration |
St.27 status event code: A-1-2-D10-D22-exm-PE0701 |
|
| GRNT | Written decision to grant | ||
| PR0701 | Registration of establishment |
St.27 status event code: A-2-4-F10-F11-exm-PR0701 |
|
| PR1002 | Payment of registration fee |
St.27 status event code: A-2-2-U10-U12-oth-PR1002 Fee payment year number: 1 |
|
| PG1601 | Publication of registration |
St.27 status event code: A-4-4-Q10-Q13-nap-PG1601 |
|
| FPAY | Annual fee payment |
Payment date: 20191223 Year of fee payment: 4 |
|
| PR1001 | Payment of annual fee |
St.27 status event code: A-4-4-U10-U11-oth-PR1001 Fee payment year number: 4 |
|
| FPAY | Annual fee payment |
Payment date: 20210204 Year of fee payment: 5 |
|
| PR1001 | Payment of annual fee |
St.27 status event code: A-4-4-U10-U11-oth-PR1001 Fee payment year number: 5 |
|
| FPAY | Annual fee payment |
Payment date: 20220207 Year of fee payment: 6 |
|
| PR1001 | Payment of annual fee |
St.27 status event code: A-4-4-U10-U11-oth-PR1001 Fee payment year number: 6 |
|
| P22-X000 | Classification modified |
St.27 status event code: A-4-4-P10-P22-nap-X000 |
|
| P22-X000 | Classification modified |
St.27 status event code: A-4-4-P10-P22-nap-X000 |
|
| PR1001 | Payment of annual fee |
St.27 status event code: A-4-4-U10-U11-oth-PR1001 Fee payment year number: 7 |
|
| PR1001 | Payment of annual fee |
St.27 status event code: A-4-4-U10-U11-oth-PR1001 Fee payment year number: 8 |
|
| PR1001 | Payment of annual fee |
St.27 status event code: A-4-4-U10-U11-oth-PR1001 Fee payment year number: 9 |
|
| P22-X000 | Classification modified |
St.27 status event code: A-4-4-P10-P22-nap-X000 |
|
| PR1001 | Payment of annual fee |
St.27 status event code: A-4-4-U10-U11-oth-PR1001 Fee payment year number: 10 |
|
| U11 | Full renewal or maintenance fee paid |
Free format text: ST27 STATUS EVENT CODE: A-4-4-U10-U11-OTH-PR1001 (AS PROVIDED BY THE NATIONAL OFFICE) Year of fee payment: 10 |