JP2010541255A - 輪郭設計された薄膜デバイス及び構造体 - Google Patents
輪郭設計された薄膜デバイス及び構造体 Download PDFInfo
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- JP2010541255A JP2010541255A JP2010527256A JP2010527256A JP2010541255A JP 2010541255 A JP2010541255 A JP 2010541255A JP 2010527256 A JP2010527256 A JP 2010527256A JP 2010527256 A JP2010527256 A JP 2010527256A JP 2010541255 A JP2010541255 A JP 2010541255A
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Abstract
【選択図】図4D
Description
[0001]本出願は、2007年10月1日出願の米国特許仮出願第60/997,335号明細書(代理人整理番号IDR1573)及び2008年10月1日出願で係属中の米国特許出願第12/243,880号明細書(代理人整理番号IDR1574)の利益を主張する。
[0002]本発明は、印刷された、滑らかな及び/又はドーム形の半導体薄膜フィーチャを備える薄膜キャパシタ、ダイオード(例えば、ショットキーダイオード)、薄膜トランジスタ並びに浮遊ゲートメモリセルなどのデバイスに関する。本出願は、新規のインク組成物、及び低コスト印刷技術の新規の使用法を用いて製造できる構造体を開示する。本発明の諸実施例は、印刷(例えば、インクジェット印刷、グラビア印刷、オフセットリソグラフィ、スクリーン印刷、フレキソグラフィ又はフレキソ印刷、マイクロスポッティング、ペンコーティング、ステンシル、スタンピング、シリンジディスペンス、ポンプディスペンス、スプレーコーティング、スリットコーティング、押出しコーティング、メニスカスコーティングなど)用のインク組成物を用いて形成されるトランジスタ、ダイオード、キャパシタ及び他の構造体に関連する。
[0003]従来のリソグラフィでパターニングされたデバイスでは、ゲート電極が活性フィーチャ(例えば、トランジスタチャネル)又は他の構造体の鋭い/急峻な縁部の上を横切る交差位置において、漏洩電流による電荷の損失が起きることがある。図1は、従来のリソグラフィで画定されたトランジスタの、基板101の上に形成されたチャネル層102、及びその上に形成された誘電体層103を示す。誘電体層103は、酸化で形成されようと堆積で形成されようと、リソグラフィで形成されたチャネル層102の不均一な被覆をチャネル層102の縁部(すなわち、チャネル層102の上部縁部、及びチャネル層102が基板101に接触するところ)に有することがある。誘電体層103の上にゲート層104が堆積される。この誘電体層は、チャネル層102の縁部においてかなり薄くなることがあり、その結果、誘電体層103の薄い部分でチャネル層102とゲート層104の間に漏洩電流が生じる。
[0007]本発明は、印刷された1つ又は複数の半導体(例えば、シリコン)、絶縁体(例えば、二酸化シリコン)及び導電体(例えば、金属)のフィーチャを含む、比較的高性能のデバイスが含まれるデバイス、及びこのようなフィーチャを製造する方法に関する。より具体的には、本発明の実施形態は、このようなデバイスを、印刷(例えば、インクジェット印刷)されたシリコン、絶縁体及び/又は金属のフィーチャ及び構造体を使用して製作するための改善された方法に関連する。本明細書に記載したいくつかの方法により、印刷される電子回路及びデバイス内の半導体、絶縁体及び導電体のフィーチャ(例えば、線、長方形、T字形、L字形、H字形、ダンベル形、タブ、円形、正方形、接触孔及び/又は接触溝、これらの組合せなど)の臨界寸法及び非臨界寸法のより精密な制御が可能になる。
[0031]次に、添付の図面に例が示されている本発明のいくつかの実施形態を詳細に参照する。本発明を好ましい諸実施形態と併せて説明するが、これらは本発明をこれらの実施形態に限定するものではないことを理解されたい。そうではなくて、本発明は、添付の特許請求の範囲によって定義される本発明の趣旨及び範囲内に含まれる代替形態、改変形態及び等価物を包含するものである。さらに、以下の開示では、本発明を完全に理解できるように多くの具体的詳細を示す。しかしながら、これらの具体的詳細なしで本発明を実施できることは、当業者には明らかであろう。他の事例では、本発明の態様を不必要に不明瞭にしないように、よく知られた方法、手順、構成要素及び回路については詳細に説明していない。
[0088]本発明の一態様は、トランジスタ、及びトランジスタ構造体を製作する方法に関し、その諸ステップが図4A〜4Dに示されている。トランジスタゲート層は、トランジスタのソース、チャネル及びドレインの上にあってもよい(いわゆる「トップゲート」トランジスタであるが、本明細書で開示した方法は、ボトムゲートトランジスタなど他の構造上の構成を有するデバイスを形成するのにも同様に有効である)。ソース/ドレイン端子層は、印刷されたドーム形のドープ半導体薄膜フィーチャを含む。トランジスタゲート層は、従来の半導体材料、従来の導電体材料、又は2つ以上の従来の半導体及び/又は導電体材料(例えば、[0033]〜[0076]及び[0080]〜[0086]パラグラフに記載したような、遷移金属シリサイドで高濃度にドープされたシリコン)の積層体を含むことができる。トランジスタはさらに、ソース/ドレイン端子層のソース及びドレイン構造体と物理的及び/又は電気的に接触する(及び任意選択で、ゲート層と物理的及び/又は電気的に接触する)接点構造体及び/又は、1つ又は複数のメタライゼーション構造体を含むこともできる。
[0097]本発明の別の態様は、薄膜キャパシタ、及び薄膜キャパシタを製作する方法に関し(例えば、金属酸化物半導体[MOS]キャパシタ、又は金属−絶縁物−金属[MIM]キャパシタ)、その諸ステップが図5A〜5Cに示されている。この薄膜キャパシタは、滑らかな及び/又はドーム形の輪郭を有する1つ又は複数の層を有することができ、これにより、同様にサイズ設定され、従来方法(例えば、リソグラフィ)で画定されたキャパシタ構造体におけるよりも大きいキャパシタ層間の界面面積が得られる。なぜなら、滑らかな又はドーム形の下部キャパシタ層の上に形成された導電体層、半導体層又は誘電体層は、従来の半導体又は導電体の上面だけではなく、滑らかな及び/又はドーム形のフィーチャを共形に被覆することもできるからである。界面面積の増大は、キャパシタ構造体の臨界寸法を増大させないで静電容量の増大を実現する。滑らかな及び/又はドーム形の輪郭により、上で論じた付加的な利点が得られる。
[0107]本発明のさらに別の態様は、不揮発性メモリセル、及び不揮発性メモリセルの製作方法に関し、その諸ステップが図6A〜6Fに図で示されている。例示的な不揮発性メモリセルが図6C及び図6Fに示されている。例示的な不揮発性メモリセルは、第1及び第2の印刷された構造体と、チャネル層並びにソース端子及びドレイン端子を含む第1の印刷された構造体620、並びに浮遊ゲートを含む第2の印刷された構造体640;第1の構造体620の少なくとも一部の上のトンネル誘電体層630;第2の構造体640の少なくとも一部の上のゲート誘電体層650;ゲート誘電体層650の少なくとも一部の上の制御ゲート660;制御ゲート660並びにソース端子及びドレイン端子と電気的に接触している金属相互接続層670とを含む。一実施形態では、金属相互接続層は、図6Fに示された例示的な不揮発性メモリセルにおけるように、均一なシリサイド層671を含むことができる。例示的な不揮発性メモリセルに関するさらなる詳細は、図6C及び図6Fに示された不揮発性メモリセルを形成する例示的な方法についての以下の説明で示す。
[0138]本発明の別の態様は、薄膜ダイオード、及び薄膜ダイオードを製作する方法に関し、その諸ステップが図7A〜7Cに示されている。好ましい実施形態には、ショットキーダイオード及びその製造方法が含まれる。しかしながら、本明細書で開示する方法では、他のタイプのダイオード(例えば、画像センサ、無線デバイスなどに使用するためのp−nダイオード、ツェナーダイオードなど)を形成することができる。薄膜ダイオードは、1つ又は複数の滑らかな及び/又はドーム形の輪郭を有する1つ又は複数の層を有することができ、これにより、その上に形成される層が、従来方法で(例えば、リソグラフィで)画定されたダイオード構造体よりも均質で共形に堆積され又は成長することが可能になり、かつ上記で論じた他の利点が得られる。
[0150]本発明の諸実施形態は、電気的活性デバイス(例えば、キャパシタ、トランジスタ、ダイオード、浮遊ゲートメモリセルなど)に関連し、これらは、誘電体、導電体及び/又は半導体の、滑らかな及び/又はドーム形の輪郭を有する層及び/又は構造体を有する。本発明はまた、このようなデバイスを、半導体、金属、及び/又は誘電体の前駆体を含むインク組成物を堆積又は印刷(例えば、インクジェット印刷)して電気的活性フィーチャ及び構造体を形成することによって形成する方法も含む。これらの実施形態では、滑らかな及び/又はドーム形の断面輪郭を有する構造体を実現し、この断面輪郭は、急激な段差に遭遇しない滑らかな移行部を可能にし、それによって堆積時のフィーチャの不連続を防止し、続いて堆積される構造体のより完全な段差被覆性を得ることができる。加えて、滑らかな及び/又はドーム形の断面輪郭は、構造体の上の、熱酸化による酸化物層の均一な成長も、構造体の表面全体の、等方性エッチングによるほぼ均一なエッチング速度も可能にする。本明細書で開示した方法により得られる酸化物層は、均一な厚さと、下の電気的活性フィーチャのほぼ完全な被覆とを有することができる。後者の特性は、単純な等方性エッチングによって電気的活性構造体(例えば、ゲート又はチャネル層)の臨界寸法を低減する効率的な方法を可能にする。開示した方法は、下の電気的活性フィーチャの臨界寸法及び非臨界寸法の維持、低減、及び/又は均一性改善を可能にする。
Claims (35)
- a)表面を有する基板と、
b)前記基板表面上に滑らかな、ドーム形の輪郭を有する第1の電気的活性層と、
c)前記第1の電気的活性層の上に共形の第2の電気的活性層とを備える電気的活性デバイス。 - 前記第1の電気的活性層が半導体層を備える、請求項1に記載の電気的活性デバイス。
- 前記半導体層が水素化シリコン及び/又は水素化ゲルマニウムを含む、請求項2に記載の電気的活性デバイス。
- 前記第1の電気的活性層が金属層を備える、請求項1に記載の電気的活性デバイス。
- 前記第1の電気的活性層の上に誘電体層をさらに備える、請求項1に記載の電気的活性デバイス。
- 前記誘電体層が、熱によって成長させたほぼ均一な厚さを有する酸化物を含む、請求項5に記載の電気的活性デバイス。
- 前記第2の電気的活性層が滑らかな及び/又はドーム形の輪郭を有する、請求項1に記載の電気的活性デバイス。
- 前記第2の電気的活性層が第2の半導体層を備える、請求項7に記載の電気的活性デバイス。
- 前記第2の半導体層が水素化シリコン及び/又は水素化ゲルマニウムを含む、請求項8に記載の電気的活性デバイス。
- 前記第2の電気的活性層が金属含有層を備える、請求項1に記載の電気的活性デバイス。
- 前記第1及び第2の電気的活性層の少なくとも一方が、(i)シリコン及び(ii)該シリコン上に形成された金属シリサイド層を備える、請求項10に記載の電気的活性デバイス。
- 前記デバイスがトランジスタであり、前記第1の電気的活性層が、チャネル領域を備える半導体層である、請求項1に記載の電気的活性デバイス。
- 前記デバイスがキャパシタであり、前記第1の電気的活性層が第1の金属層を備え、前記キャパシタがさらに誘電体層を(i)前記第1の電気的活性層と(ii)前記第2の電気的活性層との間、あるいは前記基板が導電性表面材料を有する場合には前記基板との間に備える、請求項1に記載の電気的活性デバイス。
- 前記第2の電気的活性層が、半導体層及び/又は第2の金属層を備える、請求項13に記載の電気的活性デバイス。
- 前記誘電体層が、ほぼ均一な厚さを有する熱酸化物を含み、前記第1の電気的活性層と前記第2の電気的活性層の間にある、請求項13に記載の電気的活性デバイス。
- 前記デバイスがダイオードであり、前記第1の電気的活性層が第1の半導体層を備え、前記第2の電気的活性層が金属層、又は前記第1の半導体層と異なる特性を有する第2の半導体層を備える、請求項1に記載の電気的活性デバイス。
- 前記第1の半導体層が水素化シリコン及び/又は水素化ゲルマニウムを含む、請求項16に記載の電気的活性デバイス。
- 前記第2の電気的活性層が金属層を備え、前記金属層が、Zr、Hf、V、Nb、Ta、Cr、Mo、W、Mn、Re、Fe、Ru、Os、Co、Rh、Ir、Ni、Pd、Pt、Cu、Ag、Au、Zn、Cd、又はこれらの組合せからなる群から選択される、請求項16に記載の電気的活性デバイス。
- 前記第2の電気的活性層が前記第1の電気的活性層と直接物理的に接触している、請求項16に記載の電気的活性デバイス。
- 前記デバイスが浮遊ゲートメモリセルであり、前記第1の電気的活性層が、チャネル領域と、前記チャネル領域に隣接するソース端子及びドレイン端子とを備える第1の半導体層であり、前記第2の電気的活性層が第2の半導体層を備え、前記デバイスがさらに、前記第1の電気的活性層と前記第2の電気的活性層の間にトンネル誘電体層を備える、請求項1に記載の電気的活性デバイス。
- a)1つ又は複数の第1の半導体前駆体及び/又は金属前駆体を含む第1のインク組成物を基板上に印刷するステップであって、前記第1のインクが1つ又は複数の所定の特性を有するステップと、
b)前記第1の前駆体(1つ又は複数)を硬化させて滑らかな、ドーム形の輪郭を有する第1の電気的活性層を形成するステップと、
c)前記第1の電気的活性層の上に共形の第2の電気的活性層を形成するステップとを含む、電気的活性デバイスを製作する方法。 - 前記1つ又は複数の第1の前駆体が、前記第1のインク組成物の重量で1から40%の量で存在する、請求項21に記載の方法。
- 前記1つ又は複数の第1の前駆体が、(ポリ)シラン、(ポリ)ゲルマン、(ポリ)ゲルマシラン及び、シリコン及び/又はゲルマニウムのナノ粒子からなる群から選択される、請求項22に記載の方法。
- 前記(ポリ)シラン、(ポリ)ゲルマン、及び(ポリ)ゲルマシランが、(i)少なくとも15個のシリコン及び/又はゲルマニウムの原子、及び(ii)水素を有する化学種で基本的に構成される、請求項23に記載の方法。
- 前記1つ又は複数の第1の前駆体が、Zr、Hf、V、Nb、Ta、Cr、Mo、W、Mn、Re、Fe、Ru、Os、Co、Rh、Ir、Ni、Pd、Pt、Cu、Ag、Au、Zn、Cd、又はこれらの組合せからなる群から選択された金属の化合物、複合体、クラスタ及び/又はナノ粒子を含む、請求項22に記載の方法。
- 前記インク組成物がさらに、前記1つ又は複数の第1の前駆体が溶解する溶媒を含み、前記1つ又は複数の所定の特性が2から100cPの粘度を含む、請求項22に記載の方法。
- 印刷するステップが、前記インク組成物を前記基板上に所定のパターンでインクジェット印刷、グラビア印刷、オフセットリソグラフィ、スクリーン印刷、フレキソグラフィ又はフレキソ印刷、マイクロスポッティング、ペンコーティング、ステンシル、スタンピング、シリンジディスペンス、ポンプディスペンス、スプレーコーティング、スリットコーティング、押出しコーティング、又はメニスカスコーティングするステップを含む、請求項22に記載の方法。
- 前記インク組成物を印刷するステップが、
a)1つ又は複数の第1の前駆体を析出させて、ピンニングされた機能パターンを形成するステップと、
b)前記1つ又は複数の第1の前駆体を硬化させる前に前記溶媒をほぼ蒸発させるステップとを含む、請求項26に記載の方法。 - 前記1つ又は複数の第1の前駆体を硬化させることで、前記1つ又は複数の第1の前駆体を、前記ピンニングされた機能パターンによって画定された第1の電気的活性層を形成する第1の電気的活性材料に変換する、請求項28に記載の方法。
- 前記溶媒が、3つまでのC1〜C4アルキル基で置換されたC5〜C10アルカン又は、C5〜C10モノシクロアルカン又は若しくはビシクロアルカンを含む、請求項26に記載の方法。
- 前記1つ又は複数の第1の前駆体を析出させるステップが、前記インクを紫外線放射で照射するステップを含む、請求項28に記載の方法。
- 前記第1の電気的活性層を熱によって酸化して熱酸化物層を形成するステップをさらに含む、請求項21に記載の方法。
- 前記熱酸化物層を除去し、それによって前記第1の電気的活性層の幅を縮小するステップをさらに含む、請求項32に記載の方法。
- 前記第2の電気的活性層が滑らかな、ドーム形の輪郭を有する、請求項21に記載の方法。
- 前記第1の電気的活性層を等方的にエッチングしてその幅を縮小するステップをさらに含む、請求項21に記載の方法。
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CA2701412A1 (en) | 2009-04-09 |
KR20100081983A (ko) | 2010-07-15 |
KR20160040319A (ko) | 2016-04-12 |
SG2012070850A (en) | 2014-04-28 |
CA2701412C (en) | 2017-06-20 |
US20130189823A1 (en) | 2013-07-25 |
US20090085095A1 (en) | 2009-04-02 |
US8426905B2 (en) | 2013-04-23 |
CN101821839A (zh) | 2010-09-01 |
EP2195829A4 (en) | 2014-01-15 |
KR101694684B1 (ko) | 2017-01-10 |
WO2009046148A1 (en) | 2009-04-09 |
EP2195829A1 (en) | 2010-06-16 |
US8822301B2 (en) | 2014-09-02 |
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