WO2015075310A1 - A method for the fabrication and use of electronic circuits and an electronics circuit structure - Google Patents

A method for the fabrication and use of electronic circuits and an electronics circuit structure Download PDF

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Publication number
WO2015075310A1
WO2015075310A1 PCT/FI2014/050879 FI2014050879W WO2015075310A1 WO 2015075310 A1 WO2015075310 A1 WO 2015075310A1 FI 2014050879 W FI2014050879 W FI 2014050879W WO 2015075310 A1 WO2015075310 A1 WO 2015075310A1
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Prior art keywords
substrate
semiconductor
layer
effect transistor
field effect
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PCT/FI2014/050879
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French (fr)
Inventor
Ari Alastalo
Jaakko LEPPÄNIEMI
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Teknologian Tutkimuskeskus Vtt Oy
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Publication of WO2015075310A1 publication Critical patent/WO2015075310A1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1292—Multistep manufacturing methods using liquid deposition, e.g. printing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Definitions

  • the present invention relates to the manufacture and use of semiconductor components and circuits on a substrate.
  • the invention relates to a method of forming thin-film material stacks to form arrays of semiconductor components, like transistors, and the interconnecting circuitry between them.
  • the field-effect transistor operates by the effects of a controllable electric field in a single-type (N-type or P-type) semiconductor material that forms the channel.
  • the flow of charge carriers in the channel between a source and a drain connection is dependent on the voltage applied on a gate electrode that is separated from the channel by a dielectric layer.
  • a FET has in principle a simple and layered structure.
  • a thin-film FET transistor is a special kind of field-effect transistor made by depositing thin films of active semiconductor layers as well as dielectric layers and metallic contacts over a supporting (but non-conducting) substrate.
  • a common substrate is glass, and here the TFT differs from a conventional metal-oxide- semiconductor (MOS) FET transistor, where the substrate typically is a silicon wafer being of opposite semiconductor type than that of the unipolar channel.
  • MOS metal-oxide- semiconductor
  • TFT thin film transistor
  • LCD liquid crystal display
  • AMOLED active-matrix organic light-emitting diode
  • TFTs are used to control a single pixel of the display, which has benefits for the stability and resolution of the display.
  • the semiconductor layer in TFTs is fabricated either from polycrystalline silicon (poly- Si) or amorphous silicon (a-Si).
  • New and versatile oxide semiconductor materials have properties beyond conventional a-Si or poly-Si materials, such as a high band-gap allowing transparency in the visible range, ionic nature allowing high charge-carrier mobility even in amorphous phase, and a low charge carrier concentration at conduction band.
  • This enables the use of TFT transistors in various new and improved applications.
  • a ZnO-based semiconductor film may be manufactured at low temperature processes enabling the fabrication of TFTs on low cost flexible substrates.
  • Ga- and In-doped ZnO (GalnZnO) high-mobility semiconductors gallium indium zinc oxide, GIZO
  • GIZO gallium indium zinc oxide
  • TFT indium-doped tin oxide
  • the oxide layers of thin film components are fabricated by vacuum techniques such as sputtering, pulsed laser deposition or atomic layer deposition, which can provide thin material layers of high quality.
  • the quality of the semiconducting layer, the insulating layer and their interface where the channel is located are of utmost importance for realizing high-performance devices.
  • a typical process is to form a gate on a substrate, whereafter a gate insulating layer (e.g. of silicon oxide S1O 2 ) is formed on the substrate and over the gate.
  • a gate insulating layer e.g. of silicon oxide S1O 2
  • the channel layer and finally the source and drain electrodes are then formed on the insulating layer.
  • a passivation layer which covers the channel and the source and drain, is usually formed on top.
  • the techniques used to form the aforementioned layers all need design-dedicated masks and/or materials removing processing steps for patterning each layer of the TFT stack.
  • the substrate can be flexible paper or a plastic, thus enabling manufacturing via roll-to-roll methods.
  • Additive printing is a low-waste and mask-less process that is well suited to produce large area structures at low cost.
  • the inks are prepared by dissolving compounds containing the desired materials such as metal nanoparticles for conductors, inorganic metal oxides or organic polymers for semiconductors and dielectric layers in a solvent or from precursor solutions that will convert into the desired compound via a thermal activation.
  • the printing is performed in as many steps as required to build the desired layer thickness.
  • the printed layers are annealed to remove any residual chemicals, to enable the desired electronic function and to improve the film quality.
  • semiconductor inks in amounts required for printing with roll-to-roll machines is very high.
  • the evenness, the low thickness and the low contamination of the surface of the semiconductor and insulator layers are critical requirements for the device performance, and need to be carefully optimized for printed semiconductors and gate insulators. Oxygen and moisture absorption at the surface of printed layers is also a problem.
  • the object of the present invention is to solve the problem relating to these two types of techniques by combining the benefits such as high-quality of a traditional deposition/etching process requiring design-dedicated tools with the design freedom and cost-effectiveness of printing.
  • the scope of protection sought for the inventive manufacturing method and electronics structure is stated in the appended claims.
  • the inventive method for the manufacturing of an electronic circuit on a substrate by stacking material layers to form a semiconductor component structure includes a combination of techniques of on one hand masking and depositing thin-film layers of metal and metal oxide materials to form discrete semiconductor components by a process selected from chemical or physical deposition
  • the inventive process includes printing with an ink containing electrically conductive particles, conductor inks based on metallo-organic- decomposition (MOD) or conductive organic polymers one or more electrodes and contacts for the electrodes, as well as the electric wires between the contacts of at least one other component and the terminals on the substrate.
  • MOD metallo-organic- decomposition
  • the printing is, of course, done according to a desired circuit diagram in order to produce a circuit for a specific purpose.
  • a circuit can be e.g. a display driver, a logic port, a gate circuitry or operational amplifiers.
  • the term "fabrication” is used for traditional semiconductor manufacturing techniques, usually requiring a mask on the material, deposition of a material layer and/or etching steps through the mask, and machining or other finishing steps to remove excess material.
  • Possible materials include metals like molybdenum, chromium, aluminium, copper etc., or conductive metal oxide materials.
  • Print means here any kind of printing with any kind of ink, where ink is deposited on the structure or substrate according to a digitally processed map or printing pattern or via pre-designed printing template.
  • critical thin materials layers requiring high-quality are fabricated e.g. by sputtering or other deposition methods, and connectors and other less critical parts of the circuitry are printed by means of digital inkjet printing, where no design-dedicated fabrication tools are needed.
  • no circuit design consideration is needed for the sputtered structures.
  • All design specific fabrication steps may be done using inkjet or some other printing technique that can be digitally patterned.
  • the sputtering produces an array of unconnected intermediate units that can be used in different circuit designs by making at least the inter-unit connections by printing.
  • the same design of the array of elementary units can be used for a high number of different final circuit designs that are customized using printing.
  • the method includes the steps of: A method according to claim 1 , wherein the method includes the steps of:
  • the source and drain electrodes for said field effect transistor may be deposited.
  • the gate electrode may be deposited.
  • the formed semiconductor component structure may be covered with a passivation layer.
  • the deposited electrode is the gate electrode of a thin-film field effect transistor (TFT), and the two printed electrodes on the opposite side of said dielectric and semiconductor layers are the source and drain electrodes of the same transistor.
  • the deposited electrodes are the source and drain electrodes and the gate electrode is the printed electrode.
  • all source, drain and gate electrodes can be deposited and only the connecting wiring printed, and the TFT transistors may be deposited on the substrate as a two-dimensional array n x m to form the required circuitry for different predetermined products.
  • the substrate used may be a flexible or rigid substrate such as glass, plastic, silicon, paper or textile.
  • the materials used in the inventive method will of course vary according to design choices and desired properties, and the materials mentioned hereinafter are by example only.
  • the electrode materials may be selected from one of the group of indium zinc oxide (IZO), indium tin oxide (ITO), aluminium doped zinc oxide (AZO) or an evaporated or sputtered metal, like copper, aluminum, chromium, or silver.
  • the dielectric material may be selected from one or several of the group of S1O2, Ta2O 5 , HfO2, ZrO2 or AI2O3, arranged in a single or a multilayer structure.
  • the semiconductor material may be selected from one of the group of silicon, polycrystalline silicon, amorphous silicon, indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), cupric oxide (CuO), cuprous oxide (Cu2O) or tin
  • the ink creating the electrically conductive patterns may be an ink containing silver, gold or copper nanoparticles, silver, gold, copper or aluminium flakes, or a precursor ink containing at least one metallo-organic complex.
  • a precursor ink contains metallo-organic complexes consisting typically of a metallic cation surrounded by anionic and coordinating ligand molecules.
  • ligand molecules then undergo a decomposition process, in order to bring the metal atoms into contact with each other.
  • the decomposition process may initiated or driven by a thermal, photonic, plasma, microwave, chemical or electrical sintering method.
  • the ligand decomposition process is an integral part of precursor ink printing, and is thus not part of the present invention as such.
  • the invention is also directed to an electronics circuit structure, consisting of discrete semiconductor components formed on a substrate by stacking thin-film layers of metal and metal oxide materials by chemical or physical deposition techniques, including sputtering, atomic layer deposition, vacuum evaporation, pulsed laser deposition, chemical vapour deposition, physical vapour deposition or molecular beam epitaxy, wherein at least the electric wiring between the contacts of said discrete components are printed according to a desired circuit diagram by using an ink creating electrically conductive patterns.
  • chemical or physical deposition techniques including sputtering, atomic layer deposition, vacuum evaporation, pulsed laser deposition, chemical vapour deposition, physical vapour deposition or molecular beam epitaxy, wherein at least the electric wiring between the contacts of said discrete components are printed according to a desired circuit diagram by using an ink creating electrically conductive patterns.
  • the discrete semiconductor components may consist of thin-film field-effect transistors (TFT), and the semiconductor component structure may be covered by a passivation layer.
  • TFT thin-film field-effect transistors
  • the present inventon also is directed to the use of of discrete semiconductor components formed on a substrate by the inventive method for the manufacture of a semiconductor component structure, where at least the electric wiring between the contacts of said discrete components are printed using an ink creating electrically conductive patterns according to a desired circuit diagram.
  • the manufacture and wiring of the circuit may be separated, so that the wiring is done later on e.g. at the premises of a customer of the circuit
  • Fig. 1 a-1 d shows an overview of known TFT transistor structures
  • Fig. 2 shows inventive components after a deposition (such as sputtering) phase
  • Fig. 3 shows the semiconductor components of Fig. 2 after a printing phase
  • Fig. 4a and Fig.4b shows inventive semiconductor components according to another embodiment after a deposition phase
  • Fig. 5 shows an example of an inventive semiconductor structure.
  • Fig. 1 a-1 d a selection of prior art top and bottom-gate TFT transistors is presented.
  • Figs. 1 a and 1 b show, from left to right, a staggered and a coplanar top-gate TFT transistor.
  • Figs. 1 c and 1 d show a staggered and a coplanar bottom-gate TFT transistor. All have in common a substrate 5, a gate 1 , a gate insulating layer 2, a semiconductor layer 3, and source and drain
  • the substrate is typically glass, the electrodes (gate, drain and source) metal or metal oxide, e.g. ITO.
  • the semiconductor layer may be made of e.g. amorphous silicon or indium gallium zinc oxide.
  • sputtering is one of the technologies well suited to fabricate such thin high-quality materials layers, but needs masks and/or materials removing fabrication steps.
  • the components can be fabricated by other chemical or physical deposition methods than sputtering such as atomic layer deposition (ALD), vacuum evaporation, pulsed laser deposition and chemical vapour deposition.
  • ALD atomic layer deposition
  • vacuum evaporation vacuum evaporation
  • pulsed laser deposition pulsed laser deposition
  • chemical vapour deposition chemical vapour deposition
  • Figure 2 shows an inventive semiconductor structure 10 to be fabricated by sputtering on a substrate 1 1 , here exemplified by top-gate FET transistors (two of them shown).
  • the structure in question is a stack of semiconductor and insulator materials, and may be repeated over the substrate as an array of components or elementary units.
  • the insulator 13 is smaller than the semiconductor layer 12 such that the semiconductor 12 can be contacted by the printable materials in a later fabrication step.
  • semiconductor and the insulator can be of the order of 20 nm for the
  • the semiconductor and 100 nm for the insulator for example.
  • the 20 nm thick layer is very difficult to fabricate using printing techniques. Optimization of the printing process for thin layers is pursued very widely but that is naturally limited to not very much below 100 nm, preferably the thickness of printed layers is much above 100 nm.
  • the horizontal resolution can be enhanced by fabricating the structures for a very short channel or by fabricating the drain and source electrodes as a fine finger structure using the chemical or physical deposition techniques such as sputtering.
  • Alternative embodiments of the intermediate product obtained in Fig. 2 may include:
  • the gate electrode and/or the drain and source electrodes are fabricated in fabrication steps using sputtering or some other fabrication technology
  • the components can be comprised of the gate electrode, the gate insulator and a semiconductor layer in bottom-gate top-contact configuration, where the source and drain are left to be created in the design-specific printing step;
  • the transistor structure is also not limited to the top-contact top-gate structure of Fig. 2.
  • the drain and source electrodes can be fabricated first on the substrate such that the semiconductor is then fabricated on top of the drain and source electrodes for a bottom contact structure;
  • the substrate can be flexible glass, plastic or paper substrate or a rigid
  • substrate such as glass or silicon
  • the fabricated components may occupy only a part of the substrate area or the final circuit design need not utilize all the elementary units on the substrate, leaving the rest of the substrate for other components like inverters, logical ports, passive components, integrated circuits, etc.;
  • the fabricated components may be complete transistors with sputtered drain, source and gate electrodes where only a printed wiring for creating circuits is needed.
  • the fabricated components may be inverters, logical ports or other circuit
  • elements such as capacitors and resistors such that printing is only used to make the contacts between these elements.
  • the invention can also be applied in other than transistor or logic port circuits whenever it is beneficial to use elementary units of thin materials layers where the actual design specific fabrication steps can be separated.
  • Fig. 3 shows the printing steps where the exemplified semiconductor structure of Fig. 2 is completed and the resulting elementary units are connected according to a desired circuit design.
  • the drain and source electrodes 16 and design- specific contacts 17 for the drain and source electrodes of different elementary units are printed.
  • the gate electrodes and circuit contacts for the gate electrodes 14 are printed.
  • a guard insulator 15 to avoid short circuits between the gate and the drain and source electrodes 16.
  • insulator layers between wiring 17 that is crossing, but not in electrical contact may be needed. Capacitors, resistors or other circuit elements may also be printed.
  • the design-specific manufacturing step can be performed by inkjet printing or by any other ink-based printing technology.
  • Alternative embodiments of the elementary units formed according to Fig. 3 may include:
  • the materials of the elementary units can be inorganic or organic or a
  • gate electrode and gate dielectric films can be printed for organic or inorganic thin film transistors
  • - redundant elementary units on the substrate may be used to control statistical variation between the elementary units, i.e. statistical variation can be averaged out by using more than one TFT to implement a single TFT function, or only the best conforming elementary units can be selected for the circuit implementation;
  • Fig. 4a an embodiment of the inventive semiconductor structure, a TFT transistor, having a bottom-gate top-contact configuration. Also exemplary dimensions are shown.
  • a gate electrode 21 and an isolating dielectric layer 22 on top of the gate see also the top view of the same in Fig. 4b.
  • a semiconductor layer 23 is deposited on top of the dielectric layer 22.
  • the TFT material stack in Figs. 4a and 4b may consist of a sputtered gate electrode 21 of ITO, IZO, AZO or evaporated metal, to ensure high conductivity.
  • the sputtered dielectric layer 22 may consist of a a single component oxide such as AI 2 O3 or a multilayer structure such as SiO 2 Ta 2 O 5 -SiO 2 SiO 2 multilayer structure or a SiO2 HfO2-SiO2 SiO2 multilayer structure,.
  • the thickness is preferably less than 300 nm.
  • the sputtered semiconductor layer 23 may consist of a IGZO with optimized composition with a thickness 10 - 20 nm (considering also the optimum thickness for achieving a low back channel conductance), and a minimum channel length of -10 ⁇ .
  • a sputtered and possibly patterned conductor layer can be fabricated on top of the semiconductor layer before printing the drain and source electrodes in the next step.
  • the TFT stack is then overprinted with source & drain electrodes and
  • the ink may be an ink with Ag nanoparticles.
  • TFTs with different properties such as different channel width-to-length-ratio can be fabricated in the printing step for realizing circuit elements such as an inverter.
  • the component may be spin-coated with a passivation layer (e.g. PMMA or SU-8).
  • a passivation layer e.g. PMMA or SU-8.
  • Fig. 5 an examplerary final inventive semiconductor product, consisting of TFT transistors deposited on the substrate as a two-dimensional nxm array or matrix 30, in this example a 10x10 array.
  • the elementary units 31 a, 31 b, 31 c ... 31 n correspond here to the components shown in Figs. 4a and 4b.
  • the inventive printing step as performed and explained in connection with Fig. 3 has been completed for a selection of six elementary units, that are used to implement a ring oscillator circuit.
  • the oscillator circuit has drain and source electrodes 16 and contacts and wiring 17 between electrodes of different elementary units.
  • the wiring 32 for the gates is shown, as well as external contacts for the supply voltage 33, ground connection 34 and output signal 35. Wiring for passive components (not shown) may be printed in a similar manner if needed in the circuit diagram.
  • the inventive concept offers a flexible approach to manufacture affordable component clusters on any substrate.

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Abstract

The present invention relates to the manufacture and use of semiconductor components and circuits on a substrate. According to the invention, fabrication techniques for thin-film layers of metal and metal oxide materials are used. The technique is selected from chemical or physical deposition techniques, including: sputtering, atomic layer deposition, vacuum evaporation, pulsed laser deposition, chemical vapour deposition, physical vapour deposition or molecular beam epitaxy. Discrete semiconductor components are produced, and at least the electric wiring between the contacts of the discrete components are printed using an ink creating electrically conductive patterns according to a desired circuit diagram.

Description

A method for the fabrication and use of electronic circuits and an electronics circuit structure
The present invention relates to the manufacture and use of semiconductor components and circuits on a substrate. In particular the invention relates to a method of forming thin-film material stacks to form arrays of semiconductor components, like transistors, and the interconnecting circuitry between them.
The field-effect transistor (FET) operates by the effects of a controllable electric field in a single-type (N-type or P-type) semiconductor material that forms the channel. The flow of charge carriers in the channel between a source and a drain connection is dependent on the voltage applied on a gate electrode that is separated from the channel by a dielectric layer. A FET has in principle a simple and layered structure.
A thin-film FET transistor (TFT) is a special kind of field-effect transistor made by depositing thin films of active semiconductor layers as well as dielectric layers and metallic contacts over a supporting (but non-conducting) substrate. A common substrate is glass, and here the TFT differs from a conventional metal-oxide- semiconductor (MOS) FET transistor, where the substrate typically is a silicon wafer being of opposite semiconductor type than that of the unipolar channel.
A thin film transistor (TFT) may be applied in various fields of technology. TFT is frequently used in flat panel display devices such as LCD's and active-matrix organic light-emitting diode (AMOLED) panels. In an active matrix configuration, TFTs are used to control a single pixel of the display, which has benefits for the stability and resolution of the display. Conventionally, in such applications, the semiconductor layer in TFTs is fabricated either from polycrystalline silicon (poly- Si) or amorphous silicon (a-Si).
New and versatile oxide semiconductor materials have properties beyond conventional a-Si or poly-Si materials, such as a high band-gap allowing transparency in the visible range, ionic nature allowing high charge-carrier mobility even in amorphous phase, and a low charge carrier concentration at conduction band. This enables the use of TFT transistors in various new and improved applications. For example, a ZnO-based semiconductor film may be manufactured at low temperature processes enabling the fabrication of TFTs on low cost flexible substrates. Ga- and In-doped ZnO (GalnZnO) high-mobility semiconductors (gallium indium zinc oxide, GIZO) can be used for fabricating the FET channel. In contrast to a-Si, it can be amorphous without deterioration of the charge carrier mobility. The electrical characteristics of such devices can exceed the properties of a-Si TFTs. Many TFTs have indium-doped tin oxide (ITO) as the material for the source/drain electrodes.
Traditionally, the oxide layers of thin film components, like semiconductor-gate insulator stacks or logic ports and other elementary units, are fabricated by vacuum techniques such as sputtering, pulsed laser deposition or atomic layer deposition, which can provide thin material layers of high quality. The quality of the semiconducting layer, the insulating layer and their interface where the channel is located are of utmost importance for realizing high-performance devices. A typical process is to form a gate on a substrate, whereafter a gate insulating layer (e.g. of silicon oxide S1O2) is formed on the substrate and over the gate. The channel layer and finally the source and drain electrodes are then formed on the insulating layer. A passivation layer which covers the channel and the source and drain, is usually formed on top. However, the techniques used to form the aforementioned layers all need design-dedicated masks and/or materials removing processing steps for patterning each layer of the TFT stack.
Recently, inkjet and other additive and/or digital printing technologies, like flexographic and gravure printing, has been used to construct electronic circuits such as TFT semiconductor-insulator stacks or logic ports. Here, the substrate can be flexible paper or a plastic, thus enabling manufacturing via roll-to-roll methods. Additive printing is a low-waste and mask-less process that is well suited to produce large area structures at low cost. The inks are prepared by dissolving compounds containing the desired materials such as metal nanoparticles for conductors, inorganic metal oxides or organic polymers for semiconductors and dielectric layers in a solvent or from precursor solutions that will convert into the desired compound via a thermal activation. The printing is performed in as many steps as required to build the desired layer thickness. Finally, the printed layers are annealed to remove any residual chemicals, to enable the desired electronic function and to improve the film quality. By repeating the printing and annealing step with different materials, TFT stacks can be produced.
However, producing thin high-quality and high-purity layers of semiconductor and gate insulator materials that are needed in TFT transistors is still difficult using solution processing techniques such as printing. For example, the annealing temperatures required for the onset of the high-quality performance of the metal oxide semiconductor layers are typically beyond the thermal budget of the flexible low-cost substrates. On the other hand, the cost of high-purity organic
semiconductor inks in amounts required for printing with roll-to-roll machines is very high. In addition, the evenness, the low thickness and the low contamination of the surface of the semiconductor and insulator layers are critical requirements for the device performance, and need to be carefully optimized for printed semiconductors and gate insulators. Oxygen and moisture absorption at the surface of printed layers is also a problem.
The object of the present invention is to solve the problem relating to these two types of techniques by combining the benefits such as high-quality of a traditional deposition/etching process requiring design-dedicated tools with the design freedom and cost-effectiveness of printing. The scope of protection sought for the inventive manufacturing method and electronics structure is stated in the appended claims.
The inventive method for the manufacturing of an electronic circuit on a substrate by stacking material layers to form a semiconductor component structure includes a combination of techniques of on one hand masking and depositing thin-film layers of metal and metal oxide materials to form discrete semiconductor components by a process selected from chemical or physical deposition
techniques, including: sputtering, atomic layer deposition, vacuum evaporation, pulsed laser deposition, chemical vapour deposition, physical vapour deposition or molecular beam epitaxy. On the other hand the inventive process includes printing with an ink containing electrically conductive particles, conductor inks based on metallo-organic- decomposition (MOD) or conductive organic polymers one or more electrodes and contacts for the electrodes, as well as the electric wires between the contacts of at least one other component and the terminals on the substrate. The printing is, of course, done according to a desired circuit diagram in order to produce a circuit for a specific purpose. Such a circuit can be e.g. a display driver, a logic port, a gate circuitry or operational amplifiers.
In the context of the present patent application, the term "fabrication" is used for traditional semiconductor manufacturing techniques, usually requiring a mask on the material, deposition of a material layer and/or etching steps through the mask, and machining or other finishing steps to remove excess material. Possible materials include metals like molybdenum, chromium, aluminium, copper etc., or conductive metal oxide materials. "Printing" means here any kind of printing with any kind of ink, where ink is deposited on the structure or substrate according to a digitally processed map or printing pattern or via pre-designed printing template.
According to one embodiment of the invention, critical thin materials layers requiring high-quality are fabricated e.g. by sputtering or other deposition methods, and connectors and other less critical parts of the circuitry are printed by means of digital inkjet printing, where no design-dedicated fabrication tools are needed. Vice versa, no circuit design consideration is needed for the sputtered structures. All design specific fabrication steps may be done using inkjet or some other printing technique that can be digitally patterned. In other words, the sputtering produces an array of unconnected intermediate units that can be used in different circuit designs by making at least the inter-unit connections by printing. The same design of the array of elementary units can be used for a high number of different final circuit designs that are customized using printing. The invention thus combines the benefits of both approaches while avoiding the mentioned drawbacks. According to one embodiment of the invention the method includes the steps of: A method according to claim 1 , wherein the method includes the steps of:
- depositing a layer of a metal or metal oxide material on the substrate to form a gate electrode for at least one field effect transistor,
- depositing a layer of a dielectric material on the deposited gate
electrode,
- depositing a layer of semiconductor material on said dielectric material layer,
- printing using an ink creating electrically conductive patterns to form printed source and drain electrodes for said field effect transistor to be in contact with said semiconductor layer: Alternatively, the source and drain electrodes for said field effect transistor may be deposited.
With this process it is, for example, possible to produce bottom-gate TFT transistors and circuits.
According to one embodiment of the invention the method includes the steps of:
- depositing on said substrate layers of a metal or metal oxide conductor and semiconductor material, to form conducting source and drain electrodes for at least one field effect transistor separated by said semiconductor material;
- depositing a layer of a dielectric material on said semiconductor
material layer,
- printing using an ink creating electrically conductive patterns to form a printed gate electrode for said field effect transistor on said dielectric material layer. Alternatively, the gate electrode may be deposited.
- printing using an ink creating electrically conductive patterns contacts and terminals for said at least one field effect transistor and the interconnecting wires of other components formed on said substrate. With this process it is, for example, possible to produce top-gate TFT transistors..
According to an embodiment of the inventive method, the formed semiconductor component structure may be covered with a passivation layer. Typically, the deposited electrode is the gate electrode of a thin-film field effect transistor (TFT), and the two printed electrodes on the opposite side of said dielectric and semiconductor layers are the source and drain electrodes of the same transistor. Alternatively, the deposited electrodes are the source and drain electrodes and the gate electrode is the printed electrode. Furthermore, all source, drain and gate electrodes can be deposited and only the connecting wiring printed, and the TFT transistors may be deposited on the substrate as a two-dimensional array n x m to form the required circuitry for different predetermined products. The substrate used may be a flexible or rigid substrate such as glass, plastic, silicon, paper or textile. The materials used in the inventive method will of course vary according to design choices and desired properties, and the materials mentioned hereinafter are by example only. The electrode materials may be selected from one of the group of indium zinc oxide (IZO), indium tin oxide (ITO), aluminium doped zinc oxide (AZO) or an evaporated or sputtered metal, like copper, aluminum, chromium, or silver. The dielectric material may be selected from one or several of the group of S1O2, Ta2O5, HfO2, ZrO2 or AI2O3, arranged in a single or a multilayer structure. The semiconductor material may be selected from one of the group of silicon, polycrystalline silicon, amorphous silicon, indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), cupric oxide (CuO), cuprous oxide (Cu2O) or tin
monoxide (SnO).
The ink creating the electrically conductive patterns may be an ink containing silver, gold or copper nanoparticles, silver, gold, copper or aluminium flakes, or a precursor ink containing at least one metallo-organic complex. A precursor ink contains metallo-organic complexes consisting typically of a metallic cation surrounded by anionic and coordinating ligand molecules. In contrast to
convetional inkjet printing, where the solvents dries and leaves the color or metal ink particles deposited on the substrate, precursor inks causes during printing a metal complex to be deposited on the substrate. The ligand molecules then undergo a decomposition process, in order to bring the metal atoms into contact with each other. The decomposition process may initiated or driven by a thermal, photonic, plasma, microwave, chemical or electrical sintering method. The ligand decomposition process is an integral part of precursor ink printing, and is thus not part of the present invention as such.
The invention is also directed to an electronics circuit structure, consisting of discrete semiconductor components formed on a substrate by stacking thin-film layers of metal and metal oxide materials by chemical or physical deposition techniques, including sputtering, atomic layer deposition, vacuum evaporation, pulsed laser deposition, chemical vapour deposition, physical vapour deposition or molecular beam epitaxy, wherein at least the electric wiring between the contacts of said discrete components are printed according to a desired circuit diagram by using an ink creating electrically conductive patterns.
The discrete semiconductor components may consist of thin-film field-effect transistors (TFT), and the semiconductor component structure may be covered by a passivation layer.
The present inventon also is directed to the use of of discrete semiconductor components formed on a substrate by the inventive method for the manufacture of a semiconductor component structure, where at least the electric wiring between the contacts of said discrete components are printed using an ink creating electrically conductive patterns according to a desired circuit diagram. In such a case, the manufacture and wiring of the circuit may be separated, so that the wiring is done later on e.g. at the premises of a customer of the circuit
manufacturer.
Further embodiments of the inventon are characterized by what is presented in the appended claims.
The invention is in the following described in detail by way of examples and by referring to the attached drawings, wherein Fig. 1 a-1 d shows an overview of known TFT transistor structures;
Fig. 2 shows inventive components after a deposition (such as sputtering) phase; Fig. 3 shows the semiconductor components of Fig. 2 after a printing phase;
Fig. 4a and Fig.4b shows inventive semiconductor components according to another embodiment after a deposition phase;
Fig. 5 shows an example of an inventive semiconductor structure.
In Fig. 1 a-1 d a selection of prior art top and bottom-gate TFT transistors is presented. Figs. 1 a and 1 b show, from left to right, a staggered and a coplanar top-gate TFT transistor. Respectively, Figs. 1 c and 1 d show a staggered and a coplanar bottom-gate TFT transistor. All have in common a substrate 5, a gate 1 , a gate insulating layer 2, a semiconductor layer 3, and source and drain
electrodes 4. The substrate is typically glass, the electrodes (gate, drain and source) metal or metal oxide, e.g. ITO. The semiconductor layer may be made of e.g. amorphous silicon or indium gallium zinc oxide.
In terms of manufacturing, sputtering is one of the technologies well suited to fabricate such thin high-quality materials layers, but needs masks and/or materials removing fabrication steps. The components can be fabricated by other chemical or physical deposition methods than sputtering such as atomic layer deposition (ALD), vacuum evaporation, pulsed laser deposition and chemical vapour deposition.
Figure 2 shows an inventive semiconductor structure 10 to be fabricated by sputtering on a substrate 1 1 , here exemplified by top-gate FET transistors (two of them shown). The structure in question is a stack of semiconductor and insulator materials, and may be repeated over the substrate as an array of components or elementary units. The insulator 13 is smaller than the semiconductor layer 12 such that the semiconductor 12 can be contacted by the printable materials in a later fabrication step. For transistor applications the layer thicknesses of the
semiconductor and the insulator can be of the order of 20 nm for the
semiconductor and 100 nm for the insulator for example. Especially the 20 nm thick layer is very difficult to fabricate using printing techniques. Optimization of the printing process for thin layers is pursued very widely but that is naturally limited to not very much below 100 nm, preferably the thickness of printed layers is much above 100 nm. In addition to enhancing the vertical resolution (thin layers) of the devices as compared to fully printed structures, also the horizontal resolution can be enhanced by fabricating the structures for a very short channel or by fabricating the drain and source electrodes as a fine finger structure using the chemical or physical deposition techniques such as sputtering.
Alternative embodiments of the intermediate product obtained in Fig. 2 may include:
- the gate electrode and/or the drain and source electrodes are fabricated in fabrication steps using sputtering or some other fabrication technology;
- the components can be comprised of the gate electrode, the gate insulator and a semiconductor layer in bottom-gate top-contact configuration, where the source and drain are left to be created in the design-specific printing step; - the transistor structure is also not limited to the top-contact top-gate structure of Fig. 2. For example, the drain and source electrodes can be fabricated first on the substrate such that the semiconductor is then fabricated on top of the drain and source electrodes for a bottom contact structure;
- the substrate can be flexible glass, plastic or paper substrate or a rigid
substrate such as glass or silicon;
- the fabricated components may occupy only a part of the substrate area or the final circuit design need not utilize all the elementary units on the substrate, leaving the rest of the substrate for other components like inverters, logical ports, passive components, integrated circuits, etc.;
- the fabricated components may be complete transistors with sputtered drain, source and gate electrodes where only a printed wiring for creating circuits is needed.
- the fabricated components may be inverters, logical ports or other circuit
elements such as capacitors and resistors such that printing is only used to make the contacts between these elements. The invention can also be applied in other than transistor or logic port circuits whenever it is beneficial to use elementary units of thin materials layers where the actual design specific fabrication steps can be separated.
Fig. 3 shows the printing steps where the exemplified semiconductor structure of Fig. 2 is completed and the resulting elementary units are connected according to a desired circuit design. Here the drain and source electrodes 16 and design- specific contacts 17 for the drain and source electrodes of different elementary units are printed. Also the gate electrodes and circuit contacts for the gate electrodes 14 are printed. In fig. 3 is shown a guard insulator 15 to avoid short circuits between the gate and the drain and source electrodes 16. In the printing step also insulator layers between wiring 17 that is crossing, but not in electrical contact, may be needed. Capacitors, resistors or other circuit elements may also be printed.
The design-specific manufacturing step can be performed by inkjet printing or by any other ink-based printing technology. Alternative embodiments of the elementary units formed according to Fig. 3 may include:
- two different separated or connected structures, to be used e.g. as a drive and a load transistor pairs of an inverter;
- the materials of the elementary units can be inorganic or organic or a
combination of these, and the gate electrode and gate dielectric films can be printed for organic or inorganic thin film transistors;
- any number of different elementary units meant to be connected as logical ports etc.;
- redundant elementary units on the substrate may be used to control statistical variation between the elementary units, i.e. statistical variation can be averaged out by using more than one TFT to implement a single TFT function, or only the best conforming elementary units can be selected for the circuit implementation;
- circuit designs that are dedicated to utilize the high number of available similar or sufficiently different elementary units. In Fig. 4a is shown an embodiment of the inventive semiconductor structure, a TFT transistor, having a bottom-gate top-contact configuration. Also exemplary dimensions are shown. On a substrate 20 is sputtered a gate electrode 21 and an isolating dielectric layer 22 on top of the gate, see also the top view of the same in Fig. 4b. A semiconductor layer 23 is deposited on top of the dielectric layer 22.
The TFT material stack in Figs. 4a and 4b may consist of a sputtered gate electrode 21 of ITO, IZO, AZO or evaporated metal, to ensure high conductivity. The sputtered dielectric layer 22 may consist of a a single component oxide such as AI2O3 or a multilayer structure such as SiO2 Ta2O5-SiO2 SiO2 multilayer structure or a SiO2 HfO2-SiO2 SiO2 multilayer structure,. The thickness is preferably less than 300 nm. The sputtered semiconductor layer 23 may consist of a IGZO with optimized composition with a thickness 10 - 20 nm (considering also the optimum thickness for achieving a low back channel conductance), and a minimum channel length of -10 μιτι. To optimize the electrical contact to the semiconductor layer, a sputtered and possibly patterned conductor layer can be fabricated on top of the semiconductor layer before printing the drain and source electrodes in the next step.
The TFT stack is then overprinted with source & drain electrodes and
interconnecting wiring (see Fig. 5). The ink may be an ink with Ag nanoparticles. TFTs with different properties such as different channel width-to-length-ratio can be fabricated in the printing step for realizing circuit elements such as an inverter.
Finally, the component may be spin-coated with a passivation layer (e.g. PMMA or SU-8).
In Fig. 5 is shown an exemplerary final inventive semiconductor product, consisting of TFT transistors deposited on the substrate as a two-dimensional nxm array or matrix 30, in this example a 10x10 array. The elementary units 31 a, 31 b, 31 c ... 31 n correspond here to the components shown in Figs. 4a and 4b. The inventive printing step as performed and explained in connection with Fig. 3 has been completed for a selection of six elementary units, that are used to implement a ring oscillator circuit. The oscillator circuit has drain and source electrodes 16 and contacts and wiring 17 between electrodes of different elementary units. Also the wiring 32 for the gates is shown, as well as external contacts for the supply voltage 33, ground connection 34 and output signal 35. Wiring for passive components (not shown) may be printed in a similar manner if needed in the circuit diagram. As can be readily seen, the inventive concept offers a flexible approach to manufacture affordable component clusters on any substrate.
It is to be understood that the embodiments of the invention disclosed are not limited to the particular structures, process steps, or materials disclosed herein, but are extended to equivalents thereof as would be recognized by those ordinarily skilled in the relevant arts. It should also be understood that terminology employed herein is used for the purpose of describing particular embodiments only and is not intended to be limiting.
Reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment.
As used herein, a plurality of items, structural elements, compositional elements, and/or materials may be presented in a common list for convenience. However, these lists should be construed as though each member of the list is individually identified as a separate and unique member. Thus, no individual member of such list should be construed as a de facto equivalent of any other member of the same list solely based on their presentation in a common group without indications to the contrary. In addition, various embodiments and example of the present invention may be referred to herein along with alternatives for the various components thereof. It is understood that such embodiments, examples, and alternatives are not to be construed as de facto equivalents of one another, but are to be considered as separate and autonomous representations of the present invention. Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided, such as examples of lengths, widths, shapes, etc., to provide a thorough understanding of embodiments of the invention. One skilled in the relevant art will recognize, however, that the invention can be practiced without one or more of the specific details, or with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of the invention.
While the forgoing examples are illustrative of the principles of the present invention in one or more particular applications, it will be apparent to those of ordinary skill in the art that numerous modifications in form, usage and details of implementation can be made without the exercise of inventive faculty, and without departing from the principles and concepts of the invention. Accordingly, it is not intended that the invention be limited, except as by the claims set forth below.

Claims

Claims
1 . A method for the manufacture of a semiconductor component structure on a substrate by stacking material layers to form said component structure, in which method is used fabrication techniques for thin-film layers of metal and metal oxide materials selected from chemical or physical deposition
techniques, including: sputtering, atomic layer deposition, vacuum evaporation, pulsed laser deposition, chemical vapour deposition, physical vapour deposition or molecular beam epitaxy; to produce discrete semiconductor components, and wherein either the electric wiring between the contacts of said discrete components or the electric wiring between the contacts of said discrete components and single or multiple electrodes of said discrete components are printed using an ink for creating conductive patterns according to a desired circuit diagram.
A method according to claim 1 , wherein the method includes the steps of:
- depositing a layer of a metal or metal oxide material on said substrate to form a gate electrode for at least one field effect transistor,
- depositing a layer of a dielectric material on the deposited gate
electrode,
- depositing a layer of semiconductor material on said dielectric material layer,
- printing using an ink creating electrically conductive patterns to form printed source and drain electrodes for said field effect transistor to be in contact with said semiconductor layer, and
- printing using an ink creating electrically conductive patterns contacts and terminals for said at least one field effect transistor and the interconnecting wires of other components formed on said substrate.
. A method according to claim 1 , wherein the method includes the steps of: - depositing a layer of a metal or metal oxide material on said substrate to form a gate electrode for at least one field effect transistor,
- depositing a layer of a dielectric material on the deposited gate
electrode,
- depositing a layer of semiconductor material on said dielectric material layer,
- depositing a metal or metal oxide material to form source and drain electrodes for said field effect transistor to be in contact with said semiconductor layer, and
- printing using an ink creating electrically conductive patterns contacts and terminals for said at least one field effect transistor and the interconnecting wires of other components formed on said substrate.
4. A method according to claim 1 , wherein the method includes the steps of:
- depositing on said substrate layers of a metal or metal oxide conductor and semiconductor material, to form conducting source and drain electrodes for at least one field effect transistor separated by said semiconductor material;
- depositing a layer of a dielectric material on said semiconductor
material layer,
- printing using an ink creating electrically conductive patterns to form a printed gate electrode for said field effect transistor on said dielectric material layer, and
- printing using an ink creating electrically conductive patterns contacts and terminals for said at least one field effect transistor and the interconnecting wires of other components formed on said substrate.
5. A method according to claim 1 , wherein the method includes the steps of:
- depositing on said substrate layers of a metal or metal oxide conductor and semiconductor material, to form conducting source and drain electrodes for least one field effect transistor separated by said semiconductor material;
- depositing a layer of a dielectric material on said semiconductor
material layer, - depositing a metal or metal oxide material to form a gate electrode for said field effect transistor on said dielectric material layer, and
- printing using an ink creating electrically conductive patterns contacts and terminals for said at least one field effect transistor and the interconnecting wires of other components formed on said substrate.
6. A method according to any of claims 1 - 5, wherein method includes the step of covering the formed semiconductor component structure by a passivation layer.
7. A method according to claim 2 or 6, wherein the deposited electrode is the gate electrode of a thin-film field effect transistor (TFT), and the two printed electrodes on the opposite side of said dielectric and semiconductor layers are the source and drain electrodes of the same transistor.
8. A method according to claim 4 or 6, wherein the deposited electrodes are the source and drain electrodes of a thin-film field effect transistor (TFT), and the printed electrode is the gate electrode of the same transistor.
9. A method according to any of claims 1 - 8, wherein the contacts for the source, drain and gate electrodes of a thin-film field effect transistor (TFT) and the electric wires interconnecting the components and terminals on the substrate are printed on the deposited semiconductor structure.
10. A method according to any of claims 1 - 9, wherein additional passive circuit elements and their contacts and terminals are fabricated on the substrate by said deposition and printing processes, whereby the printed interconnecting wires also connect said passive circuits according to a desired circuit diagram.
1 1 . A method according to claim 10, wherein the passive circuit elements are chosen from the group of capacitors, resistors, wiring cross-over isolation structures or connecting terminals for active components..
12. A method according to any of claims 1 - 9, wherein the TFT transistors are deposited on the substrate as a two-dimensional array n x m.
13. A method according to any of claims 1 - 5, wherein said metal oxide material for forming deposited electrodes is selected from one of the group of indium zinc oxide, indium tin oxide, aluminium-doped zinc oxide.
14. A method according to any of claims 1 - 5, wherein said metal oxide material for forming deposited electrodes is selected from one of the group of an evaporated metal such as copper, aluminium or silver.
15. A method according to any of claims 1 - 5, wherein said dielectric material is selected from one or several of the group of S1O2, Ta2O5, HfO2, ZrO2, or AI2O3, arranged in a single or a multilayer structure.
16. A method according to any of claims 1 - 5, wherein said semiconductor material is selected from one of the group of silicon, amorphous silicon, indium gallium zinc oxide, indium zinc oxide, gallium zinc oxide, indium oxide, gallium oxide, zinc oxide, zinc tin oxide, tin dioxide, cuprous oxide, cupric oxide or tin monoxide.
17. A method according to any of claims 1 - 10, wherein said electrically conductive patterns are printed using an ink containing electrically conductive nanoparticles or flakes of a metal, such as silver, gold, aluminium or copper.
18. A method according to any of claims 1 - 10, wherein said electrically conductive patterns are printed using a precursor ink containing at least one metallo-organic complex.
19. A method according to any of claims 1 - 10, wherein said substrate is glass, plastic, silicon, paper or textile.
20. A semiconductor component structure consisting of discrete semiconductor components formed on a substrate by stacking thin-film layers of metal and metal oxide materials by chemical or physical deposition techniques, including
sputtering, atomic layer deposition, vacuum evaporation, pulsed laser deposition, chemical vapour deposition, physical vapour deposition or molecular beam epitaxy, and wherein either the electric wiring between the contacts of said discrete components or the electric wiring between the contacts of said discrete components and single or multiple electrodes of said discrete components are printed using an ink for creating conductive patterns according to a desired circuit diagram.
21 . A semiconductor component structure according to claim 20, wherein each semiconductor component on said substrate consists of a metal or metal oxide material layer deposited on said substrate forming a gate electrode for at least one field effect transistor, a deposited layer of a dielectric material on said electrode, a deposited layer of semiconductor material on said dielectric material layer, and printed source and drain electrodes for said field effect transistor being in contact with said semiconductor material, and a printed pattern of interconnecting wires for other components formed on said substrate.
22. A semiconductor component structure according to claim 20, wherein each semiconductor component on said substrate consists of a metal or metal oxide material layer deposited on said substrate forming a gate electrode for at least one field effect transistor, a deposited layer of a dielectric material on said electrode, a deposited layer of semiconductor material on said dielectric material layer, and deposited source and drain electrodes for said field effect transistor being in contact with said semiconductor material, and a printed pattern of interconnecting wires for other components formed on said substrate.
23. A semiconductor component structure according to claim 20, wherein each semiconductor component on said substrate consists of layers deposited on said substrate and consisting of a metal or metal oxide material and a semiconductor material forming the source and drain electrodes for at least one field effect transistor separated by said semiconductor material, a deposited dielectric material layer on said semiconductor material, a printed gate electrode for said field effect transistor on said dielectric material layer, and a printed pattern of interconnecting wires for other components formed on said substrate.
24. A semiconductor component structure according to claim 20, wherein each semiconductor component on said substrate consists of layers deposited on said substrate and consisting of a metal or metal oxide material and a semiconductor material forming the source and drain electrodes for at least one field effect transistor separated by said semiconductor material, a deposited dielectric material layer on said semiconductor material, a deposited gate electrode for said field effect transistor on said dielectric material layer, and a printed pattern of interconnecting wires for other components formed on said substrate.
25 A semiconductor component structure according to any of claims 20-24 wherein the semiconductor components consist of thin-film field-effect transistors (TFT).
26. A semiconductor component structure according to claim 25, wherein the TFT transistors are deposited on the substrate as a two-dimensional array n x m.
27. A semiconductor component structure according to any of claims 20 - 26, wherein the semiconductor component structure is covered by a passivation layer.
28. Use of discrete semiconductor components formed on a substrate by stacking thin-film layers of metal and metal oxide materials by chemical or physical deposition techniques, including sputtering, atomic layer deposition, vacuum evaporation, pulsed laser deposition, chemical vapour deposition, physical vapour deposition or molecular beam epitaxy, in a method for the manufacture of a semiconductor component structure according to any of claims 1 - 19, and wherein either the the electric wiring between the contacts of said discrete components or the electric wiring between the contacts of said discrete
components and single or multiple electrodes of said discrete components are printed using an ink for creating conductive patterns according to a desired circuit diagram.
PCT/FI2014/050879 2013-11-19 2014-11-18 A method for the fabrication and use of electronic circuits and an electronics circuit structure WO2015075310A1 (en)

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