KR101089530B1 - 반도체 장치 및 데이터 처리 시스템 - Google Patents

반도체 장치 및 데이터 처리 시스템 Download PDF

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Publication number
KR101089530B1
KR101089530B1 KR1020090054839A KR20090054839A KR101089530B1 KR 101089530 B1 KR101089530 B1 KR 101089530B1 KR 1020090054839 A KR1020090054839 A KR 1020090054839A KR 20090054839 A KR20090054839 A KR 20090054839A KR 101089530 B1 KR101089530 B1 KR 101089530B1
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South Korea
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information
ports
data
terminal
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English (en)
Korean (ko)
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KR20090133083A (ko
Inventor
도루 이시카와
사치코 가미사키
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엘피다 메모리 가부시키가이샤
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/12015—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising clock generation or timing circuitry
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/14—Implementation of control logic, e.g. test mode decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1045—Read-write mode select circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/109—Control signal input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/06—Address interface arrangements, e.g. address buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/10—Aspects relating to interfaces of memory device to external buses
    • G11C2207/107—Serial-parallel conversion of data or prefetch

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Dram (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Tests Of Electronic Circuits (AREA)
KR1020090054839A 2008-06-23 2009-06-19 반도체 장치 및 데이터 처리 시스템 Expired - Fee Related KR101089530B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JPJP-P-2008-162799 2008-06-23
JP2008162799A JP5588100B2 (ja) 2008-06-23 2008-06-23 半導体装置およびデータ処理システム

Related Child Applications (2)

Application Number Title Priority Date Filing Date
KR1020110020558A Division KR20110031445A (ko) 2008-06-23 2011-03-08 반도체 장치 및 데이터 처리 시스템
KR1020110020556A Division KR20110033988A (ko) 2008-06-23 2011-03-08 반도체 장치 및 데이터 처리 시스템

Publications (2)

Publication Number Publication Date
KR20090133083A KR20090133083A (ko) 2009-12-31
KR101089530B1 true KR101089530B1 (ko) 2011-12-05

Family

ID=41431150

Family Applications (3)

Application Number Title Priority Date Filing Date
KR1020090054839A Expired - Fee Related KR101089530B1 (ko) 2008-06-23 2009-06-19 반도체 장치 및 데이터 처리 시스템
KR1020110020556A Ceased KR20110033988A (ko) 2008-06-23 2011-03-08 반도체 장치 및 데이터 처리 시스템
KR1020110020558A Ceased KR20110031445A (ko) 2008-06-23 2011-03-08 반도체 장치 및 데이터 처리 시스템

Family Applications After (2)

Application Number Title Priority Date Filing Date
KR1020110020556A Ceased KR20110033988A (ko) 2008-06-23 2011-03-08 반도체 장치 및 데이터 처리 시스템
KR1020110020558A Ceased KR20110031445A (ko) 2008-06-23 2011-03-08 반도체 장치 및 데이터 처리 시스템

Country Status (3)

Country Link
US (1) US7944767B2 (enExample)
JP (1) JP5588100B2 (enExample)
KR (3) KR101089530B1 (enExample)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100695432B1 (ko) 2005-09-28 2007-03-16 주식회사 하이닉스반도체 직렬 입/출력 인터페이스를 가진 멀티 포트 메모리 소자
KR100697832B1 (ko) 2006-03-06 2007-03-20 엠텍비젼 주식회사 복수개의 포트를 가진 메모리 장치와 그 테스트 방법
JP2007287306A (ja) 2006-04-13 2007-11-01 Hynix Semiconductor Inc 直列入／出力インターフェースを有するマルチポートメモリ素子及びその動作モードの制御方法

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6298437A (ja) * 1985-10-24 1987-05-07 Oki Electric Ind Co Ltd マイクロコンピユ−タ
JPH08278916A (ja) * 1994-11-30 1996-10-22 Hitachi Ltd マルチチャネルメモリシステム、転送情報同期化方法及び信号転送回路
US5799209A (en) * 1995-12-29 1998-08-25 Chatter; Mukesh Multi-port internally cached DRAM system utilizing independent serial interfaces and buffers arbitratively connected under a dynamic configuration
JP2001195899A (ja) * 2000-01-06 2001-07-19 Mitsubishi Electric Corp 半導体記憶装置
KR100609038B1 (ko) * 2004-05-06 2006-08-09 주식회사 하이닉스반도체 직렬 입/출력 인터페이스를 가진 멀티-포트 메모리 소자
US7395476B2 (en) * 2004-10-29 2008-07-01 International Business Machines Corporation System, method and storage medium for providing a high speed test interface to a memory subsystem
JP2006277872A (ja) 2005-03-30 2006-10-12 Elpida Memory Inc 半導体記憶装置及びそのテスト方法
KR100721581B1 (ko) * 2005-09-29 2007-05-23 주식회사 하이닉스반도체 직렬 입/출력 인터페이스를 가진 멀티 포트 메모리 소자
KR100695437B1 (ko) * 2006-04-13 2007-03-16 주식회사 하이닉스반도체 멀티 포트 메모리 소자
KR100695435B1 (ko) * 2006-04-13 2007-03-16 주식회사 하이닉스반도체 반도체 메모리 소자
KR100723889B1 (ko) * 2006-06-30 2007-05-31 주식회사 하이닉스반도체 직렬 입/출력 인터페이스를 가진 멀티 포트 메모리 소자
JP5579372B2 (ja) * 2008-04-25 2014-08-27 ピーエスフォー ルクスコ エスエイアールエル 半導体集積回路
US8407427B2 (en) * 2008-10-29 2013-03-26 Silicon Image, Inc. Method and system for improving serial port memory communication latency and reliability

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100695432B1 (ko) 2005-09-28 2007-03-16 주식회사 하이닉스반도체 직렬 입/출력 인터페이스를 가진 멀티 포트 메모리 소자
KR100697832B1 (ko) 2006-03-06 2007-03-20 엠텍비젼 주식회사 복수개의 포트를 가진 메모리 장치와 그 테스트 방법
JP2007287306A (ja) 2006-04-13 2007-11-01 Hynix Semiconductor Inc 直列入／出力インターフェースを有するマルチポートメモリ素子及びその動作モードの制御方法

Also Published As

Publication number Publication date
US20090316510A1 (en) 2009-12-24
US7944767B2 (en) 2011-05-17
KR20110033988A (ko) 2011-04-04
KR20110031445A (ko) 2011-03-28
JP2010003377A (ja) 2010-01-07
JP5588100B2 (ja) 2014-09-10
KR20090133083A (ko) 2009-12-31

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