KR101020846B1 - 비휘발성 반도체 메모리 및 그 구동방법 - Google Patents
비휘발성 반도체 메모리 및 그 구동방법 Download PDFInfo
- Publication number
- KR101020846B1 KR101020846B1 KR1020097000601A KR20097000601A KR101020846B1 KR 101020846 B1 KR101020846 B1 KR 101020846B1 KR 1020097000601 A KR1020097000601 A KR 1020097000601A KR 20097000601 A KR20097000601 A KR 20097000601A KR 101020846 B1 KR101020846 B1 KR 101020846B1
- Authority
- KR
- South Korea
- Prior art keywords
- line
- source line
- nonvolatile semiconductor
- source
- semiconductor memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
- G11C16/0416—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/08—Address circuits; Decoders; Word-line control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
- H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/68—Floating-gate IGFETs
- H10D30/689—Vertical floating-gate IGFETs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/69—IGFETs having charge trapping gate insulators, e.g. MNOS transistors
- H10D30/693—Vertical IGFETs having charge trapping gate insulators
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/10—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/10—EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/68—Floating-gate IGFETs
- H10D30/681—Floating-gate IGFETs having only two programming levels
- H10D30/684—Floating-gate IGFETs having only two programming levels programmed by hot carrier injection
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
- Read Only Memory (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JPJP-P-2006-191470 | 2006-07-12 | ||
| JP2006191470A JP5088465B2 (ja) | 2006-07-12 | 2006-07-12 | 不揮発性半導体メモリ |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20090031416A KR20090031416A (ko) | 2009-03-25 |
| KR101020846B1 true KR101020846B1 (ko) | 2011-03-09 |
Family
ID=38923287
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020097000601A Expired - Fee Related KR101020846B1 (ko) | 2006-07-12 | 2007-07-12 | 비휘발성 반도체 메모리 및 그 구동방법 |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US7940574B2 (https=) |
| EP (2) | EP2639825A3 (https=) |
| JP (1) | JP5088465B2 (https=) |
| KR (1) | KR101020846B1 (https=) |
| CN (1) | CN101490837B (https=) |
| TW (1) | TW200814068A (https=) |
| WO (1) | WO2008007731A1 (https=) |
Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7906818B2 (en) * | 2008-03-13 | 2011-03-15 | Micron Technology, Inc. | Memory array with a pair of memory-cell strings to a single conductive pillar |
| JP5209674B2 (ja) * | 2010-07-27 | 2013-06-12 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | 不揮発性半導体メモリトランジスタ、および、不揮発性半導体メモリの製造方法 |
| JP5209677B2 (ja) * | 2010-07-29 | 2013-06-12 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | 不揮発性半導体メモリトランジスタ、および、不揮発性半導体メモリの製造方法 |
| US9041092B2 (en) | 2012-09-07 | 2015-05-26 | Unisantis Electronics Singapore Pte. Ltd. | Semiconductor device and method for producing the same |
| KR102054181B1 (ko) | 2013-02-26 | 2019-12-10 | 삼성전자주식회사 | 수직형 메모리 장치 및 그 제조 방법 |
| JP5707003B1 (ja) * | 2013-11-07 | 2015-04-22 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッドUnisantis Electronics Singapore Pte Ltd. | 記憶装置、半導体装置、及び記憶装置、半導体装置の製造方法 |
| WO2018182720A1 (en) * | 2017-03-31 | 2018-10-04 | Intel Corporation | Technique for contact formation in a vertical transistor |
| CN109326604A (zh) * | 2017-08-01 | 2019-02-12 | 华邦电子股份有限公司 | 三维存储器及其操作方法 |
| CN116724354A (zh) * | 2020-12-25 | 2023-09-08 | 新加坡优尼山帝斯电子私人有限公司 | 包含半导体元件的存储器装置 |
| KR20230012697A (ko) * | 2021-07-16 | 2023-01-26 | 에스케이하이닉스 주식회사 | 비휘발성 메모리 장치에 데이터를 삭제하기 위한 장치 및 방법 |
| CN118368901B (zh) * | 2024-06-18 | 2024-08-30 | 杭州积海半导体有限公司 | 一种三维存储器 |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050265079A1 (en) | 2004-05-27 | 2005-12-01 | Kabushiki Kaisha Toshiba | Semiconductor memory device |
Family Cites Families (21)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3046376B2 (ja) * | 1991-03-29 | 2000-05-29 | 株式会社東芝 | 不揮発性半導体メモリ装置 |
| US5386132A (en) | 1992-11-02 | 1995-01-31 | Wong; Chun C. D. | Multimedia storage system with highly compact memory device |
| JP3743453B2 (ja) * | 1993-01-27 | 2006-02-08 | セイコーエプソン株式会社 | 不揮発性半導体記憶装置 |
| JPH06296025A (ja) * | 1993-04-08 | 1994-10-21 | Nippon Steel Corp | 不揮発性半導体メモリ装置 |
| JP3392547B2 (ja) * | 1994-11-21 | 2003-03-31 | 株式会社東芝 | 不揮発性半導体記憶装置 |
| JPH09259591A (ja) * | 1996-03-21 | 1997-10-03 | Ricoh Co Ltd | 不揮発性半導体記憶装置 |
| US5998263A (en) * | 1996-05-16 | 1999-12-07 | Altera Corporation | High-density nonvolatile memory cell |
| US5874760A (en) * | 1997-01-22 | 1999-02-23 | International Business Machines Corporation | 4F-square memory cell having vertical floating-gate transistors with self-aligned shallow trench isolation |
| JP3743189B2 (ja) | 1999-01-27 | 2006-02-08 | 富士通株式会社 | 不揮発性半導体記憶装置及びその製造方法 |
| KR100388179B1 (ko) * | 1999-02-08 | 2003-06-19 | 가부시끼가이샤 도시바 | 불휘발성 반도체 메모리 |
| US6240016B1 (en) * | 1999-12-17 | 2001-05-29 | Advanced Micro Devices, Inc. | Method to reduce read gate disturb for flash EEPROM application |
| KR100356773B1 (ko) * | 2000-02-11 | 2002-10-18 | 삼성전자 주식회사 | 플래쉬 메모리 장치 및 그 형성 방법 |
| JP3963677B2 (ja) * | 2001-06-23 | 2007-08-22 | 富士雄 舛岡 | 半導体記憶装置の製造方法 |
| WO2003028111A1 (en) | 2001-09-25 | 2003-04-03 | Sony Corporation | Nonvolatile semiconductor memory device and its manufacturing method |
| JP4102112B2 (ja) | 2002-06-06 | 2008-06-18 | 株式会社東芝 | 半導体装置及びその製造方法 |
| JP2005012137A (ja) * | 2003-06-23 | 2005-01-13 | National Institute Of Advanced Industrial & Technology | 二重ゲート型不揮発性メモリ素子 |
| DE10352785A1 (de) * | 2003-11-12 | 2005-06-02 | Infineon Technologies Ag | Speichertransistor und Speichereinheit mit asymmetrischem Kanaldotierbereich |
| JP2005191489A (ja) * | 2003-12-26 | 2005-07-14 | Sharp Corp | 半導体記憶装置およびその製造方法 |
| JP2005268418A (ja) * | 2004-03-17 | 2005-09-29 | Fujio Masuoka | 半導体記憶装置及びその製造方法 |
| JP2005260253A (ja) * | 2005-04-04 | 2005-09-22 | Renesas Technology Corp | 半導体集積回路装置およびその製造方法 |
| US8159870B2 (en) * | 2008-04-04 | 2012-04-17 | Qualcomm Incorporated | Array structural design of magnetoresistive random access memory (MRAM) bit cells |
-
2006
- 2006-07-12 JP JP2006191470A patent/JP5088465B2/ja active Active
-
2007
- 2007-07-11 TW TW096125164A patent/TW200814068A/zh unknown
- 2007-07-12 EP EP13170935.4A patent/EP2639825A3/en not_active Withdrawn
- 2007-07-12 CN CN2007800262290A patent/CN101490837B/zh not_active Expired - Fee Related
- 2007-07-12 WO PCT/JP2007/063889 patent/WO2008007731A1/ja not_active Ceased
- 2007-07-12 EP EP07790683A patent/EP2043145A4/en not_active Ceased
- 2007-07-12 KR KR1020097000601A patent/KR101020846B1/ko not_active Expired - Fee Related
-
2009
- 2009-01-12 US US12/319,782 patent/US7940574B2/en not_active Expired - Fee Related
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050265079A1 (en) | 2004-05-27 | 2005-12-01 | Kabushiki Kaisha Toshiba | Semiconductor memory device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101490837B (zh) | 2010-09-29 |
| JP5088465B2 (ja) | 2012-12-05 |
| US20090129171A1 (en) | 2009-05-21 |
| EP2043145A4 (en) | 2010-11-10 |
| EP2639825A2 (en) | 2013-09-18 |
| TW200814068A (en) | 2008-03-16 |
| US7940574B2 (en) | 2011-05-10 |
| EP2639825A3 (en) | 2013-10-16 |
| KR20090031416A (ko) | 2009-03-25 |
| WO2008007731A1 (fr) | 2008-01-17 |
| JP2008021782A (ja) | 2008-01-31 |
| EP2043145A1 (en) | 2009-04-01 |
| CN101490837A (zh) | 2009-07-22 |
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